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SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS070A - NOVEMBER 1988 - REVISED NOVEMBER 1990
D D D
High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54HCT126 . . . J PACKAGE SN74HCT126 . . . D OR N PACKAGE (TOP VIEW)
description
These bus buffers feature independent line drivers with 3-state outputs. Each output is disabled when the associated OE is low. The SN54HCT126 is characterized for operation over the full military temperature range of -55C to 125C. The SN74HCT126 is characterized for operation from -40C to 85C.
FUNCTION TABLE INPUTS OE H H L A H L X OUTPUT Y H L Z
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
SN54HCT126 . . . FK PACKAGE (TOP VIEW)
1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4A NC 4Y NC 3OE
H = high level, L = low level, X = irrelevant
NC - No internal connection
logic symbol
1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 11 8 6 EN 3 1Y
logic diagram, each buffer (positive logic)
OE A 2Y Y
3Y
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1990, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS070A - NOVEMBER 1988 - REVISED NOVEMBER 1990
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . . . . . . . . . . . . 300C Lead temperature 1,6 mm (1/16 in) from case for 10 s: DW or N package . . . . . . . . . . . . . . . . . . . . . . . 260C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54HCT126 MIN VCC VIH VIL VI VO tt TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time Operating free-air temperature VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0 0 0 0 -55 0.8 VCC VCC 500 125 NOM 5 MAX 5.5 SN74HCT126 MIN 4.5 2 0 0 0 0 -40 0.8 VCC VCC 500 85 NOM 5 MAX 5.5 UNIT V V V V V ns C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci TEST CONDITIONS VI = VIH or VIL, IOH = -20 A VI = VIH or VIL, IOH = -6 mA VI = VIH or VIL, IOL = 20 A VI = VIH or VIL, IOL = 6 mA VI = VCC or 0 VO = VCC or 0, VI = VIH or VIL VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC VCC 45V 4.5 4.5 45V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25C TYP MAX 4.499 4.3 0.001 0.17 0.1 0.01 0.1 0.26 100 0.5 8 2.4 10 SN54HCT126 MIN 4.4 3.7 0.1 0.4 1000 10 160 3 10* MAX SN74HCT126 MIN 4.4 3.84 0.1 0.33 1000 5 80 2.9 10 MAX UNIT V V nA A A mA pF
* On products compliant to MIL-STD-883C, Class B, this parameter is not production tested. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS070A - NOVEMBER 1988 - REVISED NOVEMBER 1990
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd d ten tdis di tt FROM (INPUT) A TO (OUTPUT) Y Y Y Any VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25C TYP MAX 15 12 19 15 18 15 8 7 26 23 26 23 26 23 15 14 SN54HCT126 MIN MAX 39 35 39 35 39 35 22 21 SN74HCT126 MIN MAX 33 30 33 30 33 30 19 17 UNIT ns ns ns ns
OE OE
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd d ten tt FROM (INPUT) A TO (OUTPUT) Y Y Any VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25C TYP MAX 21 17 25 21 17 14 36 32 36 32 42 38 SN54HCT126 MIN MAX 58 48 58 48 63 57 SN74HCT126 MIN MAX 46 42 46 42 53 48 UNIT ns ns ns
OE
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 35 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS070A - NOVEMBER 1988 - REVISED NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
VCC PARAMETER ten tPZH tPZL tPHZ tPLZ -- 50 pF or 150 pF 1 k RL 1 k CL 50 pF or 150 pF 50 pF S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open
S1 From Output Under Test CL (see Note A) RL
tdis S2 tpd or tt
LOAD CIRCUIT Input (See Note B) tPZL 3V Input 1.3 V tPLH Output 1.3 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0V tPHL VOH 1.3 V tf VOL Output (See Note C) 1.3 V Output (See Note C) tPZH 1.3 V VOL 10% VOH 90% 0V 3V 1.3 V 1.3 V 0V tPLZ VCC
tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 6 ns, tf 6 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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