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| SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS065C - NOVEMBER 1988 - REVISED JUNE 2000 D D Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN54HCT02 . . . J OR W PACKAGE SN74HCT02 . . . D, DB, OR N PACKAGE (TOP VIEW description These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A * B or Y = A + B in positive logic. The SN54HCT02 is characterized for operation over the full military temperature range of -55C to 125C. The SN74HCT02 is characterized for operation from -40C to 85C. FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y L L H 1Y 1A 1B 2Y 2A 2B GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4Y 4B 4A 3Y 3B 3A SN54HCT02 . . . FK PACKAGE (TOP VIEW) 1A 1Y NC VCC 4Y 1B NC 2Y NC 2A 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4B NC 4A NC 3Y logic symbol 1A 1B 2A 2B 3A 3B 4A 4B 2 3 5 6 8 9 11 12 1 NC - No internal connection 1 1Y 4 2Y 10 3Y 13 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, and W packages. logic diagram, each gate (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright (c) 2000, Texas Instruments Incorporated * DALLAS, TEXAS 75265 2B GND NC 3A 3B 1 SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS065C - NOVEMBER 1988 - REVISED JUNE 2000 absolute maximum ratings over operating free-air temperature range Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54HCT02 MIN VCC VIH VIL VI VO tt Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0 0 0 0 0.8 VCC VCC 500 NOM 5 MAX 5.5 SN74HCT02 MIN 4.5 2 0 0 0 0 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ICC Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = -20 A IOH = -4 mA IOL = 20 A IOL = 4 mA VCC 4.5 45V 4.5 45V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25C TYP MAX 4.499 4.3 0.001 0.17 0.1 0.1 0.26 100 2 2.4 10 SN54HCT02 MIN 4.4 3.7 0.1 0.4 1000 40 3 10 MAX SN74HCT02 MIN 4.4 3.84 0.1 0.33 1000 20 2.9 10 MAX UNIT V V nA A mA pF IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS065C - NOVEMBER 1988 - REVISED JUNE 2000 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd d tt FROM (INPUT) A or B TO (OUTPUT) Y Y VCC 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25C TYP MAX 11 10 9 8 20 18 15 14 SN54HCT02 MIN MAX 30 27 22 20 SN74HCT02 MIN MAX 25 22 19 17 UNIT ns ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 20 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output 3V Input 1.3 V tPLH 1.3 V 10% tPHL Out-of-Phase Output 90% 1.3 V 10% tf 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf LOAD CIRCUIT tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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