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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
D D D D
8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Shift Register Has Direct Clear Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54HC595 . . . J OR W PACKAGE SN74HC595 . . . D OR N PACKAGE (TOP VIEW)
description
The 'HC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. The SN54HC595 is characterized for operation over the full military temperature range of -55C to 125C. The SN74HC595 is characterized for operation from -40C to 85C.
QB QC QD QE QF QG QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC QA SER OE RCLK SRCLK SRCLR QH
SN54HC595 . . . FK PACKAGE (TOP VIEW)
QC QB NC VCC QA QD QE NC QF QG
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
SER OE NC RCLK SRCLK
QH
GND NC Q H
NC - No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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SRCLR
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
FUNCTION TABLE INPUTS SER X X X L H X X X SRCLK X X X X X SRCLR X X L H H H X X RCLK X X X X X X OE H L X X X X X X FUNCTION Outputs QA-QH are disabled. Outputs QA-QH are enabled. Shift register is cleared. First stage of the shift register goes low. Other stages store the data of previous stage, respectively. First stage of the shift register goes high. Other stages store the data of previous stage, respectively. Shift-register state is not changed. Shift-register data is stored in the storage register. Storage-register state is not changed.
logic symbol
13 OE RCLK 12 EN3 C2 SRG8 R C1/ 14 15 1D 2D 3 1 2 3 4 5 6 2D 3 7 9
10 SRCLR SRCLK 11
SER
QA QB QC QD QE QF QG QH QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
logic diagram (positive logic)
OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S
15
QA
2S 2R C2 R
3R C3 3S
1
QB
2S 2R C2 R
3R C3 3S
2
QC
2S 2R C2 R
3R C3 3S
3
QD
2S 2R C2 R
3R C3 3S
4
QE
2S 2R C2 R
3R C3 3S
5
QF
2S 2R C2 R
3R C3 3S
6
QG
2S 2R C2 R Pin numbers shown are for the D, J, N, and W packages.
3R C3 3S
7
QH QH
9
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH'
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IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII
SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54HC595 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 0.5 1.35 1.8 VCC VCC 1000 500 400 NOM 5 MAX 6 SN74HC595 MIN 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 A VOH VI = VIH or VIL QH, IOH = -4 mA QA-QH, IOH = -6 mA QH, IOH = -5.2 mA QA-QH, IOH = -7.8 mA IOL = 20 A VOL VI = VIH or VIL QH, IOL = 4 mA QA-QH, IOL = 6 mA QH, IOL = 5.2 mA QA-QH, IOL = 7.8 mA II IOZ ICC Ci VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 45V 6V 2V 4.5 V 6V 4.5 45V 6V 6V 6V 6V 2V to 6 V 3 MIN 1.9 4.4 5.9 3.98 3.98 5.48 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 4.3 5.8 5.8 0.002 0.001 0.001 0.17 0.17 0.15 0.15 0.1 0.01 0.1 0.1 0.1 0.26 0.26 0.26 0.26 100 0.5 8 10 SN54HC595 MIN 1.9 4.4 5.9 3.7 3.7 5.2 5.2 0.1 0.1 0.1 0.4 0.4 0.4 0.4 1000 10 160 10 MAX SN74HC595 MIN 1.9 4.4 5.9 3.84 3.84 5.34 5.34 0.1 0.1 0.1 0.33 0.33 0.33 0.33 1000 5 80 10 nA A A pF V V MAX UNIT
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V SRCLK or RCLK high or low tw Pulse duration SRCLR low 4.5 V 6V 2V 4.5 V 6V 2V SER before SRCLK 4.5 V 6V 2V SRCLK before RCLK tsu Setup time SRCLR low before RCLK 4.5 V 6V 2V 4.5 V 6V 2V SRCLR high (inactive) before SRCLK 4.5 V 6V 2V th Hold time, SER after SRCLK 4.5 V TA = 25C MIN MAX 0 0 0 80 16 14 80 16 14 100 20 17 75 15 13 50 10 9 50 10 9 0 0 6 31 36 SN54HC595 MIN 0 0 0 120 24 20 120 24 20 150 30 25 113 23 19 75 15 13 75 15 13 0 0 MAX 4.2 21 25 SN74HC595 MIN 0 0 0 100 20 17 100 20 17 125 25 21 94 19 16 65 13 11 60 12 11 0 0 ns ns ns MAX 5 25 29 MHz UNIT
6V 0 0 0 This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead the storage register.
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V SRCLK tpd d RCLK QA-QH QH 4.5 V 6V 2V 4.5 V 6V 2V tPHL SRCLR QH 4.5 V 6V 2V ten OE QA-QH 4.5 V 6V 2V tdis OE QA-QH 4.5 V 6V 2V QA-QH tt QH 4.5 V 6V 2V 4.5 V 6V MIN 6 31 36 TA = 25C TYP MAX 26 38 42 50 17 14 50 17 14 51 18 15 40 15 13 42 23 20 28 8 6 28 8 6 160 32 27 150 30 26 175 35 30 150 30 26 200 40 34 60 12 10 75 15 13 SN54HC595 MIN 4.2 21 25 240 48 41 225 45 38 261 52 44 225 45 38 300 60 51 90 18 15 110 22 19 MAX SN74HC595 MIN 5 25 29 200 40 34 187 37 32 219 44 37 187 37 32 250 50 43 75 15 13 95 19 16 ns ns ns ns ns MHz MAX UNIT
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd RCLK QA-QH 4.5 V 6V 2V ten OE QA-QH 4.5 V 6V 2V tt QA-QH 4.5 V 6V MIN TA = 25C TYP MAX 60 22 19 70 23 19 45 17 13 200 40 34 200 40 34 210 42 36 SN54HC595 MIN MAX 300 60 51 298 60 51 315 63 53 SN74HC595 MIN MAX 250 50 43 250 50 43 265 53 45 ns ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 400 UNIT pF
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS041C - DECEMBER 1982 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
VCC S1 RL PARAMETER ten tPZH tPZL tPHZ tPLZ -- 50 pF or 150 pF 1 k RL 1 k CL 50 pF or 150 pF 50 pF S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open
From Output Under Test CL (see Note A)
Test Point
S2
tdis
tpd or tt LOAD CIRCUIT
High-Level Pulse
VCC 50% tw 50% 0V VCC 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input tsu Data Input 50% 10% 90% tr
50% th 90%
VCC 0V VCC 50% 10% 0 V tf
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC Input 50% tPLH In-Phase Output 50% 10% tPHL Out-ofPhase Output 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr VOH VOL 50% 0V tPHL 90% VOH 50% 10% V OL tf
Output Control (Low-Level Enabling) tPZL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B)
VCC 50% 50% 0V tPLZ VCC 50% 10% VCC VOL VOH 0V tPHZ
50%
90%
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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