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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
D D D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Shrink Small-Outline Package
DGG PACKAGE (TOP VIEW)
description
This 1-bit to 4-bit address register/driver is designed for 1.65-V to 3.6-V VCC operation. This device is ideal for use in applications in which a single address bus is driving four separate memory locations. The SN74ALVCH16832 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is a logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) inputs. Each OE controls two groups of seven outputs. When SEL is a logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal registers. OE operates the same as in the buffer mode. When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high, the outputs are in the high-impedance state.
4Y1 3Y1 GND 2Y1 1Y1 VCC A1 GND A2 GND A3 VCC NC GND CLK OE1 OE2 SEL GND A4 A5 VCC GND A6 GND A7 VCC 4Y7 3Y7 GND 2Y7 1Y7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1Y2 2Y2 GND 3Y2 4Y2 VCC 1Y3 2Y3 GND 3Y3 4Y3 GND VCC GND 1Y4 2Y4 3Y4 4Y4 GND 1Y5 2Y5 VCC 3Y5 4Y5 GND GND VCC 1Y6 2Y6 GND 3Y6 4Y6
NC - No internal connection
Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16832 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
FUNCTION TABLE INPUTS OE H L L L L SEL X H H L L CLK X X X A X L H L H OUTPUT Y Z L H L H
logic diagram (positive logic)
OE1 16 5 17 4 CLK 15 CLK 2 7 A1 D Q 1 18 4Y1 3Y1 2Y1 1Y1
OE2
SEL
To Six Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -4 -12 -12 -24 4 12 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIL
Low-level input voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = 0.58 V VI = 1.07 V II(hold) ( ) VI = 0.7 V VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Ci Control inputs Data inputs VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 33V 4.5 5 25 -25 45 -45 75 -75 500 10 40 750 A A A pF A MIN TYP MAX UNIT VCC-0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5 A V V
VOL
II
Co Outputs VO = VCC or GND 3.3 V 7.5 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, A data before CLK Hold time, A data after CLK MAX VCC = 2.5 V 0.2 V MIN 3.3 2 0.7 MAX 150 3.3 2 0.5 VCC = 2.7 V MIN MAX 150 3.3 1.6 1.1 VCC = 3.3 V 0.3 V MIN MAX 150 MHz ns ns ns UNIT
This information was not available at the time of publication.
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER fmax A tpd ten tdis CLK SEL OE OE Y Y Y FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN TYP VCC = 2.5 V 0.2 V MIN 150 1.2 1.1 1.3 1.1 1.4 4 4.5 5.2 5.1 5.5 MAX VCC = 2.7 V MIN 150 4.1 4.4 5.2 5 4.7 MAX VCC = 3.3 V 0.3 V MIN 150 1.6 1.5 1.7 1.2 1.6 3.6 3.9 4.4 4.3 4.5 ns ns ns MAX MHz UNIT
This information was not available at the time of publication.
operating characteristics, TA = 25C
PARAMETER Power dissipation ca acitance capacitance per register/driver All outputs enabled All outputs disabled CL = 0 0, f = 10 MHz TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP 119 22 VCC = 3.3 V TYP 132 pF 25 UNIT
Cpd d
This information was not available at the time of publication.
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SCES098D - MAY 1997 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT tw 2.7 V Timing Input tsu Data Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V Output Control (low-level enabling) tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 6 V (see Note B) tPZH Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 0V
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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