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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
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Member of the Texas Instruments Widebus +TM Family 5- Switch Connection Between Two Ports TTL-Compatible Input Levels Ioff Supports Partial-Power-Down Mode Operation Active-Clamp Undershoot-Protection Circuit on the I/Os Clamps Undershoots Up to -2 V
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Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Packaged in Plastic Fine-Pitch Ball Grid Array Package
description
The SN74CBTK32245 device provides 32 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the active-clamp circuit is enabled and current from VCC is supplied to clamp the output, preventing the pass transistor from turning on. The device is organized as four 8-bit bus switches, two 16-bit bus switches, or one 32-bit bus switch. When output-enable (OE) input is low, the switch is on and port A is connected to port B. When OE is high, the switch is open and a high-impedance state exists between the two ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74CBTK32245 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 8-bit bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
GKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T 1B2 1B4 1B6 1B8 2B2 2B4 2B6 2B7 3B2 3B4 3B6 3B8 4B2 4B4 4B6 4B7 2 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B8 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B8 3 NC GND VCC GND GND VCC GND NC NC GND VCC GND GND VCC GND NC 4 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 5 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A8 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A8 6 1A2 1A4 1A6 1A8 2A2 2A4 2A6 2A7 3A2 3A4 3A6 3A8 4A2 4A4 4A6 4A7
NC - No internal connection
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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
logic diagram (positive logic)
VCC UC 1A1 A5 VCC UC D6 1A8 A4 1OE 2OE VCC UC D1 1B8 2A8 H4 H5 VCC UC A2 1B1 2A1 E5 VCC UC VCC UC H2 2B8 VCC UC VCC UC E2 2B1
VCC UC 3A1 J5 VCC UC M6 3A8 J4 3OE Undershoot clamp
VCC UC J2 VCC UC M1 3B8 4A8 T5 3B1 4A1 N5
VCC UC
VCC UC N2 4B1
VCC UC
VCC UC T2 4B8
T4 4OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature -40 4 2 0.8 85 MAX 5.5 UNIT V V V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VIKU II Ioff ICC ICC Ci Control inputs Control inputs VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron VCC = 4.5 V TEST CONDITIONS II = -18 mA 0 mA II -50 mA, VI = 5.5 V or GND VI or VO = 0 to 5.5 V VI = VCC or GND, One input at 3.4 V, OE = VCC VI = 2.4 V, VI = 0 II = 15 mA II = 64 mA II = 30 mA IO = 0 Other inputs at VCC or GND 3.5 5.5 14 5 5 20 7 7 OE = 5.5 V MIN TYP MAX -1.2 -2 5 20 60 3.5 UNIT V V A A A mA pF pF
Cio(OFF)
VI = 2.4 V, II = 15 mA 8 12 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified TTL-voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER tpd ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.35 7.4 1.6 VCC = 5 V 0.5 V MIN MAX 0.25 4.9 ns ns UNIT
tdis A or B 7.4 4.2 7.5 ns OE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
undershoot characteristics
PARAMETER TEST CONDITIONS MIN 2 TYP VOH-0.3 MAX UNIT V VOUTU See Figures 1 and 2, and Table 1 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25C. VCC 50 DUT VIN R2 10 pF 0V -2 V 5.5 V R1 VTR
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage Waveform
Table 1. Device Test Conditions
PARAMETER B port under test VIN tw tr tf R1 = R2 VTR VCC VALUE See Figure 1 See Figure 2 20 2 2 100 11 5.5 V ns ns ns k V V UNIT
Other B-port outputs are open
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SN74CBTK32245 32-BIT FET BUS SWITCH WITH ACTIVE-CLAMP UNDERSHOOT-PROTECTION CIRCUIT
SCDS106B - APRIL 2000 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL Output Waveform 1 S1 at 7 V (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B) TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
LOAD CIRCUIT
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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