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SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057D - MARCH 1998 - REVISED MAY 2000
D D D
5- Switch Connection Between Two Ports Isolation Under Power-Off Conditions Packaged in Plastic Small-Outline Transistor (DBV, DCK) Packages
DBV OR DCK PACKAGE (TOP VIEW)
description
The SN74CBTLV1G125 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high.
OE A GND
1 2 3
5 4
VCC B
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74CBTLV1G125 is characterized for operation from -40C to 85C.
FUNCTION TABLE INPUT OE L H FUNCTION A port = B port Disconnect
logic diagram (positive logic)
2 A OE 1 SW 4 B
simplified schematic, each FET switch
A
B
(OE)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
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SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057D - MARCH 1998 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL Supply voltage High-level High level control input voltage Low-level Low level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0.7 0.8 MAX 3.6 UNIT V V V
TA Operating free-air temperature -40 85 C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II Ioff ICC ICC Ci Control inputs Control inputs VCC = 3 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, VCC = 3.6 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 2.3 V, 23V TYP at VCC = 2.5 V 25 ron VCC = 3 V TEST CONDITIONS II = -18 mA VI = VCC or GND VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND 2.5 OE = VCC VI = 0 VI = 1.7 V, VI = 0 II = 64 mA II = 24 mA II = 15 mA II = 64 mA 7 7 7 15 5 10 10 25 7 MIN TYP MAX -1.2 1 10 10 300 UNIT V A A A A pF pF
Cio(OFF)
II = 24 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057D - MARCH 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2)
PARAMETER tpd ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B 1 VCC = 2.5 V 0.2 V MIN MAX 0.35 4 1 VCC = 3.3 V 0.3 V MIN MAX 0.25 4 ns ns UNIT
tdis OE A or B 1 5 1 4.1 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
LOAD CIRCUIT
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057D - MARCH 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT
Output Control tPZL VCC Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B)
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
Input
VCC/2 tPLH
VCC/2 0V tPHL
Output
VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VCC/2 VOL
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 2000, Texas Instruments Incorporated

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