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SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003K - NOVEMBER 1992 - REVISED MAY 2000
D D D D
Functionally Equivalent to QS3383 and QS3L383 5- Switch Connection Between Two Ports TTL-Compatible Input Levels Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic DIPs (JT), and Ceramic Flat (W) Package
SN54CBT3383 . . . JT OR W PACKAGE SN74CBT3383 . . . DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
description
The 'CBT3383 devices provide ten bits of high-speed TTL-compatible bus switching or exchanging. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.
BE 1B1 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 5B2 5A2 5A1 5B1 4B2 4A2 4A1 4B1 3B2 3A2 BX
The devices operate as a 10-bit bus switch or a 5-bit bus exchanger, which provides swapping of the A and B pairs of signals. The bus-exchange function is selected when BX is high. The switches are connected when BE is low. The SN54CBT3383 is characterized for operation over the full military temperature range of -55C to 125C. The SN74CBT3383 is characterized for operation from 0C to 70C.
FUNCTION TABLE INPUTS BE L L H BX L H X INPUTS/OUTPUTS 1A1-5A1 1B1-5B1 1B2-5B2 Z 1A2-5A2 1B2-5B2 1B1-5B1 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003K - NOVEMBER 1992 - REVISED MAY 2000
logic diagram (positive logic)
1A1 3 2 1B1
1A2
4
5
1B2
5A1
21
20
5B1
5A2
22
23
5B2
BE
1
BX
13
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
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POST OFFICE BOX 655303
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SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003K - NOVEMBER 1992 - REVISED MAY 2000
recommended operating conditions (see Note 3)
SN54CBT3383 MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature -55 4.5 2 0.8 125 0 MAX 5.5 SN74CBT3383 MIN 4.5 2 0.8 70 MAX 5.5 UNIT V V V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC ICC Ci Control inputs Control inputs VCC = 4.5 V, VCC = 5.5 V, TEST CONDITIONS II = -18 mA VI = 5.5 V or GND MIN SN54CBT3383 TYP MAX -1.2 5 50 2.5 3 5 BE = VCC BE = VCC VI = 0 II = 64 mA II = 30 mA 5 6 9.2 5 5 7 7 6 MIN SN74CBT3383 TYP MAX -1.2 1 50 2.5 UNIT V A A mA pF pF
VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 3 V or 0 VI = 2.5 V VO = 3 V or 0, VO = 2.5 V, VCC = 4.5 V
Ci (OFF) io(OFF)
ron
VI = 2.4 V, II = 15 mA 10 17 10 15 All typical values are at VCC = 5 V, TA = 25C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the input terminal and the output terminal at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd tpd ten FROM (INPUT) A or B BX BE TO (OUTPUT) B or A A or B A or B 1 1 SN54CBT3383 MIN MAX 1.5 10.2 10.8 1 1 SN74CBT3383 MIN MAX 0.25 9.2 8.6 UNIT ns ns ns
tdis A or B 1 8.2 1 7.5 ns BE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
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3
SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES
SCDS003K - NOVEMBER 1992 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 7 V (see Note B) tPZH VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) 3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT
3V Input 1.5 V 1.5 V 0V tPLH tPHL
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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