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SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
D D D D D D D D D
description
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the 'LVTH374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1999, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
4Q GND CLK 5Q 5D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs
SN54LVTH374 . . . J OR W PACKAGE SN74LVTH374 . . . DB, DW, OR PW PACKAGE (TOP VIEW)
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
SN54LVTH374 . . . FK PACKAGE (TOP VIEW)
1D 1Q OE VCC 2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
1
SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH374 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH374 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic symbol
1 OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 11 3 4 7 8 13 14 17 18 EN C1 1D 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE 1
CLK
11 C1 2
1D
3
1D
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH374 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH374 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH374 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature 200 -55 125 2.7 2 0.8 5.5 -24 48 10 200 -40 85 MAX 3.6 SN74LVTH374 MIN 2.7 2 0.8 5.5 -32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V s/V C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = 5.5 V VI = VCC or GND VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = 3 V VO = 0.5 V 5 -5 100 100 0.19 5 0.19 0.2 3 7 3 7 75 -75 MIN SN54LVTH374 TYP MAX -1.2 VCC-0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 10 1 1 -5 75 -75 500 -750 5 -5 100 100 0.19 5 0.19 0.2 mA pF pF mA A 10 1 1 -5 100 A A 0.2 0.5 0.4 0.5 V VCC-0.2 2.4 MIN SN74LVTH374 TYP MAX -1.2 UNIT V
VOH
V
II
Control inputs Data inputs inp ts
VCC = 0 or 3.6 V, VCC = 3.6 V, VCC = 3 6 V 3.6 VCC = 0, VCC = 3 V
Ioff
II(hold)
Data in uts inputs VCC = 3.6 V,
IOZH IOZL IOZPU IOZPD
VCC = 3.6 V, VCC = 3.6 V,
A A A A
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC
ICC Ci Co
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVTH374 VCC = 3.3 V 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 3.3 1.6 0.8 MAX 150 3.3 2 0.5 VCC = 2.7 V MIN MAX 150 3.3 1.5 0.8 SN74LVTH374 VCC = 3.3 V 0.3 V MIN MAX 150 3.3 2 0 VCC = 2.7 V MIN MAX 150 MHz ns ns ns UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH374 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN fmax tPLH tPHL tPZH tPZL tPHZ 150 CLK Q Q 1.7 1.7 1.2 1.5 1.8 1.9 4.7 4.5 4.9 4.8 4.8 4.9 MAX VCC = 2.7 V MIN 150 5.3 4.6 5.7 5.4 5 5 MAX SN74LVTH374 VCC = 3.3 V 0.3 V MIN 150 1.8 1.8 1.3 1.6 1.9 2 2.9 2.9 2.8 3 3 3.1 4.5 4.2 4.7 4.7 4.6 4.5 TYP MAX VCC = 2.7 V MIN 150 5 4.3 5.6 5.2 4.9 4.6 MAX MHz ns ns ns UNIT
OE
Q OE tPLZ All typical values are at VCC = 3.3 V, TA = 25C.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LVTH374, SN74LVTH374 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS683E - MARCH 1997 - REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
500 S1 6V Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
From Output Under Test CL = 50 pF (see Note A)
2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Input tPLH Output tPHL 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH Output 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL 1.5 V tPZH 1.5 V 1.5 V 1.5 V 0V tPLZ 3V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V
Output Waveform 1 S1 at 6 V (see Note B)
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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