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SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
* * * * *
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Drive Outputs (- 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs
SN54ABT377 . . . J PACKAGE SN74ABT377 . . . DB, DW, OR N PACKAGE (TOP VIEW)
CLKEN 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
description
The ABT377 are 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators. Data (D) input information that meets the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the common clock-enable (CLKEN) input is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the buffered clock (CLK) input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLKEN.
SN54ABT377 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLKEN VCC 2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
The SN74ABT377 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT377 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ABT377 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each flip-flop) INPUTS CLKEN H L L X CLK X H or L D X H L X OUTPUT Q Q0 H L Q0
EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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4Q GND CLK 5Q 5D
Copyright (c) 1994, Texas Instruments Incorporated
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SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
logic symbol
CE CLK 1 11 G1 1C2 2 5 6 9 12 15 16 19
1D 2D 3D 4D 5D 6D 7D 8D
3 4 7 8 13 14 17 18
2D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
CLK 11
CLKEN
1
1D
3 1D C1 2 1Q
To Seven Other Channels
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . . 1.6 W N package . . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT377 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate - 55 0 4.5 2 0.8 VCC - 24 48 5 125 - 40 0 MAX 5.5 SN74ABT377 MIN 4.5 2 0.8 VCC - 32 64 5 85 MAX 5.5 UNIT V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 3: Unused or floating inputs must be held high or low.
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SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL II Ioff ICEX IO ICC ICC Ci VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 24 mA IOH = - 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VI or VO 4.5 V VO = 5.5 V VO = 2.5 V Outputs high Outputs low Outputs high - 50 -100 1 24 MIN 2.5 3 2 2* 0.55 0.55* 1 100 50 -180 250 30 1.5 - 50 50 -180 250 30 1.5 - 50 1 0.55 0.55 1 100 50 -180 250 30 1.5 TA = 25C TYP MAX -1.2 2.5 3 2 2 V A A A mA A mA mA pF SN54ABT377 MIN MAX -1.2 2.5 3 V SN74ABT377 MIN MAX -1.2 UNIT V
VOH
VCC = 5.5 V, IO = 0, , , VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3 * On products compliant to MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V, TA = 25C MIN fclock tw tsu th Clock frequency Pulse duration Setup time before CLK Hold time after CLK CLK high or low Data high or low CLKEN high or low Data high or low CLKEN high or low 0 3.3 2 3 1.8 1.8 MAX 150 SN54ABT377 MIN 0 3.3 2.5 3 1.8 1.8 MAX 150 SN74ABT377 MIN 0 3.3 2 3 1.8 1.8 MAX 150 MHz ns ns ns UNIT
This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 150 CLK Q 2.2 3.1 4.5 5.3 6 6.8 TYP MAX SN54ABT377 MIN 150 2.2 2 7 7.6 MAX SN74ABT377 MIN 150 2.2 3.1 6.5 7.3 MAX MHz ns UNIT
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POST OFFICE BOX 655303
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SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT FOR OUTPUTS 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu 1.5 V th 3V 1.5 V 0V 1.5 V 0V
Input (see Note B) tPLH Output
3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL
Output Control tPZL Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) tPZH
3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH
3.5 V VOL + 0.3 V VOL
Output
1.5 V
[0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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SN54ABT377, SN74ABT377 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SCBS156B - FEBRUARY 1991 - REVISED JULY 1994
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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