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SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
D D D D D D D
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Members of the Texas Instruments SCOPETM Family of Testability Products Octal Test-Integrated Circuits Functionally Equivalent to 'F244 and 'BCT244 in the Normal-Function Mode Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Test Operation Synchronous to Test Access Port (TAP) Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V ) on TMS Pin SCOPETM Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP and HIGHZ - Parallel-Signature Analysis at Inputs - Pseudo-Random Pattern Generation From Outputs - Sample Inputs/Toggle Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)
SN54BCT8244A . . . JT PACKAGE SN74BCT8244A . . . DW OR NT PACKAGE (TOP VIEW)
1OE 1Y1 1Y2 1Y3 1Y4 GND 2Y1 2Y2 2Y3 2Y4 TDO TMS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
2OE 1A1 1A2 1A3 1A4 2A1 VCC 2A2 2A3 2A4 TDI TCK
SN54BCT8244A . . . FK PACKAGE (TOP VIEW)
description
The 'BCT8244A scan test devices with octal buffers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
1A2 1A1 2OE NC 1OE 1Y1 1Y2
5 6 7 8 9
1A3 1A4 2A1 NC VCC 2A2 2A3
4 3 2 1 28 27 26 25 24 23 22 21 10 20 11 19 12 13 14 15 16 17 18
2A4 TDI TCK NC TMS TDO 2Y4
NC - No internal connection
In the normal mode, these devices are functionally equivalent to the 'F244 and 'BCT244 octal buffers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal buffers. In the test mode, the normal operation of the SCOPETM octal buffers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations, as described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1Y3 1Y4 GND NC 2Y1 2Y2 2Y3
Copyright (c) 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
description (continued)
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54BCT8244A is characterized for operation over the full military temperature range of -55C to 125C. The SN74BCT8244A is characterized for operation from 0C to 70C.
FUNCTION TABLE (normal mode, each buffer) INPUTS OE H L L A X L H OUTPUT Y Z L H
logic symbol
SCAN 'BCT8244A TDI TMS TCK-IN TCK-OUT 1OE 2OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 23 22 21 20 19 17 16 15 2 1 1 24 EN1 EN2 2 3 4 5 7 8 9 10 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 TDO 11 TDO
TDI TMS TCK
14 12 13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
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SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
functional block diagram
Boundary-Scan Register VCC 1OE 1
VCC 1A1 23 One of Four Channels 2 1Y1
VCC 2OE 24
VCC 2A1 19 One of Four Channels 7 2Y1
Bypass Register
Boundary- Control Register VCC TDI 14 VCC TMS 12 VCC TCK 13 TAP Controller Instruction Register
VCC 11 TDO
Pin numbers shown are for the DW, JT, and NT packages.
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SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
Terminal Functions
TERMINAL NAME 1A1-1A4, 2A1-2A4 GND 1OE, 2OE DESCRIPTION Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs high if left unconnected. Ground Normal-function output-enable inputs. See function table for normal-mode logic. Internal pullups force these inputs high if left unconnected. Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces TCK to a high level if left unconnected. Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active and is not driven from an external source. Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS. Supply voltage Normal-function data outputs. See function table for normal-mode logic.
TCK
TDI
TDO
TMS
VCC 1Y1-1Y4, 2Y1-2Y4
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test architecture
Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset TMS = H TMS = L TMS = H Run-Test /Idle TMS = L Select-DR-Scan TMS = L TMS = H Capture-DR TMS = L Shift-DR TMS = L TMS = H TMS = H Exit1-DR TMS = L Pause-DR TMS = L TMS = H TMS = L Exit2-DR TMS = H Update-DR TMS = H TMS = L TMS = L Exit2-IR TMS = H Update-IR TMS = H TMS = L TMS = H Exit1-IR TMS = L Pause-IR TMS = L TMS = H TMS = H TMS = H Capture-IR TMS = L Shift-IR TMS = L TMS = H Select-IR-Scan TMS = L TMS = H
Figure 1. TAP-Controller State Diagram
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state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the 'BCT8244A, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation. Run-Test / Idle The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register may capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state. Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
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Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data. Update-DR If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state. Capture-IR When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the 'BCT8244A, the status value loaded in the Capture-IR state is the fixed binary value 10000001. Shift-IR Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register. While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state. Exit1-IR, Exit2-IR The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state. Pause-IR No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data. Update-IR The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.
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register overview
With the exception of the bypass register, any test register may be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. Table 2 lists the instructions supported by the 'BCT8244A. The even-parity feature specified for SCOPETM devices is not supported in this device. Bit 7 of the instruction opcode is a don't-care bit. Any instructions that are defined for SCOPETM devices but are not supported by this device default to BYPASS. During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.
Bit 7 (MSB) Don't Care Bit 0 (LSB)
TDI
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDO
Figure 2. Instruction Register Order of Scan
data register description
boundary-scan register The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function output pin. The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input terminals. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents of the BSR are not changed in Test-Logic-Reset. The BSR order of scan is from TDI through bits 17-0 to TDO. Table 1 shows the BSR bits and their associated device pin signals.
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Table 1. Boundary-Scan Register Configuration
BSR BIT NUMBER 17 16 - - - - - - DEVICE SIGNAL 1OE 2OE - - - - - - BSR BIT NUMBER 15 14 13 12 11 10 9 8 DEVICE SIGNAL 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 BSR BIT NUMBER 7 6 5 4 3 2 1 0 DEVICE SIGNAL 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
boundary-control register The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPETM instruction set. Such operations include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.
Bit 1 (MSB) Bit 0 (LSB)
TDI
TDO
Figure 3. Boundary-Control Register Order of Scan bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
TDI
Bit 0
TDO
Figure 4. Bypass Register Order of Scan
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instruction-register opcode description
The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of each instruction. Table 2. Instruction-Register Opcodes
BINARY CODE BIT 7 BIT 0 MSB LSB X0000000 X0000001 X0000010 X0000011 X0000100 X0000101 X0000110 X0000111 X0001000 X0001001 X0001010 X0001011 X0001100 X0001101 X0001110 X0001111 All others SCOPE OPCODE EXTEST/INTEST BYPASS SAMPLE/PRELOAD INTEST/EXTEST BYPASS BYPASS HIGHZ (TRIBYP) CLAMP (SETBYP) BYPASS RUNT READBN READBT CELLTST TOPHIP SCANCN SCANCT BYPASS DESCRIPTION Boundary scan Bypass scan Sample boundary Boundary scan Bypass scan Bypass scan Control boundary to high impedance Control boundary to 1/0 Bypass scan Boundary run test Boundary read Boundary read Boundary self test Boundary toggle outputs Boundary-control register scan Boundary-control register scan Bypass scan SELECTED DATA REGISTER Boundary scan Bypass Boundary scan Boundary scan Bypass Bypass Bypass Bypass Bypass Bypass Boundary scan Boundary scan Boundary scan Bypass Boundary control Boundary control Bypass MODE Test Normal Normal Test Normal Normal Modified test Test Normal Test Normal Test Normal Test Normal Test Normal
Bit 7 is a don't-care bit; X = don't care. The BYPASS instruction is executed in lieu of a SCOPETM instruction that is not supported in the 'BCT8244A.
boundary scan This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into the output BSCs is applied to the device output terminals. The device operates in the test mode. bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the normal mode.
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control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device output terminals are placed in the high-impedance state, the device input terminals remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output terminals. The device operates in the test mode. boundary run test The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG). boundary read The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation. boundary self test The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode. boundary toggle outputs The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured in the input BSCs. The device operates in the test mode. boundary-control-register scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed.
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boundary-control register opcode description
The BCR opcodes are decoded from BCR bits 1-0, as shown in Table 3. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and show the associated PSA and PRPG algorithms. Table 3. Boundary-Control Register Opcodes
BINARY CODE BIT 1 BIT 0 MSB LSB 00 01 10 11 DESCRIPTION Sample inputs/toggle outputs (TOPSIP) Pseudo-random pattern generation / 16-bit mode (PRPG) Parallel-signature analysis/16-bit mode (PSA) Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
It should be noted, in general, that while the control input BSCs (bits 17-16) are not included in the sample, toggle, PSA, or PRPG algorithms, the output-enable BSCs (bits 17-16 of the BSR) do control the drive state (active or high impedance) of the selected device output terminals. sample inputs / toggle outputs (TOPSIP) Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK. pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK. This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns.
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
= 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
Figure 5. 16-Bit PRPG Configuration
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parallel-signature analysis (PSA) Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
=
=
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 6. 16-Bit PSA Configuration simultaneous PSA and PRPG (PSA / PRPG) Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns.
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
=
= 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
Figure 7. 8-Bit PSA / PRPG Configuration
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timing description
All test operations of the 'BCT8244A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK. A simple timing example is shown in Figure 8. In this example, the TAP controller begins in the Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 details the operation of the test circuitry during each TCK cycle. Table 4. Explanation of Timing Example
TCK CYCLE(S) 1 2 3 4 5 6 TAP STATE AFTER TCK Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state. TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR. TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state. TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO. TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. In general, the selected data register is updated with the new data on the falling edge of TCK. DESCRIPTION TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state.
7-13
Shift-IR
14 15 16 17 18 19-20 21 22 23 24 25
Exit1-IR Update-IR Select-DR-Scan Capture-DR Shift-DR Shift-DR Exit1-DR Update-DR Select-DR-Scan Select-IR-Scan Test-Logic-Reset
Test operation completed
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SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
1 TCK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TMS
TDI
TDO
Test-Logic-Reset
TAP Controller State
3-State (TDO) or Don't Care (TDI)
Figure 8. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI: except TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 12 V Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC Input clamp current, IIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Current into any output in the low state: SN54BCT8244A (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SN54BCT8244A (any Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74BCT8244A (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74BCT8244A (any Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input voltage rating may be exceeded if the input clamp-current rating is observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
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Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Select-DR-Scan
Select-DR-Scan
Select-IR-Scan
Run-Test/Idle
Exit1-IR
Capture-IR
Update-IR
Exit1-DR
Capture-DR
Update-DR
Shift-DR
IIIIII IIIIII IIIIII IIIIII
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IIIII IIIII IIIII IIIII
II II
IIIIIIII IIIIIIII IIIIIIII IIIIIIII
Shift-IR
SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
recommended operating conditions
SN54BCT8244A MIN VCC VIH VIHH VIL IIK IOH IOL TA Supply voltage High-level input voltage Double-high-level input voltage Low-level input voltage Input clamp current High-level High level output current Low-level Low level output current Operating free-air temperature TDO Any Y TDO Any Y -55 TMS 4.5 2 10 12 0.8 -18 -3 -12 20 48 125 0 NOM 5 MAX 5.5 SN74BCT8244A MIN 4.5 2 10 12 0.8 -18 -3 -15 24 64 70 NOM 5 MAX 5.5 UNIT V V V V mA mA mA C
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SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS
SCBS042E - FEBRUARY 1990 - REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.75 V, Any Y VOH VCC = 4.75 V, TDO VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 5.5 V, TMS Any Y TDO Any Y TDO VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 V, VCC = 5 5 V 5.5 V, VCC = 0 to 2 V, VCC = 2 V to 0, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VCC = 5 V, VCC = 5 V, VCC = 4.5 V TEST CONDITIONS II = -18 mA IOH = -3 mA IOH = -3 mA IOH = -12 mA IOH = - 15 mA IOH = -1 mA IOH = -1 mA IOH = -3 mA IOL = 48 mA IOL = 64 mA IOL = 20 mA IOL = 24 mA VI = 5.5 V VI = 2.7 V VI = 10 V VI = 0.5 V VO = 2.7 V 27 VO = 0.5 V 05 VO = 0.5 V or 2.7 V VO = 0.5 V or 2.7 V VI or VO 4.5 V VO = 0 Outputs high ICC Ci Co Outputs open Outputs low Outputs disabled VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V -100 3.5 35 1.5 10 18 -1 -30 -1 -30 MIN SN54BCT8244A TYP MAX -1.2 2.7 2.4 2 2.7 2.5 2.4 3.4 3.4 3.2 2 3.4 3.4 3.3 0.38 0.3 0.55 0.42 0.5 0.35 0.1 -35 -70 -35 -70 -100 1 -200 50 -100 -50 -200 250 250 250 -225 7.5 52 3.5 -100 3.5 35 1.5 10 18 -30 -70 -1 -35 -30 -70 -1 -35 0.5 0.1 -100 1 -200 50 -100 -50 -200 250 250 250 -225 7.5 52 3.5 pF pF mA mA A mA A A A A A A mA 0.55 V 2.7 2.5 2.4 3.1 3.4 3.4 3.3 V 2.7 2.4 3.4 3.4 MIN SN74BCT8244A TYP MAX -1.2 UNIT V
Any Y VOL TDO II IIH IIHH IIL IOZH IOZL IOZPU IOZPD Ioff IOS
All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
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timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9)
VCC = 5 V, TA = 25C MIN fclock tw Clock frequency Pulse duration TCK TCK high or low TMS double high Any A before TCK tsu Setup time Any OE before TCK TDI before TCK TMS before TCK Any A after TCK th Hold time Any OE after TCK TDI after TCK TMS after TCK 0 25 50* 6 6 6 12 4.5 4.5 4.5 0 MAX 20 SN54BCT8244A MIN 0 25 50* 6 6 6 12 4.5 4.5 4.5 0 100* MAX 20 SN74BCT8244A MIN 0 25 50 6 6 6 12 4.5 4.5 4.5 0 100 ns ns ns MAX 20 MHz ns UNIT
td Delay time Power up to TCK 100* * On products compliant to MIL-PRF-38535, this parameter is not production tested.
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switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 9)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 2 2 3 3.5 2.5 2.5 TYP 5.4 5.2 6 7 6 5.5 MAX 7 7 8 9 8 8 SN54BCT8244A MIN 2 2 3 3.5 2.5 2.5 MAX 9 9 10 12 10 10 SN74BCT8244A MIN 2 2 3 3.5 2.5 2.5 MAX 8.5 8.5 9.5 11 9 9 ns ns ns UNIT
A
Y Y Y
OE OE
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9)
PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TCK TCK TCK Y TDO Y Y TDO Y Y TDO Y TO (OUTPUT) VCC = 5 V, TA = 25C MIN 20 6 6 3.5 3.5 7.5 7.5 6.5 7 3.5 4 8 8 6 6 3 3 8 8 13 12.5 7.6 8 16.5 17 14 15 7.6 8.5 18 19 14 14 8 7.5 18.5 18.5 15.5 15.5 10.5 10.5 20 21 17 20 10.5 11 22 25 18 17 11.5 10 22 22 TYP MAX SN54BCT8244A MIN 20 6 6 3.5 3.5 7.5 7.5 6.5 7 3.5 4 8 8 6 6 3 3 8 8 21.5 21.5 14 13 28 29 24 26 11.5 13.5 30 32 24 23 13 13 31 31 MAX SN74BCT8244A MIN 20 6 6 3.5 3.5 7.5 7.5 6.5 7 3.5 4 8 8 6 6 3 3 8 8 20 20 13 12 24 25 21 23 11 12.5 27 29 22 21 12.5 12 27 27 MAX MHz ns ns ns ns ns ns ns ns ns UNIT
TCK TCK TCK
TCK TCK TCK
TCK
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PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.) S1 Open (all others)
R1 From Output Under Test CL (see Note A) R2 RL = R1 = R2 Test Point From Output Under Test CL (see Note A) R1 Test Point
LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V tw 3V Low-Level Pulse 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V 0V
Timing Input
3V 1.5 V 0V tsu th 3V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH 1.5 V 1.5 V VOL
Data Input
Input
Output Control (low-level enable) tPZL Waveform 1 (see Note B) tPZH Waveform 2 (see Note B)
1.5 V
1.5 V 0V tPLZ
tPLH In-Phase Output 1.5 V
1.5 V
3.5 V VOL
tPHL Out-of-Phase Output
tPHZ
0.3 V VOH
1.5 V
0.3 V 0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, tr = tf 2.5 ns, duty cycle = 50%. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 9. Load Circuits and Voltage Waveforms
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