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| SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A - JANUARY 1993 - REVISED JULY 1995 D D D D D EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) description This octal registered transceiver is designed for 2.7-V to 3.6-V VCC operation. LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB The SN74LVC543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B but uses CEBA, LEBA, and OEBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC543 is characterized for operation from - 40C to 85C. FUNCTION TABLE INPUTS CEAB H X L L LEAB X X H L OEAB X H L L A X X X L OUTPUT B Z Z B0 L L L L H H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A - JANUARY 1993 - REVISED JULY 1995 logic symbol 2 OEBA 23 CEBA 1 LEBA 13 OEAB 11 CEAB 14 LEAB A1 3 3 4 5 6 7 8 9 10 6D 1 1 1EN3 G1 1C5 2EN4 G2 2C6 5D 4 22 B1 A2 A3 A4 A5 A6 A7 A8 21 20 19 18 17 16 15 B2 B3 B4 B5 B6 B7 B8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 3 C1 1D 22 B1 C1 1D To Seven Other Channels 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A - JANUARY 1993 - REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High level output current High-level Low-level Low level output current Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Control inputs Data inputs 2.7 2 0.8 0 0 0 5.5 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A - JANUARY 1993 - REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC Ci IOL = 12 mA IOL = 24 mA VI = 5.5 V or GND VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 4.6 7.2 MIN VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.55 5 10 20 500 A A A A pF pF V TYP MAX UNIT V nICC Control inputs VI = VCC or GND 3.3 V Cio A or B ports VO = VCC or GND 3.3 V For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC = 3.3 V 0.3 V MIN tw tsu th Pulse duration Setup time, data before LE or CE Hold time, data after LE or CE 4 1.5 2.5 MAX VCC = 2.7 V MIN 4 1.5 2.5 MAX ns ns ns UNIT switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) A or B LE OE CE OE CE A or B TO (OUTPUT) B or A VCC = 3.3 V 0.3 V MIN 1.5 1.5 1.5 1.5 1.5 1.5 MAX 8 9.5 8.5 9 8.5 9 VCC = 2.7 V MIN MAX 9 10.5 9.5 10 9.5 10 ns UNIT tpd d ten tdis di A or B ns ns 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS299A - JANUARY 1993 - REVISED JULY 1995 operating characteristics, VCC = 3.3 V, TA = 25C PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 32 4.6 UNIT pF PARAMETER MEASUREMENT INFORMATION 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND LOAD CIRCUIT FOR OUTPUTS 2.7 V Timing Input 1.5 V 0V tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V 2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control 1.5 V [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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