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SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS296B - JANUARY 1993 - REVISED NOVEMBER 1994
* * * *
EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
description
This octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
The SN74LVC374 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74LVC374 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
1
SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS296B - JANUARY 1993 - REVISED NOVEMBER 1994
logic symbol
OE CLK 1 11 EN C1 2 5 6 9 12 15 16 19
logic diagram (positive logic)
OE CLK 1D 1 11 C1 3 2 1Q
1D 2D 3D 4D 5D 6D 7D 8D
3 4 7 8 13 14 17 18
1D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
1D
To Seven Other Channels
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . 0.7 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 4.6 V maximum. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS296B - JANUARY 1993 - REVISED NOVEMBER 1994
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low level output current Low-level Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 3: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC IOL = 12 mA IOL = 24 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VCC = 3 V to 3.6 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND IO = 0 One input at VCC - 0.6 V, TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V TA = - 40C to 85C MIN TYP MAX VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 10 20 500 3.3 V 3.3 V 5.5 5.8 A A A A pF pF V UNIT
V
nICC
Ci Co
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 0 5 2 2 MAX 100 VCC = 2.7 V MIN 0 5 2 2 MAX 80 MHz ns ns ns UNIT
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3
SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS296B - JANUARY 1993 - REVISED NOVEMBER 1994
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd ten tdis FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN TYP MAX 100 CLK OE OE Q Q Q 1.5 1.5 1.5 150 4.9 4.1 4.2 8.5 8.5 7.5 VCC = 2.7 V MIN MAX 80 1.5 1.5 1.5 9.5 9.5 8.5 UNIT MHz ns ns ns
operating characteristics, VCC = 3.3 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 18 9 UNIT pF
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS296B - JANUARY 1993 - REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS 2.7 V Timing Input tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control tPZL VOH Output 1.5 V 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note C) Output Waveform 1 S1 at 6 V (see Note C) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH VOL + 0.3 V 3V VOL 1.5 V 1.5 V 0V 1.5 V 0V
Input (see Note B) tPLH
2.7 V 1.5 V 1.5 V 0V tPHL
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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