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RF2617
0
Typical Applications * 3V CDMA/FM Cellular Systems * Supports Dual-Mode AMPS/CDMA * Supports Dual-Mode TACS/CDMA Product Description
The RF2617 is a complete AGC amplifier designed for the receive section of 3V dual-mode CDMA/FM cellular applications. It is designed to amplify IF signals while providing more than 90dB of gain control range. Noise Figure, IP3, and other specifications are designed to be compatible with the IS-95 Interim Standard for CDMA cellular communications. This circuit is designed as part of the RFMD CDMA Chip Set, consisting of a Transmit IF AGC Amp, a Transmit Upconverter, a Receive LNA/Mixer, and this Receive IF AGC Amp. The IC is manufactured on an advanced high frequency Silicon Bipolar process, and is packaged in a standard miniature 16-lead plastic SSOP package.
3V CDMA/FM RECEIVE AGC AMPLIFIER
* General Purpose Linear IF Amplifier * Commercial and Consumer Systems * Portable Battery Powered Equipment
IG N S
0.157 0.150 0.012 0.008 0.196 0.189 0.025
-A0.0098 0.0040
E S
0.2440 0.2284
0.0688 0.0532
D
8 MAX 0MIN
0.050 0.016
0.0098 0.0075
Optimum Technology Matching(R) Applied
N E
GaAs MESFET Si CMOS SiGe Bi-CMOS
GAIN CONTROL 16 GC 15 VCC 14 VCC 13 VCC 12 GND 11 GND 10 OUT+ 9 OUT-
W
NOTES: 1. Shaded lead is Pin 1. 2. All dimensions are excluding mold flash. 3. Lead coplanarity - 0.005 with respect to datum "A".
!
Package Style: SSOP-16
Si BJT Si Bi-CMOS InGaP/HBT
GaAs HBT SiGe HBT GaN HEMT
Features * Supports Dual Mode Operation * -48dB to +48dB Gain Control Range * Single 3V Power Supply * Digitally Selectable Inputs * -2dBm Input IP3 * 12MHz to 285MHz Operation
CDMA+ 1 CDMA- 2 GND 3 FM+ 4 FM- 5
N O T
FO
IN SEL.
R
GND 6 IN SELECT 7 NC 8
Ordering Information
RF2617 RF2617 PCBA 3V CDMA/FM Receive AGC Amplifier Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
NOT FOR NEW DESIGNS
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev B5 021008
10-25
RF2617
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltage Input RF Power Operating Ambient Temperature Storage Temperature
Value
-0.5 to +7.0 -0.5 to +5.0 +10 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Specification Min. Typ. Max.
Unit
Condition
T=25C, 85MHz, VCC =3.0V, ZS =500, ZL =500, 500 External CDMA Input Terminating Resistor, 500 External Output Terminating Resistor (Effective ZS =333, Effective ZL =250) (See application schematic).
Overall
W
1 850 30
Frequency Range CDMA Maximum Gain CDMA Minimum Gain FM Maximum Gain FM Minimum Gain Gain Slope Gain Control Voltage Range Gain Control Input Impedance Noise Figure Input IP3 Stability (Max VSWR)
-45
+45
-45
D
8 15 16
IF Input
Input Impedance Input Impedance CDMA to FM Isolation
N E
2.7 to 3.3 13 14
-44 -4 10:1
Power Supply
Voltage Current Consumption Current Consumption
R
FO
N O T
10-26
E S
k dB V mA mA
+45
12 to 285 +48 -48 +49 -48 57 0 to 3 30 5 -40 -2
MHz dB dB dB dB dB/V VDC k dB dBm dBm
IG N S
CDMA, differential FM, single-ended
VGC =2.4V VGC =0.3V VGC =2.4V VGC =0.3V Measured in 0.5V increments Source impedance of 4.7k
At maximum gain and 85MHz At +40dB gain, referenced to 500 At minimum gain, referenced to 500 Spurious<-70dBm
Minimum gain, VCC =3.0V Maximum gain, VCC =3.0V
Rev B5 021008
RF2617
Pin 1 Function CDMA+ Description
CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level other than VCC present. A DC to connection to VCC is acceptable. For single-ended input operation, one pin is used as an input and the other CDMA input is AC-coupled to ground. The balanced input impedance is 1k, while the single-ended input impedance is 500. Same as pin 2, except complementary input. Ground connection. For best performance, keep traces physically short and connect immediately to ground plane. FM balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other FM input is AC-coupled to ground. The balanced input impedance is 1.7k, while the single-ended input impedance is 850.
Interface Schematic
BIAS
700 CDMA+
700 CDMA-
2 3 4
CDMAGND FM+
See pin 1.
IG N S
FM+
BIAS
650
650 FM-
8 9
NC OUT-
Selects which IF input (CDMA or FM) is used. This is a digitally controlled input. A logic "high" selects the CDMA input amplifier. A logic "low" selects the FM input amplifier. The threshold voltage is approximately 1.3V. No connection pin. This pin is internally biased and should not be connected to any external circuitry, including ground or VCC.
E S
5 6 7
FMGND IN SELECT
Same as pin 4, except complementary input. Same as pin 3.
See pin 4.
20 k IN SELECT
N O T
14 15 16
FO
10 11 12 13
OUT+ GND GND VCC
Balanced output pin. This is an open-collector output, designed to operate into a 250 balanced load. The load sets the operating impedOUT+ ance, but an external choke or matching inductor to VCC must also be supplied in order to correctly bias this output. This bias inductor is typically incorporated in the matching network between the output and next stage. Because this pin is biased to VCC, a DC-blocking capacitor must be used if the next stage's input has a DC path to ground. Same as pin 9, except complementary output. See pin 9.
W
D
OUT-
VCC VCC GC
R
Same as pin 3. Same as pin 3. Supply Voltage pin. External bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 13. Same as pin 13. Analog gain adjustment for all amplifiers. Valid control ranges are from 0V to 3.0V. Maximum gain is selected with 3.0V. Minimum gain is selected with 0V. These voltages are only valid for a 4.7k DC source impedance.
VCC
N E
12.7 k 23.5 k 15 k
Rev B5 021008
10-27
RF2617
Application Schematic
Measurement Reference Plane
ZS=500 CDMA IF Filter CDMA+ CDMAZ IN, EFF=500 FM IF Filter FM IN
Z S, EFF=333 1 2 Z IN=1 k 3 Z IN=850 4 10 nF IN SEL. GAIN CONTROL 4.7 k 16 15 GC
R1 1 k
IG N S
14 13 12 11 10 9 10 nF C1 L1 C2
10 nF
ZS=850
5 6
VCC
ZLOAD=500 OUT+
IF IN SELECT
7 NC 8
E S
R2 500
C2 C2 OUTL1
D
ZLOAD,EFF=250
C1
VCC
Measurement Reference Plane
W
R1 sets the CDMA balanced input impedance. The effective input impedance is then 500 . R2 sets the balanced output impedance to 500 . L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network of the load impedance is not 500 . Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit at the IF when the load impedance is 500 . 10 nF ZOUT=500
N O T
10-28
FO
R
N E
Rev B5 021008
RF2617
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
L2 390 nH J1 CDMA 50 strip T1 C3 15 pF C4 15 pF 50 strip
L1 390 nH
C1 10 nF C2 10 nF R1 1 k 1 2 GAIN CONTROL 16 15 IN SEL. 14 C14 10 nF P1-3 C13 10 nF
R3 4.7 k P1-1
J2 FM
C6 10 pF L3 330 nH C5 10 nF
3 4 5 C7 10 nF 6 7 C8 10 nF 8
IG N S
13 12 11 10 9 C12 15 pF C11 15 pF R2 500
P2-1
T2
50 strip
J3 OUT
P1-1
1 2
GC GND VCC
P2-1
1 2
SELECT GND
2617400-
E S
P1
P2
L4 390 nH C9 10 nF
L5 390 nH C10 10 nF
P1-3
P1-3
3
NC
3
N O T
Rev B5 021008
FO
R
N E
W
D
10-29
RF2617
Evaluation Board Layout
N O T
10-30
FO
R
N E
W
D
E S
Rev B5 021008
IG N S
RF2617
Gain versus Gain Control Voltage
60.0 50.0 40.0 30.0 20.0
Gain versus Gain Control Voltage
60.0 50.0 40.0 30.0 20.0
(VCC=2.7 V, 85 MHz)
(VCC=3.0 V, 85 MHz)
Gain (dB)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 0.0 0.5 1.0 1.5 2.0 2.5 -30 C +25 C +80 C
Gain (dB)
10.0
10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0
IG N S
0.5 1.0 1.5
-30 C +25 C +80 C 2.0 2.5
0.0
GC (V)
GC (V)
E S
10.0
Gain versus Gain Control Voltage
60.0 50.0 40.0 30.0 20.0
Input IP3 versus Gain
(VCC=2.7 V, 85 MHz)
-30 C +25 C +80 C
(VCC=3.3 V, 85 MHz)
0.0
W N E R
0.0 0.5 1.0 1.5 2.0 -30 C +25 C +80 C 2.5
Gain (dB)
10.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0
IIP3 (dBm)
D
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0
FO
GC (V)
Gain (dBm)
Input IP3 versus Gain
(VCC=3.0 V, 85 MHz)
-30 C +25 C +80 C 0.0 10.0
Input IP3 versus Gain
(VCC=3.3 V, 85 MHz)
-30 C +25 C +80 C
10.0
N O T
0.0 -10.0
-10.0
IIP3 (dBm)
-20.0
IIP3 (dBm)
-20.0 0.0 20.0 40.0 60.0
-20.0
-30.0
-30.0
-40.0
-40.0
-50.0
-50.0
-60.0 -60.0 -40.0
-60.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0
Gain (dBm)
Gain (dBm)
Rev B5 021008
10-31
RF2617
Output IP3 versus Gain
10.0
Output IP3 versus Gain
10.0
(VCC=2.7 V, 85 MHz)
(VCC=3.0 V, 85 MHz)
0.0
0.0
-10.0
-10.0
OIP3 (dBm)
-20.0
OIP3 (dBm)
-20.0
-30.0
-30.0
-30 C -50.0 +25 C +80 C -60.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 -60.0 -60.0 -50.0
IG N S
-40.0 -20.0 0.0 20.0
-40.0
-40.0
-30 C +25 C +80 C 40.0 60.0
Gain (dBm)
Gain (dBm)
10.0
(VCC=3.3 V, 85 MHz)
E S
60.0
Output IP3 versus Gain
Noise Figure versus Gain
(VCC=2.7 V, 85 MHz)
-30 C +25 C +80 C
0.0
-10.0
OIP3 (dBm)
NF (dB)
-20.0
W N E
-30 C +25 C
-30.0
-40.0
-50.0
R
0.0 20.0
+80 C 0.0 40.0 60.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0
-60.0 -60.0 -40.0 -20.0
FO
Gain (dBm)
D
40.0 30.0 20.0 10.0
50.0
Gain (dB)
Noise Figure versus Gain
(VCC=3.0 V, 85 MHz)
-30 C +25 C +80 C 50.0 60.0
Noise Figure versus Gain
(VCC=3.3 V, 85 MHz)
-30 C +25 C +80 C
60.0
N O T
50.0 40.0
40.0
NF (dB)
30.0
NF (dB)
0.0 20.0 40.0 60.0
30.0
20.0
20.0
10.0
10.0
0.0 -60.0 -40.0 -20.0
0.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0
Gain (dB)
Gain (dB)
10-32
Rev B5 021008

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