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QL903M QuickMIPSTM Data Sheet
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QuickMIPS Embedded Standard Product (ESP) Family
Device Highlights
CPU Core
* 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) * 1.3 Dhrystone MIPS per MHz * MDU supports MAC instructions for DSP functions * 16 KB of instruction cache (4-way set associative) * 16 KB of data cache (4-way set associative), lockable on a per line basis
Two Ethernet Controllers
* Two 10/100 MACs * Provides MII connection to external transceivers/devices
Two UARTs
* One with modem control signals * Both with IRDA-compliant signals
Four General Purpose 16-bit Timer/Counters
* 16-bit prescaler to increase timer/counter delay * Four modes of operation: decrement, increment, interval, and Pulse Width Modulation (PWM) * Operation from the System Bus clock or a clock source supplied from the Programmable Fabric
SDRAM Memory Controller
* Support for PC-100 type SDRAMs, up to 256 MB total * Two chip selects * Operates at up to one-half CPU pipeline speed * Support for x16 and x32 external memory bus configurations
System SRAM
* 16 KB accessible by all System Bus masters or the Programmable Fabric Figure 1: QL903M Block Diagram
I/O Peripheral Controller
* Direct support for SRAM, EPROM and Flash * 8-bit, 16-bit and 32-bit device widths supported * Eight independent chip selects
18 ECU Blocks (8x8 Multiply, 16-bit carry/add)
PCI Controller
* 32-bit v2.2 compatible * Up to 66 MHz operation * Supports host and satellite configurations * Dedicated DMA channels for transmit and receive bus transactions * Support for external bus master arbitration (through FPGA library provided by QuickLogic)
MII 10/100 Ethernet MII
ViaLink Programmable Fabric
18 RAM Blocks (128x18 and 256x9)
10/100 Ethernet
AHB Master
AHB Slave
APB Slave (3)
16K SRAM
32-bit System Bus (AMBA) Low Speed Peripherals 16-bit Timer
(X4)
ICU
UART
(X2)
PCI Controller
32-bit MIPS 4Kc
16K 16K D-Cache I-Cache
Memory Controller
PCI 32/66
SDRAM SRAM
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QL903M QuickMIPSTM Data Sheet Rev. H
High Performance 32-bit System Bus (AMBA Bus)
* Operates at one-half, one-third, or one-fourth of CPU pipeline speed * One 32-bit AHB master port/one 32-bit AHB slave port to programmable Fabric * Three 32-bit APB slave ports in the programmable Fabric
Flexible Programmable Fabric
* 1152 logic cells (316 K system gates) * 124 I/O pins * 1.95 V Vcc, 1.8/2.5/3.3 V drive capable I/O * 2,510 dedicated flip-flops * IEEE 1149.1 boundary scan testing compliant
Dual-Port SRAM Modules
* Eighteen 2,304 bit Dual-Port High Performance SRAM Blocks * 41,472 embedded RAM bits * RAM/ROM/FIFO Wizard for automatic configuration * Configurable and cascadable
Programmable I/O
* High performance I/O cell with fast clock-to-out time * Programmable Slew Rate Control * Programmable I/O Standards: LVTTL, LVCMOS, LVCMOS18, PCI, GTL+, SSTL2, and SSTL3 Independent I/O Banks capable of supporting multiple standards in one device I/O Register Configurations: Input, Output, Output Enable (OE)
Advanced Clock Network
* Multiple dedicated Low Skew Clock Networks * High drive input-only networks * Quadrant-based segmentable clock networks * User-programmable Phase Locked Loop (PLL) circuit
Embedded Computational Units (ECUs)
Eighteen hardwired DSP building blocks with integrated Multiply, Add, and Accumulate functions.
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QL903M QuickMIPSTM Data Sheet Rev. H
Security Features
The QuickLogic products come with secure ViaLink technology that protects intellectual property from design theft and reverse engineering. No external configuration memory is needed for the Fabric. The device is instant-on at power-up.
QuickWorks Design Software
The QuickWorks package provides the most complete ESP and Field Programmable Gate Array (FPGA) software solution from design entry to logic synthesis, to place and route, and simulation. The package provides a solution for designers who use third party tools from Cadence, Mentor, Synopsys, and other thirdparty tools for design entry, synthesis, or simulation.
Process Data
The QL903M is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.95 V VCC supply and the I/Os are up to 3.3 V compliant. The QL903M is available in commercial and industrial temperature grades.
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QL903M QuickMIPSTM Data Sheet Rev. H
QL903M Architectural Overview
The QL903M chip can be thought of as having two distinct sides, an Application Specific Standard Product (ASSP) side and a Programmable Fabric side. The ASSP side contains the standard cell circuitry of the device such as the MIPS 4Kc CPU and the Ethernet MACs, and the Fabric side contains all of the programmable logic elements (e.g., logic cells and dual-port RAMs) of the device.
ASSP Side
This section discusses the various circuits in the ASSP portion of the QL903M device.
CPU Core
The MIPS32 4Kc processor core is a high-performance, low-power, 32-bit MIPS RISC core capable of speeds up to 200 MHz. The 4Kc core contains a fully-associative translation lookaside buffer (TLB) based Memory Management Unit (MMU) and a pipelined MDU. The core executes the MIPS32 instruction set architecture (ISA). It supports all application code in the MIPS I, II, III, and IV instruction sets. It also supports kernel code for the R4000 processor and above. The MIPS32 ISA contains special multiply-accumulate, conditional move, prefetch, wait, and zero/one detect instructions. The MMU contains a three-entry instruction TLB (ITLB), a three-entry data TLB (DTLB), and a 16 dual-entry joint TLB (JTLB) with variable page sizes. The 4Kc multiply-divide unit (MDU) supports a maximum issue rate of one 32x16 multiply (MUL/MULT/MULTU), multiply-add (MADD/MADDU), or multiply-subtract (MSUB/MSUBU) operation per clock, or one 32x32 MUL, MADD, or MSUB every other clock. Instruction and Data Caches The instruction and data caches are both 16 Kbytes in size. Each cache is organized as four-way set associative. The data cache has lockout capability per cache line. On a cache miss, loads are blocked only until the first critical word becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches are virtually indexed and physically tagged. Virtual indexing allows the cache to be indexed in the same clock in which the address is generated rather than waiting for the virtual-to physical address translation in the MMU. EJTAG Interface The basic Enhanced JTAG (EJTAG) features provide CPU run control with stop, single stepping and re-start, and software breakpoints through the SDBBP instruction. In addition, instruction and data virtual address hardware breakpoints, and connection to an external EJTAG probe through the Test Access Port (TAP) is included.
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QL903M QuickMIPSTM Data Sheet Rev. H
ASSP PLL
On the ASSP side of the QL903M there is a single clock input that provides an input clock reference for the MIPS core, the System Bus, and all ASSP peripherals (other than the PCI Controller, which is independently driven by the PCI_CLK input). This clock input (CPU_PLL_CLKIN) is the input to a PLL that is fixed at an 8 times clock multiplication rate. For example, if the clock rate applied to CPU_PLL_CLKIN is 25 MHz, the resultant clock that drives the MIPS core is 200 MHz. Table 1 shows the maximum input clock rates for CPU_PLL_CLKIN based upon the ASSP speed grade of the given QL903M device. Table 1: Maximum Input Frequency for CPU_PLL_CLKIN and MIPS Core Frequency Based on QL903M ASSP Speed Grade
QuickMIPS Device Part Number Prefix QL903M175 QL903M200 Maximum Input Frequency for CPU_PLL_CLKIN 21.875 MHz 25.000 MHz Resultant Maximum MIPS Core Frequency 175 MHz 200 MHz
The System Bus clock can run at a maximum rate of one-half the MIPS core clock frequency. Other ratios (one-third and one-fourth) are also possible and controlled by the CPU_PLL_DIV(1) and CPU_PLL_DIV(0) inputs as shown in Table 2. Table 2: MIPS Core Clock Rate to System Bus Clock Rate (hclk) Ratio Based on CPU_PLL_DIV(1) and CPU_PLL_DIV(0) Signals
CPU_PLL_DIV(1) 0 1 1 CPU_PLL_DIV(0) X 1 0 Ratio MIPS Core Clock Rate : System Bus Clock Rate (hclk) 2:1 3:1 4:1 System Bus Clock (hclk) Duty Cycle 50% 33%a 50%
a. In 3:1 mode, the System bus clock duty cycle is not symmetric. This affects the internal System Bus clock as well as hclk and the SDRAM clock source (SD_CLKOUT). Therefore, care must be taken so that minimum clock pulse widths are not violated when these clock signals are used to drive externally connected devices.
SDRAM Memory Controller
The QL903M SDRAM Memory Controller (SDMC) provides all the necessary logic to connect to a wide variety of industry standard SDRAMs for use by the CPU, Ethernet Controllers, PCI Controller, and Programmable Fabric. The SDMC supports a minimum SDRAM size of 16 Mbytes and a maximum SDRAM size of 256 Mbytes. The SDRAM Controller controls the SDRAM on the external bus. On receiving an access request, the SDRAM Controller decides on the appropriate commands to send to the SDRAM memory. The DRAM Bank Controller sequences all of the commands required to complete a read or write request to an SDRAM memory location with timing controlled by the CAS Delay and RAS Delay values. The bus interface is a slave on the System Bus; it contains the control register block. The bus interface produces read, write, refresh and mode register write requests to the SDRAM control engine, and software supplied configuration information.
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QL903M QuickMIPSTM Data Sheet Rev. H
Data is transferred to and from the SDRAM as unbroken quad words. This data packet size is convenient for cache line fills and buffered writes. For accesses smaller than a quad word, extra read data is ignored by the SDRAM Controller; for writes, the SD_DQM(3:0) pins are used to force the SDRAMs to ignore invalid data. For access sizes larger than a quad word, multiple quad word accesses are issued to the SDRAM control engine.
I/O Peripheral Controller
This section describes access to I/O and memory devices on the external M Bus (with the exception of SDRAM). The I/O Peripheral Controller (Figure 2) generates strobes and signals that can be used to interface the M Bus with common asynchronous peripheral devices. The QL903M Peripheral Controller Unit (PCU) provides decoded strobe signals to control external peripherals such as SRAM, flash, real time clock (RTC) and memory mapped I/O devices. It supports 8-bit, 16-bit, and 32-bit widths with programmable wait states and bus turnaround time based on memory speed. The PCU provides the following functionality: * Decoding of memory access in the local CPUs memory map to generate chip selects or strobes. * Control of wait states for decoded regions. A total of eight chip select signals are available. Chip select seven is used as the boot ROM chip select. The M Bus is a shared resource between the SDRAM Controller and I/O Controller. The M Bus is assigned to one of these two controllers by an internal arbiter. There is one turn-around cycle when switching from one controller to the other. Figure 2: SDRAM and I/O Controllers
System Bus
SDRAM Controller
SD_DQM[3:0] SD_CS[1:0] SD_RAS SD_CAS SD_WE SD_CKE[1:0] SD_CLKOUT SD_CLKIN ADDR[14:0] DATA[31:0]
M Bus M Bus Controller MUX
ADDR[23:0] DATA[31:0]
ADDR[23:0] DATA[31:0]
I/O Controller
BLS[3:0] OE WE CS[7:0]
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QL903M QuickMIPSTM Data Sheet Rev. H
PCI Controller
The QuickMIPS PCI Interface is a 32-bit, 66 MHz, Revision 2.2 compliant interface as specified by the PCI Local Bus Specification. This section provides a detailed description of the PCI Controller functionality. Figure 3 shows a simplified block diagram of the PCI Controller. The PCI Controller is a bridge between the on-chip System Bus and the external PCI bus. There are two main modes of operation of the PCI function, each utilizing several resources: * PCI Target PCI Target access to System Address Space PCI Target to PCI configuration registers PCI Target to extended registers (DMA and message/mailbox) * PCI Master System Address Space to PCI access System-to-PCI and PCI-to-System DMA PCI master read/write generated through the single access register Figure 3: PCI Block Diagram
System Bus
Message Unit
Master Interface
Target Interface
PCI Interface
DMA Registers PCI Configuration Registers Write FIFO
(8x32)
DMA Controller Read FIFO
(8x32)
Write FIFO
(32x32)
Read FIFO
(32x32)
Single Access Registers
PCI Target
PCI Master
32 PCI Bus
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QL903M QuickMIPSTM Data Sheet Rev. H
The PCI Controller can be used as a system host or as a secondary master: * System Host: The QL903M PCI interface is connected to the root PCI bus segment (Bus 0) and the onchip CPU performs bus enumeration to determine how all PCI Base Address Registers are configured. The SDRAM controlled by the QL903M is used as the main memory. The Single Access Controller can be used for performing enumeration upon system boot, and then to perform I/O operations to I/O mapped PCI devices. The System Bus to PCI Memory Aperture can be used by host drivers to control memory mapped PCI devices (PIO). The DMA Controller provides the most efficient way to transfer large blocks of data between system memory and external PCI target devices (such as video controllers, etc.). * Secondary Master: The QL903M is enumerated by an external PCI host CPU. The PCI configuration registers of the QL903M are recognized by the host CPU and enumerated accordingly. The DMA Controller can be used to efficiently move data between local QL903M-controlled SDRAM and the host memory. The Single Access Controller can be used to transfer small amounts of data in and out of the host memory space. The message unit can be used as an inter-CPU communication mechanism for a host driver to synchronize with a local driver running on the QL903M CPU. The PCI to local System Bus aperture can be used to allow the host CPU or other PCI agent to access QL903M memory directly.
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QL903M QuickMIPSTM Data Sheet Rev. H
Ethernet Controllers
The QL903M has two Ethernet Media Access Controllers (MACs) embedded in the ASSP portion of the device. The Ethernet Controllers incorporate the essential protocol requirements for operation of Ethernet/IEEE 802.3 compliant nodes, and provide interfaces between the host subsystem and the Media Independent Interface (MII). Each 10/100 MAC can operate in 10 Mbps or 100 Mbps mode based on the transmit and receive clocks provided (2.5/25 MHz). The controllers contain transmit and receive FIFOs and embedded DMA control. Figure 4 shows a block diagram of the QL903M Ethernet Controller. Figure 4: Ethernet Controller Block Diagram
Fabric
MII 10/100 MAC
TX FIFO
RX FIFO
DMA Controller
System Bus
The DMA Controller is responsible for exchanging data between the FIFOs and the system memory. DMA operation is controllable through a set of control and status registers. Each 10/100 MAC operates in half-duplex mode and full-duplex modes. When operating in the half-duplex mode, the 10/100 MAC core is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard) and ANSI/IEEE 802.3. When operating in the full-duplex mode, the 10/100 MAC core is compliant to the IEEE 802.3x standard for full-duplex operations. Each 10/100 MAC is also compatible with Home PNA 1.1. The 10/100 MAC core provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include the ability to disable retires after a collision, dynamic FCS generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmission and detection of collision frames. The 10/100 MAC core can sustain transmission or reception of minimal-sized back-to-back packets at full line speed with an inter-packet gap (IPG) of 9.6 s for 10-Mb/s and 0.96 s for 100-Mb/s. Data to/from the MAC is buffered in transmit/receive FIFOs. In the case of data received by the Ethernet MAC, the data is drained from the receive FIFO by the DMA Controller and stored to the specified target (typically the data is stored in SDRAM). For Ethernet transmit, the DMA Controller reads data from memory (SDRAM typically) and pushes it into the transmit FIFO. DMA operation is controllable through a set of control and status registers. With the exception of the M1_RXCLK, M2_RXCLK, M1_TXCLK and M2_TXCLK signals, the MII interface is located on the ASSP/Fabric boundary internal to the device. If the designer wants to use one or both of the Ethernet MACs, the signal ports on this interface must be brought out to Fabric IO pins in the top-level Fabric design. Table 3 shows the recommended Fabric IO pin locations for the MII interface pins.
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 3: MII Interface Signals and Recommended Fabric IO Pin Locations
MII Interface Signal M1_COL M1_CRS M1_MDC M1_MDI M1_MDO M1_MDO_EN_N M1_RXD(0) M1_RXD(1) M1_RXD(2) M1_RXD(3) M1_RXDV M1_RXER M1_TXD(0) M1_TXD(1) M1_TXD(2) M1_TXD(3) M1_TXEN M2_COL M2_CRS M2_MDC M2_MDI M2_MDO M2_MDO_EN_N M2_RXD(0) M2_RXD(1) M2_RXD(2) M2_RXD(3) M2_RXDV M2_RXER M2_TXD(0) M2_TXD(1) M2_TXD(2) M2_TXD(3) M2_TXEN MII Interface Directiona I I O I O O I I I I I I O O O O O I I O I O O I I I I I I O O O O O M2_RXD(0) M2_RXD(1) M2_RXD(2) M2_RXD(3) M2_RXDV M2_RXER M2_TXD(0) M2_TXD(1) M2_TXD(2) M2_TXD(3) M2_TXEN I I I I I I O O O O O B26 L23 E24 C24 F24 L22 M24 C26 M23 D26 M22 M2_MDIOb I/O/Z E25 M1_RXD(0) M1_RXD(1) M1_RXD(2) M1_RXD(3) M1_RXDV M1_RXER M1_TXD(0) M1_TXD(1) M1_TXD(2) M1_TXD(3) M1_TXEN M2_COL M2_CRS M2_MDC I I I I I I O O O O O I I O F2 E1 E2 D1 L4 D2 L3 C1 L5 B1 E3 K22 L24 C25 M1_MDIOb I/O/Z K4 Fabric Pin Signal M1_COL M1_CRS M1_MDC Fabric Pin Type I I O Fabric Pin Location F1 G2 F3
a. MII Interface direction is specified with respect to the ASSP portion of the device. I designates an input to the ASSP and O designates an output from the ASSP. b. The M1_MDIO and M2_MDIO signals require the instantiation of a bipad_25um macro. See Figure 5 for more details.
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QL903M QuickMIPSTM Data Sheet Rev. H
The pin assignments in Table 3 represent connections to IO banks A and D of the Fabric. If the Ethernet MACs are connected in this fashion, these two banks must be configured for 3.3 V operation. See Table 17 for more details. As Table 3 indicates, the Mn_MDIO pin is bi-directional. The signal on this pin is made up of three MII interface signals. Mn_MDI and Mn_MDO are the data input and output signals respectively, and Mn_MDO_EN_N is the tri-state buffer enable signal that turns on the pin output driver. Mn_MDO_EN_N is active low, and must be made active high by running it through a logic cell inverter before connecting it to the bipad_25um macro. Figure 5 shows how these connections are made to the bipad_25um macro. Figure 5: bipad_25um Macro and Connections to MII Interface Signals
Connect to inverted copy of Mn_MDO_EN_N Connect to Mn_MDO Connect to Mn_MDI
EN
A P Q Mn_MDIO
The remainder of the MII signals are simple inputs or outputs and can be connected to the Fabric IO pins directly without the instantiation of any specific macros.
System SRAM
The QL903M contains 16 K bytes of SRAM internal to the ASSP portion of the device. This SRAM is divided into four equal sections of 4 KB each (each arranged as 32-bit x 1024 words), and each section can be configured to be connected to the System Bus (specifically, AHB) or connected to the Fabric directly. When connected to the AHB, the SRAM (an AHB slave) can be accessed by any AHB master. Furthermore, the 4Kc core can use this internal SRAM for data or instruction storage. The SRAM supports 32-bit, 16-bit, or single byte accesses. When connected to the Fabric, the SRAM can be accessed directly by any Fabric design without suffering the overhead of accessing it through the AHB interface. In addition, the Fabric has a master AHB interface, which it may also use to access the SRAM. However, in some high-speed applications, it may be necessary for the Fabric to have exclusive access to the SRAM memory. The Fabric interface of the SRAM block facilitates this function, and is described below. Figure 6 shows the connection scheme of the four memory banks between the Fabric and the AHB.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 6: SRAM Connection Scheme between the Fabric and AHB
Fabric
SRAM 4 Interface
SRAM 3 Interface
SRAM 2 Interface
SRAM 1 Interface
Address, Write Data, Clock and Control
Address, Write Data, Clock, and Control
Address, Write Data, Clock, and Control
Read Data
Read Data
System Target Interface 48 32 48 32 48 32 48 32
4K SRAM (1024x32)
4K SRAM (1024x32)
Read Data
4K SRAM (1024x32)
4K SRAM (1024x32)
System Bus
Each SRAM block is single ported, and is connected to the Fabric or AHB through a selection MUX. For each SRAM block, the address bus, control signals, clock, and data write bus are all multiplexed by a register bit that is accessible through the System Bus. Therefore, any AHB master may control the switch of a given SRAM block between the AHB and the Fabric interface. Because each SRAM clock is also switched by the selection MUX, it is possible for the Fabric to drive each SRAM block with a separate clock. However, when an SRAM block is connected to the AHB interface, the System Bus clock (hclk) is always used to drive the block. Refer to Table 51 for descriptions of all the System SRAM signals that interface to the Fabric.
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Read Data
GL_SR_SELECT Register
Address, Write Data, Clock, and Control
SRAM Block
QL903M QuickMIPSTM Data Sheet Rev. H
Interrupt Controller
This section describes the function of the QL903M Interrupt Controller Unit (ICU). Figure 7 shows a block diagram of the Interrupt Controller. Figure 7: Simplified Interrupt Controller Block Diagram
Configuration Options Interrupts from On-Chip Peripherals/Fabric
PLL and Clock Divider (PL)
Clocks and Reset
Global Logic (GL)
Interrupts to CPU
MIPS 4Kc CPU Core
System Bus
The QL903M has 9 on-chip peripheral interrupts and 7 external interrupts (including on NMI), for a total of 16 interrupt sources. These 16 interrupt sources are combined into 7 interrupts by the interrupt controller and fed to the CPU core. External interrupts must be asserted for at least two clock periods in order to be recognized as an interrupt. All interrupts are level triggered. Each interrupt has an Emulation Enable Register bit and an Emulation Interrupt Value Register bit in the Interrupt Controller. The primary use for the Emulation registers is for testing purposes. The interrupt enable bits are stored in the GL_EMUL_EN register. The emulation interrupt value for each possible interrupt is stored in the GL_INT_EMUL register. Each interrupt has an enable bit in the Global Individual Interrupt Enable (GL_IND_INT_EN) register in the Interrupt Controller. Each interrupt also has a status bit in the Global Individual Interrupt Status (GL_IND_INT_STATUS) register in the Interrupt Controller. The Global CPU Interrupt Enable register (GL_CPU_INT_EN) enables masking of the interrupt groups after they have been grouped together. The Interrupt Controller has no programmability for priority. That is, there is no hardware priority encoder. Priority is provided as a function of software.
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QL903M QuickMIPSTM Data Sheet Rev. H
High Performance 32-Bit System Bus (AMBA Bus)
The purpose of this section is to describe the AMBA1 bus operation for the purposes of implementing user circuits in the Programmable Fabric. All circuits in the ASSP portion of the QL903M chip communicate with the Programmable Fabric primarily through the AMBA bus interfaces (Advanced Microcontroller Bus Architecture from ARM). Circuits implemented in the Programmable Fabric must be designed according to the AMBA Specification, Revision 2.0. The devices within the QL903M are interconnected through the Advanced High-performance Bus (AHB) or the Advanced Peripheral Bus (APB). Refer to the AMBA Specification, Revision 2.0, for more detailed information about the AHB and APB. Advanced High-Performance Bus (AHB) The AHB is the high-performance variant of the AMBA specification. It supports multiple bus masters and provides high bandwidth operation. The AHB implementation in the QL903M is 32 bits wide. All signals are synchronous to the rising clock edge of the bus clock (hclk). The key features of the QL903M AHB include: * Burst transfers * Single-cycle bus master handover * 32-bit bus runs at up to half the CPU clock frequency * Multiple bus masters * Arbitration through an AHB arbiter * Address decoding through an AHB decoder Table 4 lists the master and slave devices that connect to the AHB. Table 4: Master and Slave Devices on the AHB
AHB Masters MIPS 4Kc CPU PCI Ethernet Controller 1 Ethernet Controller 2 32-bit Master Interface to Programmable Fabric AHB Slaves System SRAM PCI Ethernet Controller 1 Ethernet Controller 2 32-bit Slave Interface to Programmable Fabric SDRAM and I/O Peripheral Controllers Interrupt Controller AHB to APB Bridge
The QL903M AHB supports multiple bus masters as well as bus slaves. Only one bus master can use the bus at a given time. The bus master provides address and control information when performing read and write operations. In response to the read or write operation from the bus master within a given address range, a bus slave provides information regarding the status of the data transfer (success, failure, or wait). The AHB arbiter ensures that only one bus master is initiating data transfers. The AHB decoder decodes the address of each transfer and provides a select signal for the slave that is involved in the transfer.
1. AMBA is a trademark of ARM Ltd. * * * *
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QL903M QuickMIPSTM Data Sheet Rev. H
AHB Arbitration The internal arbiter of the QL903M provides either fixed arbitration priority or round robin rotating priority. Preemption occurs only after a burst of four. Consequently, when a low priority master is in control of the bus and a higher priority master requests access, the lower priority device will lose its grant after a burst of four before another master takes control. This minimizes the loss of performance that happens when bursts are preempted. This preemption only happens when the designated AHB master is performing bursts of undefined lengths. If the AHB master is performing a burst of a defined (fixed) length, the burst will complete without interruption by the arbiter. The ARB_FAIR_EN bit in the GL_INT_EMUL register determines the priority scheme. When fixed priority is chosen, the priority of AHB masters is as follows (highest to lowest): 1. MIPS 4Kc CPU 2. Ethernet Controller 1 3. Ethernet Controller 2 4. PCI Controller 5. Programmable Fabric Advanced Peripheral Bus (APB) The APB is a simplified bus that is ideal for implementing device control registers and other non-burst transfers. The APB is a 32-bit wide bus that runs at the same frequency as AHB. The APB only accommodates slaves, does not support burst transfers, and does not support advanced slave response operations such as retries or wait state insertion. The APB on the QL903M is supported through an AHB-to-APB bridge. Three separately decoded APB regions are available for APB devices implemented in the Fabric. Table 5 lists the slave devices on the APB. Table 5: Slave Devices on the APB
APB Slaves Two UARTs Four 16-bit Timers/Counters Three 32-bit slave interfaces to Programmable Fabric
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QL903M QuickMIPSTM Data Sheet Rev. H
UARTs
The QL903M chip contains two UARTs. Each UART provides a full-duplex asynchronous receiver and transmitter and has programmable Baud rates. The UARTs contain an IrDA Serial Infrared (SIR) Encoder/ Decoder (ENDEC). One UART also has modem control signals. The serial output is software selectable between IrDA and generic serial modes. Figure 8 shows a block diagram of the UART. Figure 8: UART Block Diagram
Transmit FIFO System Bus Interface
Receive FIFO
Reveiver
Rx Data
Register Block
Baud Rate Generator
Transmitter Tx Data
System Clock FIFO Status / Interrupt Generation Interrupt
SIR ENDEC SIR Receive Decoder SIR Transmit Decoder
The key features of the UARTs are as follows: * Programmable Baud rate generation of up to 1/16 System Bus clock rate * FIFO enable or disable * 5, 6, 7, or 8 data bits * 1 or 2 stop bits * Odd and even, stick or no parity * Parity, framing, and overrun error detection * Line break generation and detection * Loopback * Interrupt generation
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
* IrDA SIR ENDEC block providing: Programmable use of IrDA SIR or UART input/output Support of IrDA SIR ENDEC functions for data rates up to 115.2 kilobits/second half-duplex Support of normal 3/16 and low-power (1.41 to 2.23s) bit durations Programmable internal clock generator allowing division of reference clock by 1 to 512 for low-power mode bit duration The System Bus (APB interface) generates read and write decodes for accesses to status/control registers and transmit/receive FIFO memories. The Register Block stores data written or to be read across the APB interface. The Baud Rate Generator contains free-running counters that generate a clock that is 16 times the transmit/receive bit rate. The transmit FIFO is an 8-bit wide, 16-entry deep FIFO memory buffer. CPU data written across the APB interface is stored in the FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act like a one-byte holding register. The receive FIFO is a 12-bit wide, 16-entry deep FIFO memory buffer. Received data and corresponding error bits, are stored in the receive FIFO by the receive logic until read out by the CPU across the APB interface. The receive FIFO can be disabled to act like a one-byte holding register. The transmitter performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits, Least Significant Bit (LSB), a parity bit, and then stop bits according to the programmed configuration in control registers. The receiver performs serialto-parallel conversion on the received bitstream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line break detection are also performed, and the data with associated overrun, parity, framing, and break error bits is written to the receive FIFO. The Interrupt Generator outputs a single, combined interrupt to the QL903M Interrupt Controller. The SIR Transmit Encoder modulates the Non-Return-to-Zero (NRZ) transmit bitstream output from the QL903M chip. The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode (LED). The SIR Receive Decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bitstream to the QL903M UART received data input. The decoder input is normally HIGH (marking state) in the idle state. The transmit encoder output has the opposite polarity to the decoder input.
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
General Purpose 16-bit Timer/Counters
The QL903M chip has four independent 16-bit timer/counter modules. The configuration registers for these modules are accessible through the System Bus (APB). The System Bus clock (hclk), or an external clock supplied from the Fabric, drive the clock inputs on the timer/counter modules. These counters operate in one of four modes: decrement, increment, interval, or Pulse Width Modulation (PWM). Each timer/counter module has the capability to generate system interrupts on various events. One timer/counter is configured, by default, as a watchdog timer after a system reset. This watchdog timer has its own system interrupt output. Figure 9 shows a functional block diagram of the timer module. Figure 9: Timer Functional Block Diagram
Programmable ViaLink Fabric
System Bus tm_extclk[4:1] tm_overflow[4:2] tm_fbenable
ICU
7 Interrupts
32-bit MIPS 4Kc CPU 16K 16K D-cache I-cache
Timer Int
WD Int
Control Registers
tm_enable
TM_ENABLE
Counter 4
3 4
Counter 3
Counter 2
Counter 1
tm_overflow[1]
TM_OVERFLOW
16-bit Timer/Counters
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
The key features of each timer/counter module are as follows: * Up to 100 MHz operation. * 32-bit data path on the System Bus. * 16-bit timer/counter. * 16-bit pre-scaler to increase timer/counter delay. * Four modes of operation: decrement, increment, interval and PWM. * Operation from the System Bus clock (hclk) or an external clock from the Fabric. * Two external hardware timer enable signals can be used to start/stop the timer/counter. One of these signals can be supplied from the Fabric and the other is a dedicated input pin on the chip. * Three match interrupts, one interval interrupt and one overflow interrupt. * Six control registers to control various counter functions, including enable/disable, load, and reset. The timer/counters are controlled by a set of control registers. Each timer/counter module has six control registers. By contrast, one interrupt register is used to control and convey the status of the interrupts from all the modules. One counter (Counter 4) is configured, by default, to be used as a watchdog timer after the system reset. This watchdog timer has its own system interrupt output, and it can be reconfigured by software for use as a standard timer/counter.
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
Fabric Side
This section discusses the various circuit elements in the Fabric portion of the QL903M device.
Logic Cells
The QL903M logic cell structure presented in Figure 10 is a dual register, multiplexor-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be connected to multiple routing channels. The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. Figure 10: QL903M Logic Cell
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ
DQ
QZ
NZ
DQ
Q2Z
FZ
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Dual-Port SRAM Modules
The QL903M includes up to 18 dual-port 2,304-bit RAM modules (shown in Figure 11) for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into two different block organizations and can be cascaded vertically to increase their effective depth or horizontally to increase their effective width as shown in Figure 12. Figure 11: 2,304-bit RAM Module
MODE[1:0] WA[7:0] WD[17:0] WE WCLK ASYNCRD RA[7:0] RD[17:0] RE RCLK
2,304-bit Module
Using two mode pins, designers can configure each module into 128 x 18 (Mode 0) or 256 x 9 (Mode1). Figure 12: Cascaded RAM Modules
WDATA WADDR
RAM Module (2,304 bits)
RDATA
RADDR
RAM Module (2,304 bits) WDATA RDATA
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some higher order data lines or the highest order address line may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low). The RE and RCLK inputs are ignored when ASYNCRD is tied high.
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QL903M QuickMIPSTM Data Sheet Rev. H
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 256 words. In this case address signals higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions). Dual-Port SRAM Module Signals The dual-port RAM module signal descriptions are shown in Table 6. Table 6: Dual-Port RAM Module Signal Descriptions
Signal Name WCLK WE I/O I I Description Write Clock. Clock input for the write port of the RAM module. All write port input signals are synchronous with this clock. Write Enable. Sampled on the rising edge of WCLK, when WE is high, data is written into the RAM module at the specified write address. Write Address. Sampled on the rising edge of WCLK, this is the write address for the data to be written into the RAM module. WA(7:0) is ignored when WE is low. Note that some higher order bits of WA(7:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Write Data. Sampled on the rising edge of WCLK, this is the data to be written into the RAM module. WD(17:0) is ignored when WE is low. Note that some higher order bits of WD(17:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Read Clock. This is the clock input for the read port of the RAM module. If ASYNCRD is low, all read port I/O signals are synchronous with this clock. If ASYNCRD is high, RCLK is ignored. Read Enable. Sampled on the rising edge of RCLK, when RE is high, data is read from the RAM module at the specified read address. If ASYNCRD is high, this RE is ignored. Read Address. This is the read address for data to be read from the RAM module. If ASYNCRD is low, RA(7:0) is sampled only on the rising edge of RCLK while RE is high. If ASYNCRD is high, RA(7:0) is continuously sampled by the RAM module and RE has no effect. Note that some higher order bits of RA(7:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Read Data. This is the read output data from the RAM module. If the RAM module is in synchronous read mode (ASYNCRD low), valid read data is output immediately following the rising edge of RCLK which sampled RE as high. If the RAM module is in asynchronous read mode (ASYNCRD high), valid read data is output immediately after any change in the read address. Note that some higher order bits of RD(17:0) may not be used depending on the selected mode for the RAM module (see MODE(1:0) signal description). Asynchronous Read Input. This signal, when high, indicates to the RAM block that the read port should operate asynchronously. When low, all read port I/O signals are synchronous with RCLK. This signal can only be tied to `1' or `0' inside the Fabric. Mode for RAM Module. These bits configure the width and depth of the RAM module (for both the read and write ports) and can only be tied to `1' or `0' inside the Fabric. The possible RAM module modes are: MODE(1:0) = "00" : 128 x 18 (locations x data bits) MODE(1:0) = "01" : 256 x 9 (locations x data bits) MODE(1:0) = "1X" : Reserved
WA(7:0)
I
WD(17:0)
I
RCLK RE
I I
RA(7:0)
I
RD(17:0)
O
ASYNCRD
I
MODE(1:0)
I
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Embedded Computational Units (ECUs)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively-- these functions require high logic cell usage while garnering only moderate performance results. The QL903M architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL903M device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 13. Figure 13: ECU Block Diagram
S3 S2 S1 CIN SIGN2 SIGN1
A[15:8] A[7:0]
3-4 Decoder
D C B A
00 01 Q[16:0]
8-bit Multiplier
16-bit Adder
DQ
10
A[15:0] B[15:0]
CLK RESET
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QL903M QuickMIPSTM Data Sheet Rev. H
ECU Signals Table 7 defines the ECU I/O signals. For more information on the operation of the ECU, see QuickLogic Application Note 52 at http://www.quicklogic.com/images/appnote52.pdf. Table 7: ECU I/O Signals
Signal Name CLK RESET S1 S2 S3 CIN SIGN1 SIGN2 A(15:0) A(15:8) A(7:0) B(15:0) Q(16:0) I O I I/O I I I I I I I I Description Clock Input. Input clock for the ECU output register. Reset Input. Active high reset input for the ECU output register. ECU Control S1. One of three instruction signals that define the configuration mode of the ECU (see Table 8). ECU Control S2. One of three instruction signals that define the configuration mode of the ECU (see Table 8). ECU Control S3. One of three instruction signals that define the configuration mode of the ECU (see Table 8). Carry Input. 1-bit Carry In for 16-bit adder operations. Sign Input for Multiplier A Input. When SIGN1 = `1', A(7:0) is treated as signed or two's complement binary. When SIGN1 = `0' A(7:0) is treated as unsigned binary. Sign Input for Multiplier B Input. When SIGN2 = `1', B(15:8) is treated as signed or two's complement binary. When SIGN2 = `0' B(15:8) is treated as unsigned binary. Augend Input. 16-bit augend input of the 16-bit adder when the ECU is in any of the adder configuration modes. Multiplicand Input. 8-bit multiplicand input when the ECU is in any of the multiplier configuration modes. Multiplier Input. 8-bit multiplier input when the ECU is in any of the multiplier configuration modes. Addend Input. 16-bit addend input when ECU is in any of the adder configuration modes. ECU Output. This is the 17-bit output of the ECU. The interpretation of the value of Q(16:0) depends on the setting of S1, S2, S3, SIGN1, and SIGN2.
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
The QL903M ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Up to eighteen 8-bit MAC functions can be implemented per cycle for a total of 1.8 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The instruction modes for the ECU block are dynamically re-programmable through the programmable logic as shown in Table 8. Table 8: ECU Mode Select Criteria
Instruction S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulate Add Multiply (registered)a Multiply- Add (registered) Multiply - Accumulate Add (registered)
a. B (15:0) set to zero.
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QL903M QuickMIPSTM Data Sheet Rev. H
Fabric PLL
Instead of requiring extra components, designers simply need to instantiate the QL903M Fabric PLL model (described in this section). The Fabric PLL built into the QL903M supports a wider range of frequencies than many other PLLs. The PLL also has the ability to support different ranges of frequency multiplications or divisions, driving the Fabric at a faster or slower rate than the incoming clock frequency. Figure 14 illustrates the QL903M Fabric PLL. Figure 14: QL903M Fabric PLL Block Diagram
Lock Detect
LOCK_DETECT
Phase Frequency Detector FB_PLL_CLKIN
Charge Pump
VCO FB_PLL_PADOUT
M = 2, 4 or 8 :M FB_PLL_RESET_n
FD = 1, 2, 3, 4 or 8 : FD
Phase = 0, 90, 180, 270 Phase Adj. PLLCLK_OUT
Phase = 0, 90, 180, 270 Phase Adj.
PLLCLK_OUT2
FD0 FD1 FD2
M0 M1
PS0 PS1
PS2 PS3
The QL903M Fabric PLL is driven by the FB_PLL_CLKIN input pin. This input is used by the PLL as a clock reference for the Voltage Controlled Oscillator (VCO) internal to the PLL circuit. Using the M1 and M0 inputs to the PLL block, the designer may choose a frequency multiplier value for the VCO. The PLL output pin, FB_PLL_PADOUT runs at the VCO operational frequency. Table 9 shows the minimum and maximum input (Fin) and output (Fpad) frequency for each possible VCO multiplier mode.
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Table 9: Frequency Ranges for Fabric PLL Input Pad (FB_PLL_CLKIN), Output Pad (FB_PLL_PADOUT) and VCO
M1 0 0 1 1 M0 0 1 0 1 VCO Mode 2x 4x 8x FB_PLL_CLKIN (Fin) Input Frequency Range 50.0 to 150.0 MHz 25.0 to 75.0 MHz 12.5 to 37.5 MHz Reserved - should not be used FB_PLL_PADOUT (Fvco and Fpad) Pad Output Frequency Range 100 to 300 MHz 100 to 300 MHz 100 to 300 MHz
In addition to the Fabric PLL output pin, the PLL can also drive two clock networks in the Fabric. These two additional outputs, PLLCLK_OUT and PLLCLK_OUT2 offer further control over frequency and phase by adding an output frequency divider and phase adjustment control. PLLCLK_OUT and PLLCLK_OUT2 can be configured for different output phases, but they both operate at the same frequency. Table 10 shows the Fabric clock network PLLCLK_OUT resultant output frequency (Ffab), duty cycle and phase based on the FD2, FD1, FD0, PS3 and PS2 inputs. Table 10: Frequency, Duty Cycle and Phase Values for Fabric PLL Output PLLCLK_OUT
Fabric Output PLLCLK_OUT FD2 0 FD1 0 FD0 0 (Ffab) Frequency FVCO Duty Cycle 50% PS3 X 0 0 0 1 FVCO / 2 50% 0 1 1 0 1 0 FVCO / 3 33% X 0 0 1 1 FVCO / 4 50% 0 1 1 0 1 X X FVCO / 8 50% 0 1 1 PS2 X 0 1 0 1 X 0 1 0 1 0 1 0 1 Phase 0 180 270 0 90 0 0 90 180 270 270 0 90 180
NOTE: PLLCLK_OUT phase shown in the Table 10 is based on the period 1/Ffab. NOTE: An output phase of 0 indicates that the rising edge of PLLCLK_OUT will be aligned with the rising edge of FB_PLL_CLKIN. NOTE: To maintain the phase values shown in Table 10, FVCO should not exceed 200 MHz. If FVCO is set above 200 MHz, the phase of PLLCLK_OUT will have no guaranteed relation to FB_PLL_CLKIN.
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 11 shows the Fabric clock network PLLCLK_OUT2 resultant output frequency (Ffab), duty cycle and phase based on the FD2, FD1, FD0, PS1 and PS0 inputs. Table 11: Frequency, Duty Cycle and Phase Values for Fabric PLL Output PLLCLK_OUT2
Fabric Output PLLCLK_OUT2 FD2 0 FD1 0 FD0 0 (Ffab) Frequency FVCO Duty Cycle 50% PS1 X 0 0 0 1 FVCO / 2 50% 0 1 1 0 1 0 FVCO / 3 33% X 0 0 1 1 FVCO / 4 50% 0 1 1 0 1 X X FVCO / 8 50% 0 1 1 PS0 X 0 1 0 1 X 0 1 0 1 0 1 0 1 Phase 0 180 270 0 90 0 0 90 180 270 270 0 90 180
NOTE: PLLCLK_OUT2 phase shown in the Table 11 is based on the period 1/Ffab. NOTE: An output phase of 0 indicates that the rising edge of PLLCLK_OUT2 will be aligned with the rising edge of FB_PLL_CLKIN. NOTE: To maintain the phase values shown in Table 11, FVCO should not exceed 200 MHz. If FVCO is set above 200 MHz, the phase of PLLCLK_OUT2 will have no guaranteed relation to FB_PLL_CLKIN. Fabric PLL Signals Table 12 summarizes the key signals of the QL903M Fabric PLL. Table 12: Fabric PLL I/O Signals
Signal Name FB_PLL_CLKIN FB_PLL_RESET_n FB_PLL_PADOUT I/O I I O Description Input clock signal. See Table 50 for more details. Active low reset. See Table 50 for more details. PLL output off chip. See Table 50 for more details. PLL output to Fabric (1 of 2). This is the PLL output clock driven to the Fabric clock network. This output runs at the Ffab frequency described in Table 10. Furthermore, this output is also phase adjustable. The output frequency and phase is determined by the M(1:0), FD(2:0) and PS(3:2) inputs. PLL output to Fabric (2 of 2). This is the PLL output clock driven to the Fabric clock network. This output runs at the Ffab frequency described in Table 11. Furthermore, this output is also phase adjustable. The output frequency and phase is determined by the M(1:0), FD(2:0) and PS(1:0) inputs.
PLLCLK_OUT
O
PLLCLK_OUT2
O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 12: Fabric PLL I/O Signals (Continued)
Signal Name LOCK_DETECT M(1:0) FD(2:0) PS(3:2) PS(1:0) I/O O I I I I Description Active high lock detection signal. This signal is output to the Fabric and goes high when the PLL VCO is locked to the input clock reference. VCO frequency multiplier input. These inputs are statically driven high or low by the Fabric. See Table 9 for their effect on PLL operation. Fabric output frequency divide input. These inputs are statically driven high or low by the Fabric. See Table 10 for their effect on PLL operation. Phase select input for Fabric output. These inputs are statically driven high or low by the Fabric. See Table 10 for their effect on PLL operation. Phase select input for Fabric output2. These inputs are statically driven high or low by the Fabric. See Table 11 for their effect on PLL operation.
NOTE: Because FB_PLL_CLKIN, FB_PLL_RESET_n, and FB_PLL_PADOUT have appropriate INPAD and OUTPADs included, you do not have to add these pads to your design.
Advanced Clock Networks
The QL903M device has a large number of extremely advanced and highly flexible clock networks. These consist of three basic types of networks; a Global Network and a Dedicated Network (for low-skew applications), and an I/O Control/Hi-Drive Network (for high-fanout, multi-load applications). Global and Dedicated Low-Skew Networks The Global and Dedicated Networks are low-skew networks typically used to drive clock signals throughout the entire device. In addition, the Global Network can also be used to globally drive other high-fanout signals with low skew (e.g., flip-flop set or reset signals). Both networks are segmented, separated on a per-quadrant basis. (Unlike the QuickLogic Eclipse architecture, the QL903M has only two quadrants.) Figure 15 shows a simplified view of the low-skew clock network architecture in the QL903M device. Figure 15: Low Skew Clock Architecture
Upper Left Upper Right
Global and Dedicated Networks
CLK Pin
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 13 shows the number of Global and Dedicated Networks available per quadrant in the QL903M. Table 13: Number of QL903M Low-Skew Clock Networks
Clock Network Type Global Dedicated Total Quadrant Upper Left 8 (5 are Quad-Nets) 1 9 Upper Right 8 (5 are Quad-Nets) 1 9 Total 16 2 18
As Table 13 shows, there are a total of nine low-skew networks per quadrant in the QL903M, making a total of eighteen in the entire device. Each quadrant contains eight Global Networks and one Dedicated Network. The Global Network and Dedicated Network differ slightly in performance and flexibility. The Dedicated Network offers superb low-skew and minimal pin to logic element delay performance, but can only drive the clock inputs of specific Fabric elements. The Global Network offers more flexibility to drive a variety of inputs in the Fabric as well as internal ASSP port inputs, but at a slight increase in skew and delay. Table 14 outlines all allowable input destinations for each clock network type. Table 14: Allowable Inputs Destinations for Global and Dedicated Networks
Element Inputs That Can be Driven by the Global Clock Network QC A2 Logic Cells F1 QS QR WCLK RAM Modules RCLK RE WE ECUs CLK RESET IQC IQR I/O Cells EQE IQE IE ASSP Interface All Inputs IQC WCLK RCLK QC Inputs That Can be Driven by the Dedicated Clock Network
Each quadrant consists of an element called the PLLMUX that drives the Global Networks and the Dedicated Network in the quadrant. The PLLMUX selects between external CLK input pins and clock signals that are driven from other elements internal to the device such as the Fabric PLL and the ASSP System Bus clock (hclk). Figure 16 shows a simplified schematic diagram of the CLK input pins, the PLLMUX elements and the associated clock networks.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 16: Low Skew Clock Structure Schematic Based Upon PLLMUX Elements (1 of 2 Quadrants)
PLL MUX hclk Logic Element CLK(2) Input Pin Global Clock Network
XX
tPGCK tBGCK
Global Clock Network
PLL MUX PLLCLK_OUT
Logic Element CLK(3) Input Pin
XX
tPGCK tBGCK
Global Clock Network
PLL MUX No Connection
Logic Element CLK(5) Input Pin
XX
tPGCK tBGCK
Dedicated Clock Network
PLL MUX PLLCLK_OUT2
Logic Element CLK(4)/DEDCLK Input Pin
XX
tPDEDCLK
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QL903M QuickMIPSTM Data Sheet Rev. H
If either of the Fabric PLL outputs or hclk are utilized in a given quadrant of the Fabric design, the QuickWorks software automatically configures the corresponding PLLMUX to select the internal clock input. Each quadrant consists of four PLLMUX elements of which one input is tied to a specific CLK input pin as shown in Table 15. Table 15: PLLMUX Input Signals and Output Type (Per Quadrant)
Input Pin CLK(2) CLK(3) CLK(4)/DEDCLK CLK(5) Internal Signals hclk PLLCLK_OUT PLLCLK_OUT2 Output Type Global clock network Global clock network Dedicated clock network Global clock network
As Table 15 indicates, once a PLLMUX is used to drive an internal signal onto the Global or Dedicated Networks, the corresponding CLK input pin is blocked from entering that quadrant. NOTE: If either of the Fabric PLL outputs or hclk are utilized in the Fabric design, and external clock pins are also utilized, the designer should choose clock input pins on the device that do not conflict with these corresponding PLLMUX elements. Quad-Net Network (Subset of the Global Network) In each quadrant, the remaining five Global Networks are also referred to as Quad-Net Networks. Quad-Nets are networks that can be driven by input CLK pins or by signals that are generated internally to the Fabric. Quad-Nets are driven by an element in the Fabric called the HSCKMUX. Figure 17 shows a simplified schematic diagram of the CLK input pins, the HSCKMUX elements and the associated Quad-Net networks.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 17: Low Skew Clock Structure Schematic Based Upon HSCKMUX Elements (1 of 2 Quadrants)
HSCKMUX Any Fabric Signal Logic Element CLK(0) Input Pin Global Clock Network (Quad-Net)
XX
tPGCK
HSCKMUX Any Fabric Signal Logic Element CLK(1) Input Pin
tBGCK
Global Clock Network (Quad-Net)
XX
tPGCK tBGCK
HSCKMUX Any Fabric Signal
Global Clock Network (Quad-Net)
Logic Element CLK(6) Input Pin
XX
tPGCK tBGCK
Global Clock Network (Quad-Net)
HSCKMUX Any Fabric Signal
Logic Element CLK(7) Input Pin
XX
tPGCK tBGCK
Global Clock Network (Quad-Net)
HSCKMUX Any Fabric Signal
Logic Element CLK(8) Input Pin
XX
tPGCK tBGCK
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QL903M QuickMIPSTM Data Sheet Rev. H
By instantiating the gclkbuff_25um macro with a given Fabric signal as its input, the designer can program an HSCKMUX to drive this signal on a Quad-Net (the QuickWorks tool automatically chooses which HSCKMUX to use). Each quadrant consists of five HSCKMUX elements of which one input is tied to a specific CLK input pin as shown in Table 16. Table 16: HSCKMUX Input Signals and Output Type (Per Quadrant)
Input Pin CLK(0) CLK(1) CLK(6) CLK(7) CLK(8) Internal Signals Any Signal Any Signal Any Signal Any Signal Any Signal Output Type Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net) Global clock network (Quad-Net)
As Table 16 indicates, once an HSCKMUX is used to drive an internal signal onto the Quad-Net Network, the corresponding CLK input pin is blocked from entering that quadrant. NOTE: If the sum of utilized clock input pins from Table 16 and the number of instantiated gclkbuff_25um macros is greater than five, the QuickWorks software may be unable to successfully resolve the conflicts between the CLK input pins and the internally generated clock input signals. This is dependant on several factors, but in most cases can be attributed to the size and complexity of the Fabric design. I/O Control/Hi-Drive Network The I/O Control/Hi-Drive Network is used primarily to drive high-fanout (typically other than clock or reset) signals throughout the device. Each bank of I/Os has two input-only pins entitled IOCTRL that can be programmed to drive the IQC (flip-flop clock), IQR (flip-flop reset), EQE & IQE (flip-flop enables), and IE (output enable) inputs of each I/O cell in that bank. These input-only pins also simultaneously serve as high drive inputs to any logic element input located in the adjacent quadrant. In addition, the I/O Control/Hi-Drive Network can be driven by the internal logic by instantiating the io_buff_25um macro. The QL903M has a total of eight IOCTRL input pins which are also shared with the io_buff_25um macros (i.e., if a io_buff_25um macro is utilized at a specific location, the corresponding IOCTRL input pin is ignored by the device. The performance of this network is presented in Table 35.
General Routing Network
QL903M devices are delivered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets. Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of "pass" links. Express wires provide higher performance for long routes or high fan-out nets.
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QL903M QuickMIPSTM Data Sheet Rev. H
Distributed networks are described in Advanced Clock Networks on page 29. These wires span the programmable logic and are driven by "column clock" buffers. All clock network pin buffers (both Dedicated and Global) are hard wired to individual sets of column clock buffers.
Programmable I/O
The QL903M features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single-ended I/O standards, VCCIO(A:D) specifies the input tolerance and the output drive. For example, the VCCIO(A:D) pins must be tied to a 3.3 V supply to provide 3.3 V compliance. For voltage referenced I/O standards (e.g, SSTL), the voltage supplied to the INREF(A:D) pins in each bank specifies the input switch point. The QL903M can also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 17). Table 17: I/O Standards and Applications
I/O Standard LVTTL LVCMOS25 LVCMOS18 PCI GTL+ SSTL3 SSTL2 Reference Voltage n/a n/a n/a n/a 1 1.5 1.25 Output Voltage 3.3 V 2.5 V 1.8 V 3.3 V n/a 3.3 V 2.5 V Application General Purpose General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM
As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. The QL903M has addressed these new system requirements and includes a new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in Figure 18, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either Vcc or GND.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 18: QL903M I/O Cell
IZ IQE INPUT REGISTER IQQ
+
Q E R D
>
OSEL OQQ
OUTPUT REGISTER
OQI
PAD
D
Q R
IP
>
ESEL EQE OUTPUT ENABLE REGISTER IE
D
E R
Q
IQR IQC
>
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of the input registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. The comparator and multiplexor in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. Using the output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output register. For combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. For registered control operation, the array logic drives the D input of the OE register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output register to be used for registered feedback into the logic array. 36 * www.quicklogic.com *
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QL903M QuickMIPSTM Data Sheet Rev. H
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/Os. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The QL903M contains four I/O banks. Figure 19 illustrates the I/O bank configurations. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g., PCI and LVTTL). Figure 19: Multiple I/O Banks
VCCIO(C) IOCTRL(C) INREF(C) VCCIO(B) IOCTRL(B) INREF(B)
VCCIO(D)
Embeded Computational Units
VCCIO(A)
IOCTRL(D)
IOCTRL(A)
Fabric
INREF(D) INREF(A)
Embedded RAM Blocks
PLL
ASSP
Programmable Slew Rate Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching noise of each I/O. See Table 41 through Table 43 for specific information on the slew rates for the Fabric I/O pins. The option to change the slew rate is selectable through QuickWorks in the Tools/Configure Pins window in SpDE. Programmable Weak Pull-Down A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os. The spec for pull-down current is maximum of 150 A under worst case conditions. The option to use the programmable weak pull-down resistor is selectable through QuickWorks in the Tools/Configure Pins window in SpDE.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 20: Programmable I/O Weak Pull-Down
PAD I/O Output Logic
Global Power-On Reset (POR)
The QL903M family of devices features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted. This is accomplished by holding the "Set" signal high for at least 1 ms after the VCC supply has reached 1.95 V. Figure 21: Power-On Reset
VCC
Power-on Reset
Q
XXXXXXXXXXXX
0
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QL903M QuickMIPSTM Data Sheet Rev. H
Joint Test Access Group (JTAG)
Figure 22: JTAG Block Diagram
TCK TMS TRSTB
Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) Controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAPs Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device.
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QL903M QuickMIPSTM Data Sheet Rev. H
* Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. JTAG BSDL Support * BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation) Security Links There are several security links: to disable reading logic from the array, and to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. Power-Up Loading Link The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the Power Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. See the Power-Up Loading power-up sequencing requirement for proper functionality in Figure 23.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 23: Required Power-Up Sequence when using Power-up Loading
VCCIO V3V
Voltage
VCC
VCC
< 2 ms
Time
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QL903M QuickMIPSTM Data Sheet Rev. H
Electrical Specifications
DC Characteristics
The DC Specifications are provided in Table 18 through Table 23. Table 18: Absolute Maximum Ratings
Parameter VCC Voltage VCCIO(A:D) Voltage INREF(A:D) Voltage Input Voltage Value -0.5 V to 2.0 V -0.5 V to 4.0 V 0.5 V to VCCIO(A:D) -0.5 V to VCCIO(A:D) + 0.5 V Parameter Latch-up Immunity DC Input Current BGA Package Storage Temperature V3V Voltage Value 100 mA 20 mA -55 C to +125 C -0.5 V to 4.0 V
Table 19: Operating Range
Symbol VCC V3V VCCIO(A:D) TJ K Supply Voltage ASSP I/O Supply Voltage Fabric I/O Bank Supply Voltages Junction Temperature Delay Factor -1 Speed Grade -2 Speed Grade Parameter Industrial Min. 1.90 3.00 1.71 -40 0.48 0.47 Max. 2.00 3.60 3.60 100 1.32 1.17 Commercial Min. 1.90 3.00 1.71 0 0.51 0.50 Max. 2.00 3.60 3.60 85 1.29 1.14 V V V C n/a n/a Unit
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 20: DC Characteristics
Symbol ICC ICC(STATIC) IV3V Parameter D.C. Supply Current D.C. Supply Current, Static D.C. Supply Current on V3V Conditions VI, VO = V3V, VCCIO(A:D) or GND VI, VO = V3V, VCCIO(A:D) or GND, All clock inputs are 0 MHz V3V = 3.3 V Min. Max. TBD Units mA
-
600
A
-
TBD
mA
Table 21: Fabric I/O DC Characteristics
Symbol II IOZ CI CCLOCK IOS IREF IPD Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitancea Clock Input Capacitance
a
Conditions VI = VCCIO(A:D) or GND VI = VCCIO(A:D) or GND Vo = GND Vo = VCCIO(A:D) VCCIO(A:D) = 3.6 V VCCIO(A:D) = 2.5 V VCCIO(A:D) = 1.8 V VCCIO(A:D) = 3.6 V VCCIO(A:D) = 2.5 V VCCIO(A:D) = 1.8 V
Min. -1 -15 40 -10
Max. 1 1 8 12 -180 210 10
Units A A pF pF mA mA A
Output Short Circuit Currentb D.C. Supply Current on INREF(A:D) Current on programmable Pull-down D.C. Supply Current on VCCIO(A:D)
-
150 10 10 20
A
ICCIO
-
A
a. Capacitance is sample tested only. b. Only one output at a time. Duration should not exceed 30 seconds.
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 22: ASSP I/O DC Characteristics
Symbol II IOZ CI Parameter I or I/O Input Leakage Current 3-state Output Leakage Current I/O Input Capacitance
a a
Conditions VI = V3V or GND VI = V3V or GND VO = GND VO = V3V V3V = 3.3 V
Min. -1 -
Typ.
Max. Units 1 TBD A A pF pF TBD TBD mA mA V
7 7 TBD TBD 0.90 1.24
CCLOCK Clock Input Capacitance IOS
Output Short Circuit Currentb
CPU_RESET_n, VRST_TL CPU_WARMRESET_n, EJTAG_TRST_n input low threshold CPU_RESET_n, VRST_TH CPU_WARMRESET_n, EJTAG_TRST_n input high threshold CPU_RESET_n, VRST_HYS CPU_WARMRESET_n, EJTAG_TRST_n input hysteresis
1.46
V3V = 3.3 V
1.39
1.82
2.06
V
V3V = 3.3 V
0.49
0.51
0.54
V
a. Capacitance is sample tested only. b. Only one output at a time. Duration should not exceed 30 seconds.
Table 23: Fabric DC Input and Output Levelsa
INREF VMIN VMAX VMIN LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 n/a n/a n/a n/a n/a n/a -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 0.63 INREF(A:D) - 0.2 VMIN 2.2 1.7 1.2 INREF(A:D) + 0.2 VIH VMAX VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.5 VCCIO(A:D) + 0.3 VCCIO(A:D) + 0.3 VOL VMAX 0.4 0.7 0.7 0.6 VOH VMIN 2.4 1.7 1.7 n/a IOL IOH mA mA 2.0 -2.0 2.0 -2.0 2.0 -2.0 40 n/a
0.88 1.12 -0.3 n/a n/a -0.3
0.3 x 0.5 x VCCIO(A:D) VCCIO(A:D) INREF(A:D) - 0.18 INREF(A:D) - 0.2 INREF(A:D) + 0.18 INREF(A:D) + 0.2
0.1 x 0.9 x 1.5 -0.5 VCCIO(A:D) VCCIO(A:D) 0.74 1.10 1.76 1.90 7.6 -7.6 8 -8
1.15 1.35 -0.3 1.3 1.7 -0.3
a. The data provided in Table 23 are JEDEC and PCI Specifications. QuickLogic devices either meet or exceed these requirements.
NOTE: All CLK and IOCTRL input pins are clamped to the V3V rail. Therefore, these pains can be driven up to V3V+0.3V.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 24 through Figure 24 show the VIL and VIH characteristics for Fabric I/O and clock pins. Figure 24: VIL Maximum for Fabric I/O
VILmax for IO
2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 1.8 1.89 2.5 3.3 3.6
Figure 25: VIH Minimum for Fabric I/O
VIHmin for IO
2.5 2 Voltage 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 1.8 1.89 2.5 3.3 3.6
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 26: VIL Maximum for Fabric CLOCK Pins
VILmax for CLOCK pins
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature
1.71 1.8 1.89 2.5 3.3 3.6
Voltage (V)
Figure 27: VIH Minimum for Fabric CLOCK Pins
VIHmin for CLOCK pins
2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.71 1.8 1.89 2.5 3.3 3.6
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 28 through Figure 32 show the output drive characteristics for the Fabric I/Os across various voltages and temperatures. Figure 28: Drive Current at VCCIO = 1.71 V
Drive Current @ Vccio = 1.71
35 30
Drive Current (mA)
25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.71
Output Voltage (V)
IOH: 55C IOL: 55C IOH: 25C IOL: 25C IOH: 125 IOL: 125
Figure 29: Drive Current at VCCIO = 1.8 V
Drive Current @ Vccio = 1.8
40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Output Voltage (V)
Drive Current (mA)
IOH: 55C IOL: 55C IOH: 25C IOL: 25C IOH: 125 IOL: 125
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 30: Drive Current at VCCIO = 2.5 V
Drive Current @ Vccio = 2.5V
80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 Output Voltage (V)
Drive Current (mA)
IOH: 55C IOL: 55C IOH: 25C IOL: 25C IOH: 125 IOL: 125
Figure 31: Drive Current at VCCIO = 3.3 V
Drive Current @ Vccio = 3.3V
120 Drive Current (mA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 Output Voltage (V) IOH: 55C IOL: 55C IOH: 25C IOL: 25C IOH: 125 IOL: 125
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 32: Drive Current at VCCIO = 3.6 V
Drive Current @ Vccio = 3.6V
140 120 Drive Current (mA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 3.6 Output Voltage (V) IOH: 55C IOL: 55C IOH: 25C IOL: 25C IOH: 125 IOL: 125
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QL903M QuickMIPSTM Data Sheet Rev. H
AC Characteristics
The AC Specifications in this section are shown at VCC = 1.95 V, TA = 25 C, Worst Case Corner, Fabric Speed Grade = -2 (K = 1.01) unless otherwise indicated.
ASSP PLL
Table 24: ASSP PLL Timing Parameters
Peak to Peak Jitter 200 ps VCO Frequency Range 100 to 300 MHz Minimum Lock Frequency 80 MHz Duty Cycle 45% / 55% Crystal Accuracy 100 PPM Lock Time 20 s
SDRAM Controller
Figure 33: SDRAM Waveforms SD_CLKOUT Tpd-sdclk SD_CLKIN Tco_sdram ADDR[23:0] SD_CS_n[3:0] SD_CKE[3:0] SD_DQM[3:0] SD_RAS_n SD_CAS_n SD_WE_n DATA(output)[31:0] Tsu_sdram DATA(input[31:0] Table 25: SDRAM AC Timing
Symbol TCO TSU TH TPD-SDCLK Parametera Clock to out, all control and data signals Setup time, read data Hold time, read data Maximum allowed delay, SD_CLKOUT to SD_CLKIN QL903M175 Min. 1.8 1.1 0.22 Max. 7.1 2.81 QL903M200 Min. 1.6 0.95 0.19 Max. 6.2 2.45 Units ns ns ns ns
Th_sdram
a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF load except for SD_CLKOUT, which has a load of 15 pF.
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QL903M QuickMIPSTM Data Sheet Rev. H
I/O Peripheral Controller
Figure 34: SRAM Read Waveforms
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n WEN_n D0 D1 DATA[31:0] read data addr byte lane select
Table 26: SRAM AC Read Timing Requirements
Symbol D0 D1 Parameter Access time, address and byte lane output to read data valida Access time, output enable to read data valid QL903M175 Min. Max. 8.3 13.9 QL903M200 Min. Max. 7.3 12.1 Units ns ns
a. Measurement is based on SD_CLKIN feedback with 0 ns delay and SD_CLKOUT load of 15 pF. Allowed access time will be decreased by SD_CLKIN to SD_CLKOUT delay.
Figure 35: SRAM Write Waveforms
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n D0 D1 WEN_n DATA[31:0] write data addr byte lane select
Table 27: SRAM AC Write Timing Characteristics
Symbol D0 D1 Parameter Write enable low pulse width Write output data valid before rising edge of write enablea QL903M175 Min. 1 4.7 Max. QL903M200 Min. 1 4.1 Max. Units hclk period ns
a. Measurement is based on SD_CLKIN feedback with 0 ns delay and SD_CLKOUT load of 15 pf. Setup time will be decreased by SD_CLKIN to SD_CLKOUT delay.
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QL903M QuickMIPSTM Data Sheet Rev. H
PCI Controller
Figure 36: PCI Waveforms
PCI_CLK Tval PCI_AD(output)[31:0] PCI_C_BE_n(output)[3:0] PCI_PAR(output) PCI_FRAME_n(output) PCI_IRDY_n(output) PCI_TRDY_n(output) PCI_STOP_n(output) PCI_DEVSEL_n(output) PCI_SERR_n PCI_PERR_n(output) Tval(ptp) PCI_REQ_n Tsu PCI_AD(input)[31:0] PCI_C_BE_n(input)[3:0] PCI_PAR(input) PCI_FRAME_n(input) PCI_IRDY_n(input) PCI_TRDY_n(input) PCI_STOP_n(input) PCI_DEVSEL_n(input) PCI_IDSEL PCI_PERR_n(input) PCI_LOCK_n Tsu(ptp) PCI_GNT_n Th
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 28: PCI AC Timing
Parametera tCYC tHIGH tLOW - tVAL tVAL (PTP) tON tOFF tSU tSU (PTP) tH tRST tRST-CLK PCI_CLK Cycle Time PCI_CLK High Time PCI_CLK Low Time PCI_CLK Slew Rate PCI_CLK to Signal Valid Delay PCI_CLK to Signal Valid Delay point-to-point signalsb Float to Active Delay Active to Float Delay Input Setup Time to PCI_CLK bused signals Input Setup Time to PCI_CLK point-to-point Input Hold Time from PCI_CLK Reset Active Time after power stable Reset Active Time after PCI_CLK stable PCI_RST_n high to first configuration access PCI_RST_n high to first PCI_FRAME_n assertion 66 MHz Min. 15 6 6 1.5 2 2 2 3 5 0 1 100 Max. 4 6 6 14 40 2 5 2 5 Min. 30 11 11 1 2 2 2 7 10, 12 0 1 100 33 MHz Max. 4 11 12 28 40 Units ns ns ns V/ns ns ns ns ns ns ns ns ms
s
ns clocks clocks
tRST-OFFc Reset Active to output float delay tRHFA tRHFF
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n. b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n. c. All output drivers must be 3-stated when PCI_RST_n is active.
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Preliminary
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QL903M QuickMIPSTM Data Sheet Rev. H
System SRAM
Figure 37: System SRAM Block Diagram
Fabric
SRAM 4 Interface
SRAM 3 Interface
SRAM 2 Interface
SRAM 1 Interface
Address, Write Data, Clock and Control
Address, Write Data, Clock, and Control
Address, Write Data, Clock, and Control
Read Data
Read Data
System Target Interface 48 32 48 32 48 32 48 32
4K SRAM (1024x32)
4K SRAM (1024x32)
Read Data
4K SRAM (1024x32)
4K SRAM (1024x32)
System Bus
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Read Data
GL_SR_SELECT Register
Address, Write Data, Clock, and Control
SRAM Block
QL903M QuickMIPSTM Data Sheet Rev. H
Figure 38: System SRAM Fabric Interface Read Timing (one SRAM interface shown)
Figure 39: System SRAM Fabric Interface Write Timing (one SRAM interface shown)
Table 29: System SRAM Fabric Interface Timing
Symbol tSA tHA tSWD tHWD tSWE tHWE tSWEb tHWEb tCORD Parameter Setup time, address input Hold time, address input Setup time, write data input Hold time, write data input Setup time, write enable input Hold time, write enable input Setup time, byte write enable input Hold time, byte write enable input Clock-to-out time, read data output QL903M175 Min. 1.40 0.48 1.81 0.56 0.60 0.54 1.13 0.94 Max. 5.17 QL903M200 Min. 1.23 0.42 1.59 0.49 0.53 0.48 0.99 0.82 Max. 4.52 Units ns ns ns ns ns ns ns ns ns
NOTE: For timing values related to each individual ASSP SRAM block, refer to Table 46 and Table 47.
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Preliminary
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55
QL903M QuickMIPSTM Data Sheet Rev. H
Logic Cells
Figure 40: QL903M Logic Cell
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR
AZ
OZ
DQ
QZ
NZ
DQ
Q2Z
FZ
Figure 41: Logic Cell Flip-Flop
SET D CLK RESET Q
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 42: Logic Cell Flip-Flop Timings--First Waveform
CLK tCWHI (min) SET tCWLO (min)
RESET
Q tRESET tRW tSET
tSW
Figure 43: Logic Cell Flip-Flop Timings--Second Waveform
CLK
D
tSU
tHL
Q tCO
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57
QL903M QuickMIPSTM Data Sheet Rev. H
Table 30: Logic Cells
Symbol Logic Cells tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Value Min. 0.28 ns 0.25 ns 0 ns 0.22 ns 0.46 ns 0.46 ns 0.3 ns 0.3 ns Max. 0.95 ns 0.52 ns 0.69 ns 1.09 ns -
Dual-Port SRAM Modules
Figure 44: RAM Module
[7:0] [17:0]
WA WD WE WCLK
RE RCLK RA RD ASYNCRD RAM Module [7:0] [17:0]
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 45: RAM Cell Synchronous Write Timing
WCLK
WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA
Table 31: RAM Cell Synchronous Write Timing
Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.675 ns 0 ns 0.654 ns 0 ns 0.623 ns 0 ns 4.38 ns Parameter Value Min. Max.
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Preliminary
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59
QL903M QuickMIPSTM Data Sheet Rev. H
Figure 46: RAM Cell Synchronous and Asynchronous Read Timing
RCLK
RA
tSRA tHRA
RE
tSRE tHRE
new data
RD
old data
tRCRD rPDRD
Table 32: RAM Cell Synchronous and Asynchronous Read Timing
Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 0.686 ns 0 ns 0.243 ns 0 ns 4.38 ns Parameter Value Min. Max.
RAM Cell Asynchronous Read Timing rPDRD 2.06 ns
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QL903M QuickMIPSTM Data Sheet Rev. H
ECUs
Figure 47: ECU Block Diagram
S3 S2 S1 CIN SIGN2 SIGN1
A[15:8] A[7:0]
3-4 Decoder
D C B A
00 01 Q[16:0]
8-bit Multiplier
16-bit Adder
DQ
10
A[15:0] B[15:0]
CLK RESET
Table 33: ECU Mode Select Criteria
Instruction S1 0 0 0 0 1 1 1 1 A2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulateb Add Multiply (registered)
c
ECU Performancea, -2 WCC tPD 6.6 ns max. 8.8 ns max. 3.1 ns max. tSU 3.9 ns min. 9.6 ns min. 9.6 ns min. 9.6 ns min. 3.9 ns min. tCO 1.2 ns max. 1.2 ns max. 1.2 ns max. 1.2 ns max. 1.2 ns max.
Multiply-Add (registered) Multiply-Accumulate Add (registered)
a. tPD, tSU, and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max. clk frequency to 238 MHz. c. B (15:0) set to zero.
NOTE: Timing numbers in Table 33 represent -2 Worst Case Commercial conditions.
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Preliminary
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61
QL903M QuickMIPSTM Data Sheet Rev. H
Fabric PLL
Figure 48: QL903M Fabric PLL Block Diagram
Lock Detect
LOCK_DETECT
Phase Frequency Detector FB_PLL_CLKIN
Charge Pump
VCO FB_PLL_PADOUT
M = 2, 4 or 8 :M FB_PLL_RESET_n
FD = 1, 2, 3, 4 or 8 : FD
Phase = 0, 90, 180, 270 Phase Adj. PLLCLK_OUT
Phase = 0, 90, 180, 270 Phase Adj.
PLLCLK_OUT2
FD0 FD1 FD2
M0 M1
PS0 PS1
PS2 PS3
Table 34: Fabric PLL Timing Parameters
Peak to Peak Jitter 200 ps VCO Frequency Range 100 to 300 MHz Minimum Lock Frequency 80 MHz Duty Cycle 45% / 55% Crystal Accuracy 100 PPM Lock Time 20 s Propagation Delay FB_PLL_CLKIN to FB_PLL_PADOUT TBD ns
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QL903M QuickMIPSTM Data Sheet Rev. H
Clock Network
Table 35: I/O Control Network/Local High-Drive
Destination I/O (far) I/O (near) Skew From Pad (max.) 1.00 ns 0.63 ns 0.37 ns From Array (max.) 1.14 ns 0.78 ns 0.36 ns
Figure 49: Dedicated Clock Structure Schematic
PLL MUX FB_PLL_CLKIN Input Pin Fabric PLL PLLCLK_OUT2 Logic Element CLK(4)/DEDCLK Input Pin Dedicated Clock Network
XX
tPDEDCLK tPPLL_DEDCLK
Table 36: Dedicated Clock Network Performance
Symbol tPDEDCLK tSKEWDEDCLK tPPLL_DEDCLK Parameters Delay from dedicated clock input pin to logic cell flip-flop Skew on dedicated clock network Delay from Fabric PLL input pin to logic cell flip-flop Value Min. Max. 1.69 ns 0.25 ns 2.20 ns
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 50: Global Clock Structure Schematic
Fabric PLL Global Clock Network hclk Internal Signal Logic Element CLK Input Pin
FB_PLL_CLKIN Input Pin
XX XX XX
tPGCK tPPLL_GCK tBGCK
Table 37: Global Clock Network Performance
Symbol tPGCK tBGCK tSKEWGCK tPPLL_GCK Parameter Global clock pin delay to quad net Global clock tree delay (quad net to logic cell flip-flop) Skew on global clock network Global clock tree delay, Fabric PLL input to logic cell flip-flop Value Min. Max. 1.95 ns 0.28 ns 0.25 ns TBD ns
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QL903M QuickMIPSTM Data Sheet Rev. H
I/O Cells
Figure 51: QL903M Input Register Cell
tISU + tSID
QE R D
PAD
Table 38: Standard Input Delays
Symbol Standard Input Delays tSID (LVTTL) tSID (LVCMOS2) Parameter To get the total input delay add this delay to tISUa LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V PCI input delay: Peripheral Component Interconnect for 3.3 V Min. Value Max. 0.82 ns 0.82 ns TBD ns 0.94 ns 0.94 ns 0.94 ns 0.82 ns
tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications tSID (GTL+) tSID (SSTL3) tSID (SSTL2) tSID (PCI)
a. See Table 39 for tISU value.
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Preliminary
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 52: QL903M Input Register Cell Timing
R
CLK
D
tIS U tIH L
Q
tIC O tIR S T
E
tIE S U tIE H
Table 39: Input Register Cell
Symbol Input Register Cell Only tISU tIHL tICO tIRST tIESU tIEH Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. Input register clock-to-out: time taken by the flip-flop to output after the active clock edge. Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low). Input register clock enable setup time: time "enable" must be stable before the active clock edge. Input register clock enable hold time: time "enable" must be stable after the active clock edge. 2.15 ns 0 ns 0.40 ns 0 ns 0.30 ns 0.82 ns Parameter Value Min. Max.
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QL903M QuickMIPSTM Data Sheet Rev. H
Figure 53: QL903M Output Register Cell
PAD OUTPUT REGISTER
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Preliminary
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67
QL903M QuickMIPSTM Data Sheet Rev. H
Figure 54: QL903M Output Register Cell Timing
H L H Z L H Z L
tOUTLH
H L H tPZH Z L H Z L
tOUTHL
tPZL tPHZ
tPLZ
Table 40: Output Register Cell
Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP tOUTSU tOUTH tOUTRST tOESU tOEH tOERST Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock-to-out delay: time taken by the flip-flop to output after the active clock edge. Output register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. Output register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. Output register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low). Output enable register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge. Output enable register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge. Output enable register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low). TBD TBD TBD TBD 4.46 ns (fast slew) 6.12 ns (slow slew) 3.31 ns (fast slew) 5.50 ns (slow slew) 4.19 ns (fast slew) 6.22 ns (slow slew) 4.19 ns (fast slew) 4.35 ns (slow slew) 5.97 ns (fast slew) 3.79 ns (slow slew) 3.58 ns (fast slew) 5.75 ns (slow slew) 6.50 ns (fast slew) TBD ns (slow slew) TBD Parameter Value Min. Max.
-
TBD
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 40: Output Register Cell (Continued)
Symbol tOEESU tOEEH tOECOP Parameter Output enable register clock enable setup time: time "enable" must be stable before the active clock edge. Output enable register clock enable hold time: time "enable" must be stable after the active clock edge. Output enable register clock-to-out delay: time taken by the flip-flop to output after the active clock edge. Value Min. TBD TBD Max. TBD
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Preliminary
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69
QL903M QuickMIPSTM Data Sheet Rev. H
Table 41: Fabric Output Slew Rates @ VCCIO(A:D) = 3.3 V, 25 C
Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns
Table 42: Fabric Output Slew Rates @ VCCIO(A:D) = 2.5 V, 25 C
Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns
Table 43: Fabric Output Slew Rates @ VCCIO(A:D) = 1.8 V, 25 C
Fast Slew Rising Edge Falling Edge TBD V/ns TBD V/ns Slow Slew TBD V/ns TBD V/ns
Table 44: ASSP Output Slew Rates @ V3V = 3.3 V, 25 C by Signal Groups
ASSP Output Groupa SDRAM Signals (except SD_CLKOUT) SD_CLKOUT SRAM Control Signals PCI Signals UART Signals Slew (V/ns) Maximum Rising 3.00 4.20 2.30 5.35 1.33 Falling 3.87 5.30 2/97 3.20 1.59 Slew (V/ns) Minimum Rising 0.96 1.50 0.55 1.90 0.30 Falling 1.12 1.95 0.58 2.43 0.30
a. Loads are as follows: SDRAM signals - 35 pF, SD_CLKOUT = 15 pF, SRAM signals = 50 pF, PCI signals = 10 pF, and UART signals = 50 pF.
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QL903M QuickMIPSTM Data Sheet Rev. H
ASSP to Fabric Timing
Table 45 through Table 47 list the synchronous and asynchronous timing for the QL903M ASSP to Fabric interface ports and ASSP I/O pins. Note the following regarding the Fabric timing: * * * * fb_int is asynchronous and is synchronized inside the core. fb_bigendian is a static signal and reflects the value on the CPU_BIGENDIAN pin. pm_* and si_* signals are synchronous to the internal MIPS clock which is at least twice the hclk frequency. This internal clock is not driven to the Fabric. All AF_PCI_* signals are static.
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Preliminary
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71
QL903M QuickMIPSTM Data Sheet Rev. H
ASSP to Fabric Synchronous Output Timing Table 45: ASSP to Fabric Interface Synchronous Output Timing
Clock Reference hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT * * * * Signal ahb_hready_in ahbm_hgrant ahbm_hrdata(31:0) ahbm_hresp(1:0) ahbs_haddr(31:0) ahbs_hburst(2:0) ahbs_hprot(3:0) ahbs_hsel ahbs_hsize(2:0) ahbs_htrans(1:0) ahbs_hwdata(31:0) ahbs_hwrite apbs_paddr(15:2) apbs_penable apbs_psel0 apbs_psel1 apbs_psel2 apbs_pwdata(31:0) apbs_pwrite hresetn M1_MDC M1_MDO M1_MDO_EN_N M2_MDC M2_MDO M2_MDO_EN_N pm_dcachehit pm_dcachemiss pm_dtlbhit pm_dtlbmiss pm_icachehit pm_icachemiss pm_instncomplete pm_itlbhit QL903M175 tCO (ns max.) QL903M200 tCO (ns max.)
6.05 7.63 7.94 6.05 6.03 5.61 4.75 6.23 5.63 6.23 5.92 5.55 3.06 2.98 3.32 3.36 3.31 3.32 3.05 4.07 2.88 2.84 2.87 3.24 3.26 3.30 2.99 2.85 2.76 2.84 2.86 2.70 2.60 2.72
5.29 6.68 6.95 5.30 5.27 4.90 4.15 5.45 4.93 5.45 5.18 4.85 2.68 2.61 2.91 2.94 2.90 2.91 2.67 3.56 2.52 2.48 2.51 2.84 2.85 2.89 2.61 2.50 2.42 2.49 2.50 2.36 2.27 2.38
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 45: ASSP to Fabric Interface Synchronous Output Timing (Continued)
Clock Reference CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT CPU_PLL_CLKOUT hclk hclk hclk SR1_CLK SR2_CLK SR3_CLK SR4_CLK Signal pm_itlbmiss pm_jtlbhit pm_jtlbmiss pm_wtbmerge pm_wtbnomerge si_rp si_sleep tm_overflow2 tm_overflow3 tm_overflow4 SR1_RDATA(31:0) SR2_RDATA(31:0) SR3_RDATA(31:0) SR4_RDATA(31:0) QL903M175 tCO (ns max.) QL903M200 tCO (ns max.)
2.70 2.61 2.69 4.49 2.88 3.24 2.27 2.94 2.85 2.94 4.49 5.17 4.30 4.04
2.36 2.28 2.35 3.93 2.52 2.83 1.99 2.57 2.50 2.57 3.93 4.52 3.76 3.53
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Preliminary
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QL903M QuickMIPSTM Data Sheet Rev. H
Fabric to ASSP Interface Timing Requirements Table 46: Fabric to ASSP Interface Timing Requirements
Clock Reference hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk hclk M1_RXCLK M1_RXCLK M1_RXCLK hclk M2_RXCLK M2_RXCLK M2_RXCLK SR1_CLK SR1_CLK SR1_CLK SR1_CLK SR2_CLK SR2_CLK SR2_CLK SR2_CLK * * * * Signal ahbm_haddr(31:0) ahbm_hburst(2:0) ahbm_hbusreq ahbm_hprot(3:0) ahbm_hsize(2:0) ahbm_htrans(1:0) ahbm_hwdata(31:0) ahbm_hwrite ahbs_hrdata(31:0) ahbs_hready_out ahbs_hresp(1:0) apbs_prdata0(31:0) apbs_prdata1(31:0) apbs_prdata2(31:0) M1_COL M1_CRS M1_MDI M1_RXD(3:0) M1_RXDV M1_RXER M2_COL M2_CRS M2_MDI M2_RXD(3:0) M2_RXDV M2_RXER SR1_ADDR(11:2) SR1_WDATA(31:0) SR1_WEN SR1_WENb(3:0) SR2_ADDR(11:2) SR2_WDATA(31:0) SR2_WEN SR2_WENb(3:0) QL903M175 tSU (ns min) tH (ns min) QL903M200 tSU (ns min) tH (ns min)
3.64 3.33 3.47 4.42 3.07 3.56 3.06 2.98 3.25 4.15 4.03 3.44 3.42 3.34
1.39 0.03 0 0 0.96 0.30 1.23 0.86 0.89 0.46 0.77 0.53 0.51 0.65
3.18 2.91 3.04 3.87 2.69 3.12 2.68 2.61 2.84 3.63 3.52 3.01 3.00 2.92
1.21 0.03 0 0 0.84 0.26 1.07 0.75 0.78 0.40 0.67 0.46 0.45 0.57
Asynchronous input - no requirement Asynchronous input - no requirement
0 0.67 1.06 0.57
1.38 0 0 0
0 0.58 0.92 0.50
1.20 0 0 0
Asynchronous input - no requirement Asynchronous input - no requirement
0 0.93 1.65 0.71 1.18 1.36 0.54 0.27 0.93 1.81 0.53 0.43
1.62 0.35 0 0.09 0.45 0.15 0 0.66 0.48 0.48 0.54 0.94
0 0.81 1.45 0.62 1.03 1.19 0.47 0.24 0.81 1.59 0.46 0.38
1.42 0.31 0 0.08 0.39 0.13 0 0.58 0.42 0.42 0.48 0.82
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 46: Fabric to ASSP Interface Timing Requirements (Continued)
Clock Reference SR3_CLK SR3_CLK SR3_CLK SR3_CLK SR4_CLK SR4_CLK SR4_CLK SR4_CLK hclk hclk hclk hclk hclk Signal SR3_ADDR(11:2) SR3_WDATA(31:0) SR3_WEN SR3_WENb(3:0) SR4_ADDR(11:2) SR4_WDATA(31:0) SR4_WEN SR4_WENb(3:0) tm_extclk1 tm_extclk2 tm_extclk3 tm_extclk4 tm_fbenable QL903M175 tSU (ns min) tH (ns min) QL903M200 tSU (ns min) tH (ns min)
0.53 1.45 0.21 0.26 1.40 1.78 0.60 1.13 0 0 0 0 0
0.34 0.56 0.26 0.59 0.23 0.15 0.15 0.52 1.58 1.57 1.57 1.61 1.60
0.46 1.27 0.19 0.23 1.23 1.56 0.53 0.99 0 0 0 0 0
0.30 0.49 0.23 0.52 0.20 0.13 0.13 0.46 1.38 1.37 1.37 1.41 1.40
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Preliminary
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QL903M QuickMIPSTM Data Sheet Rev. H
ASSP Propagation Delays Table 47: ASSP Propagation Delays
Starting Signal Path: Fabric to Fabric through ASSP ahbm_haddr(31:0) ahbm_haddr(31:0) ahbm_hburst(2:0) ahbm_hburst(2:0) ahbm_hbusreq ahbm_hprot(3:0) ahbm_hsize(2:0) ahbm_htrans(1:0) ahbm_htrans(1:0) ahbm_hwdata(31:0) ahbm_hwrite ahbs_hrdata(31:0) ahbs_hready_out ahbs_hready_out ahbs_hresp(1:0) ahbs_hresp(1:0) apbs_prdata0(31:0) apbs_prdata1(31:0) apbs_prdata2(31:0) Path: ASSP Input Pin to Fabric CPU_BIGENDIAN M1_TXCLK M1_TXCLK M2_TXCLK M2_TXCLK CPU_PLL_CLKIN Path: ASSP Input Pin to ASSP Output Pin CPU_PLL_CLKIN CPU_PLL_CLKOUT fb_bigendian M1_TXD(3:0) M1_TXEN M2_TXD(3:0) M2_TXEN hclk ahbs_haddr(31:0) ahbs_hsel ahbm_hgrant ahbs_hburst(2:0) ahbm_hgrant ahbs_hprot(3:0) ahbs_hsize(2:0) ahbs_htrans(1:0) ahbm_hgrant ahbs_hwdata(31:0) ahbs_hwrite ahbm_hrdata(31:0) ahb_hready_in ahbm_hgrant ahbm_hgrant ahbm_hresp(1:0) ahbm_hrdata(31:0) ahbm_hrdata(31:0) ahbm_hrdata(31:0) Ending Signal QL903M175 tPD (ns max) QL903M200 tPD (ns max)
1.80 2.12 1.78 2.33 2.66 1.30 1.64 1.86 2.31 1.80 1.71 2.37 1.79 3.31 2.07 3.17 2.75 2.66 2.57 1.97 2.32 2.62 3.19 3.14 1.64 2.38
1.57 1.86 1.55 2.04 2.32 1.14 1.43 1.63 2.02 1.57 1.49 2.07 1.57 2.90 1.81 2.77 2.41 2.33 2.25 1.72 2.03 2.29 2.79 2.75 1.43 2.09
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QL903M QuickMIPSTM Data Sheet Rev. H
Package Thermal Characteristics
Thermal Resistance Equations:
JC JA
= (TJ - TC)/P = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/JA Parameter Description:
JC: JA:
TJ: TC: TA: P: PMAX: TJMAX: TAMAX:
Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction temperature Case temperature Ambient temperature Power dissipated by the device while operating The maximum power dissipation for the device Maximum junction temperature Maximum ambient temperature
NOTE: Maximum junction temperature (TJMAX) is 125C. To calculate the maximum power dissipation for a device package look up JA from Table 48, pick an appropriate TAMAX and use: PMAX = (125C - TAMAX)/JA
Table 48: Package Thermal Characteristics
Package Description Pin Count Package Type 544 PBGA
JA ( C/W) @ Various Flow Rates (m/sec)
0 20 1 16.4 2 15.5 2.5 14.4
JC ( C/W)
8.0
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QL903M QuickMIPSTM Data Sheet Rev. H
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below: PTOTAL (mW) = 0.350 + fFabric [0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 CKLD + 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] + 28.1 fasspio + 5.55 fmips Where
LC CKBF CLBF CKLD RAM PLL INP OUTP
fFabric fasspio fmips
= number of logic cells in the design = number of clock buffers = number of column clock buffers = number of loads connected to the column clock buffers = number of RAM blocks = number of PLLs = number of input pins = number of output pins = average switching frequency of Fabric = average switching frequency of ASSP I/O signals = CPU operational frequency
NOTE: To learn more about power consumption, please refer to Application Note 60 at http://www.quicklogic.com/images/appnote60.pdf.
Power-Up Sequencing
Figure 55: Power-Up Sequencing
VCCIO V3V
|V3V - VCC| MAX |VCCIO - VCC| MAX
Voltage
VCC
VCC
400 us
Time
When powering up a device, the VCC, VCCIO and V3V rails must take 400 s or longer to reach the maximum value (refer to Figure 55). NOTE: Ramping VCC, VCCIO and V3V to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (V3V - VCC)MAX and (VCCIO -VCC)MAX 500 mV when ramping up the power supply. 78 * www.quicklogic.com *
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QL903M QuickMIPSTM Data Sheet Rev. H
Board Layout Recommendations
This section describes various recommendations for design and layout of the printed circuit board (PCB) that is used with the QL903M.
PLL Power Supply Filtering
The PLL analog power supply inputs of the QL903M are: Fabric PLL: GND_FB_PLL and V3V_FB_PLL CPU PLL: GND_CPU_PLL and V3V_CPU_PLL These signals must be filtered as shown in Figure 56: Figure 56: PLL Power Supply Filtering Circuits
P22 C 0.1 F GND_FB_PLL T21 C 0.01 F R 0 GND +3.3 V L C 0.1 F +3.3 V
V3V_FB_PLL
V3V_CPU_PLL
P5 C 0.1 F U6 C 0.01 F
L C R 0 GND 0.1 F
GND_CPU_PLL
For best performance and noise immunity, separate or split power planes for digital ground (GND), analog ground (FB_PLL_GND and CPU_PLL_GND), digital VCC (VCC), digital 3.3 V (V3V) and analog 3.3 V (FB_PLL_V3V and CPU_PLL_V3V) should be used.
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QL903M QuickMIPSTM Data Sheet Rev. H
Bypass Capacitor Guidelines
This section outlines the recommendations for capacitive bypassing for the various digital supplies of the QL903M. Table 49 indicates the minimum recommended number of 0.1 F and 0.01 F capacitors for each digital supply input on the QL903M. A minimum total quantity of 48 bypass capacitors is recommended. Table 49: Minimum Recommended Number of Bypass Capacitors for Each Digital Supply Input
Supply Input VCC VCCIO(A) VCCIO(B) VCCIO(C) VCCIO(D) V3V Totals: Recommended Number of Capacitors 0.1 F, X7R Type (or better) 8 2 2 2 2 8 24 Recommended Number of Capacitors 0.01 F, X7R Type (or better) 8 2 2 2 2 8 24 Totals 16 4 4 4 4 16 48
NOTE: All capacitors should be X7R type (or better) and 0603 package size is recommended. Capacitor Placement Eight capacitors (all for the VCC supply) should be placed directly under the device (in the area between the 8x8 GND pads in the center of the device and the outer rows of signal pads) on the back side of the PCB. The remaining forty capacitors (for the remainder of VCC and all other supplies) should be placed around the perimeter of the chip, also preferably on the back side of the board. Listed below is the proximity location priority (1=highest). Higher priority filters and/or capacitors should be placed closest to the QL903M. 1. PLL bypass capacitors and filter circuitry 2. VCC bypass capacitors 3. VCCIO/V3V bypass capacitors
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QL903M QuickMIPSTM Data Sheet Rev. H
Signal Descriptions
Pin Descriptions
Table 50: Pin Descriptions
Pin PCI Signals PCI Address and Data. PCI_AD(31:0) contain the multiplexed address and data. A bus transaction consists of a single address phase (or two address phases for 64-bit addresses) followed by one or more data phases. The QuickMIPS chip supports both read and write bursts. The address phase occurs in the first clock cycle when PCI_FRAME_n is asserted. During the address phase, PCI_AD(31:0) contain a 32-bit physical address. For I/O, this I/O is a byte address; for configuration and memory, it is a DWORD (32-bit) address. During data phases, PCI_AD(7:0) contain the least-significant byte, and PCI_AD(31:24) contain the most-significant byte. Write data is stable and valid when PCI_IRDY_n is asserted; read data is stable and valid when PCI_TRDY_n is asserted. Data is transferred when both PCI_IRDY_n and PCI_TRDY_n are asserted. Connect to GND if the PCI Controller is unused. Bus Command and Byte Enables. Bus commands and byte enables are multiplexed on PCI_C_BE_n(3:0). During the address phase of a transaction (PCI_FRAME_n is asserted), PCI_C_BE_n(3:0) define the bus command as shown in the following table (only valid combinations are shown). PCI_C_BE_n(3:0) 0000 0001 0010 0011 0110 0111 1010 1011 1100 1101 1110 1111 Bus Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate I/O Function
PCI_AD(31:0)
PCI_C_BE_n(3:0)
I/O
During each data phase, PCI_C_BE_n(3:0) are byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. PCI_C_BE_n(0) applies to byte 0 (PCI_AD(7:0)) and PCI_C_BE_n(3) applies to byte 3 (PCI_AD(31:24)). Connect to GND if the PCI Controller is unused. PCI Device Select. When asserted low, PCI_DEVSEL_n indicates the driving device has decoded its address as the target of the current access. As an input, I/O PCI_DEVSEL_n indicates whether any device on the bus has responded. Connect to 3.3 V if the PCI Controller is unused.
PCI_DEVSEL_n
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin I/O Function PCI Cycle Frame. The current master asserts PCI_FRAME_n to indicate the beginning and duration of a bus transaction. While PCI_FRAME_n is asserted, data transfers I/O continue. When PCI_FRAME_n is deasserted, the transaction is in the final data phase or has completed. Connect to 3.3 V if the PCI Controller is unused. PCI_GNT_n I PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been granted. PCI_GNT_n is ignored while PCI_RST_n is asserted. Connect to 3.3 V if the PCI Controller is unused. PCI_IDSEL I PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write transactions (PCI_C_BE_n(3:0) = 1010 or 1011). Connect to GND if the PCI Controller is unused. PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip. PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains asserted until the interrupt is cleared. PCI_INTA_n O Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only. However, such an interrupt controller can be built into the Fabric. Leave unconnected if the PCI Controller is unused. PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator) asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD(31:0) during a write, or that it is ready to accept data on PCI_AD(31:0) during a read. PCI_IRDY_n I/O A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD(31:0). During a read, a low assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. Connect to 3.3 V if the PCI Controller is unused. PCI Parity. Parity is driven high or low to create even parity across PCI_AD(31:0) and PCI_C_BE_n(3:0). The master drives PCI_PAR for address and write data phases; the I/O target drives PCI_PAR for read data phases. Connect to 3.3 V if the PCI Controller is unused. PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI transactions except a Special Cycle. The QuickMIPS chip drives PCI_PERR_n low two clocks following the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n is one clock for each data phase that a data parity I/O error is detected. (If sequential data phases each have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.) PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals. Connect to 3.3 V if the PCI Controller is unused.
PCI_FRAME_n
PCI_PAR
PCI_PERR_n
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin PCI_REQ_n I/O O Function PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus. PCI_REQ_n is 3-stated while PCI_RST_n is asserted. Leave unconnected if the PCI Controller is unused. PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset). The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK. Connect to GND if the PCI Controller is unused. PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data parity error on the Special Cycle command, or any other system error where the result is catastrophic. PCI_SERR_n is open drain and is actively driven for a single PCI clock. The assertion of PCI_SERR_n is synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can take two to three clock periods to fully restore PCI_SERR_n. Leave unconnected if the PCI Controller is unused. PCI_STOP_n I/O PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop the current transaction. Connect to 3.3 V if the PCI Controller is unused. PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave (target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD(31:0) during a read, or that it is ready to accept data on PCI_AD(31:0) during a write. PCI_TRDY_n I/O A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD(31:0). During a write, a low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. Connect to 3.3 V if the PCI Controller is unused. PCI_CLK Ethernet MAC Signals Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference for the transfer of the RXDV and RXD(3:0) signals from the Ethernet PHY Controller to the MAC core. The Ethernet PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the received signal on the Ethernet cable. Connect to GND if the Ethernet Controller is unused. I PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz. Connect to GND if the PCI Controller is unused.
PCI_RST_n
I
PCI_SERR_n
O
M1_RXCLK, M2_RXCLK
I
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin I/O Function Ethernet Transmit Clock. TXCLK is a continuous clock that provides a timing reference for the transfer of the TXEN and TXD signals from the MAC core to the Ethernet PHY Controller. The Ethernet PHY Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Connect to GND if the Ethernet Controller is unused. Memory Controller Interface Signals SRAM Byte Enables. BLS_n(3:0) indicates the validity of the bytes on DATA(31:0) for external SRAM read and write accesses. BLS_n(3) corresponds to DATA(31:24) BLS_n(2) corresponds to DATA(23:16) BLS_n(1) corresponds to DATA(15:8) BLS_n(0) corresponds to DATA(7:0) Chip Selects. These signals are the active-low chip selects for the SRAM. Memory Address. This 24-bit bus contains the memory address for external SRAM and SDRAM accesses. Memory Data. This 32-bit bus contains the memory read/write data for SRAM and SDRAM accesses. SRAM Output Enable. OE_n is the active-low output enable to the external SRAM. SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external SDRAM. SDRAM Clock Enables. If low, these signals indicate to the externally connected SDRAM to enter the power-down state. SDRAM Input Clock. SD_CLKIN should be tied to SD_CLKOUT on the PCB. Internal to the QuickMIPS device, all SDRAM command, address and data signals are synchronized with SD_CLKIN. If a clock buffer is used to drive the SDRAM devices, this buffer should be a zero-delay type buffer, and SD_CLKIN should be tied to one of the buffer outputs. SDRAM Output Clock. SD_CLKOUT is the clock source for the externally connected SDRAMs. This signal may be connected to a zero-delay buffer to drive multiple SDRAM devices. SD_CLKOUT is equal in frequency to the internal System Bus clock and hclk. See Table 2 for additional details. SDRAM Output Chip Select. SD_CS_n(1:0) are the active-low chip selects for the external SDRAMs. SDRAM Data Mask. SD_DQM(3:0) are the data masks for DATA(31:0) during SDRAM read and write accesses. SD_DQM(3) corresponds to DATA(31:24) SD_DQM(2) corresponds to DATA(23:16) SD_DQM(1) corresponds to DATA(15:8) SD_DQM(0) corresponds to DATA(7:0) SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external SDRAM. SDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs. SRAM Write Enable. WE_n indicates whether transactions between the QuickMIPS chip and the external SRAM are reads (WE_n is high) or writes (WE_n is low).
M1_TXCLK, M2_TXCLK
I
BLS_n(3:0)
O
CS_n(7:0) ADDR(23:0) DATA(31:0) OE_n SD_CAS_n SD_CKE(1:0)
O O I/O O O O
SD_CLKIN
I
SD_CLKOUT
O
SD_CS_n(1:0)
O
SD_DQM(3:0)
O
SD_RAS_n SD_WE_n WE_n
O O O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin UART Interface Signals U1_CTS_n I UART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data. Connect to GND if the UART is unused. U1_DCD_n I UART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected. Connect to GND if the UART is unused. U1_DSR_n I UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the link to the QuickMIPS UART. Connect to GND if the UART is unused. U1_DTR_n O UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to establish the external communication link. Leave unconnected if the UART is unused. UART1 Ring Indicator. This input is an active-low ring indicator. U1_RI_n I Connect to 3.3 V if the UART is unused. U1_RTS_n O UART1 Request to Send. The QuickMIPS chip asserts this signal low to inform the external device that the UART is ready to send data. Leave unconnected if the UART is unused. U1_RXD_SIRIN I UART1 Receive Serial Data/SIR Receive Serial Data. This input receives serial data from either the UART or the IrDA block. Connect to GND if the UART is unused. U1_TXD_SIROUT O UART1 Transmit Serial Data/SIR Transmit Serial Data. This output transmits serial data to either the UART or IrDA block. Leave unconnected if the UART is unused. U2_RXD_SIRIN I UART2 Receive Serial Data/SIR Receive Serial Data. This input receives serial data from either the UART or the IrDA block. Connect to GND if the UART is unused. U2_TXD_SIROUT Test Interface Signals EJTAG Test Clock. This clock controls the updates to the TAP Controller and the shifts through the Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are used. Connect to 3.3 V through a 1 K resistor. EJTAG_TDI I EJTAG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register. This input is sampled on the rising edge of EJTAG_TCK. Connect to 3.3 V through a 1 K resistor.
(c) 2004 QuickLogic Corporation
I/O
Function
O
UART2 Transmit Serial Data/SIR Transmit Serial Data. This output transmits serial data to either the UART or IrDA block. Leave unconnected if the UART is unused.
EJTAG_TCK
I
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin EJTAG_TDO I/O O Function EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or data register. This signal changes on the falling edge of EJTAG_TCK. Connect to 3.3 V through a 10 K resistor. EJTAG_TMS I EJTAG Test Mode Select. This input is the control signal for the TAP Controller. It is sampled on the rising edge of EJTAG_TCK. Connect to 3.3 V through a 1 K resistor. EJTAG_TRST_n I EJTAG Test Reset. This signal is asserted asynchronously to reset the TAP Controller, Instruction register, and EJTAGBOOT indication. Connect to GND through a 1 K resistor. EJTAG_DEBUGM O Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be used to bring the chip out of low power mode. Debug Exception Request. Assertion high of this input indicates a debug exception request is pending. The request is cleared when debug mode is entered. Requests that occur while the chip is in debug mode are ignored. Connect to 3.3 V through a 1 K resistor. Fabric Interface Signals I/O(A) Programmable Input/Output/3-State/Bidirectional Pin in Bank A. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank B. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank C. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Input/Output/3-State/Bidirectional Pin in Bank D. If an I/O is not I/O used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Programmable Global Clock Pin. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. Connect to 3.3V or GND if unused. CLK(4)/ DEDCLK Low Skew Dedicated Clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, flip-flops). Connect to 3.3V or GND if unused. Differential I/O Reference Voltage. INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 23 for the appropriate standard. Connect to GND when using TTL, PCI or LVCMOS.
EJTAG_DINT
I
I/O(B)
I/O(C)
I/O(D)
CLK(8:5) CLK(3:0)
I
I
INREF(A:D)
I
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin I/O Function High Drive I/O Control Pins. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. There is an internal pull-down resistor to GND on this pin. This pin should be tied to GND if it is not used. If tied to 3.3 V, it will draw no more than 20 A per IOCTRL pin due to the pull-down resistor. Fabric JTAG Signals TDI/RSI I Test Data In for JTAG/RAM Init. Serial Data In. Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to 3.3V if unused. TRSTB/RRO I Active low Reset for JTAG/RAM Init. Reset Out. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Test Mode Select for JTAG. Hold HIGH during normal operation. TMS I Connect to 3.3V if not used for JTAG. Test Clock for JTAG. Hold HIGH or LOW during normal operation. TCK I Connect to 3.3V or GND if not used for JTAG. TDO/RCO Timer Interface Signals Timer Overflow. When timer #1 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #1's interval register. Conversely, this signal is asserted low when the counter is greater than the interval value. Timer Enable. This signal can be used to enable the timers internal to the QuickMIPS device. Internal timer setup registers determine how this signal is used by each timer block. Boot Memory Size. These signals indicate to the QuickMIPS device the width of the boot memory (the width of the memory device connected to CS_n(7)). CPU_BOOT(1:0) = 00: 8-bit width CPU_BOOT(1:0) = 01: 16-bit width CPU_BOOT(1:0) = 10: 32-bit width CPU_BOOT(1:0) = 11: Reserved Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates little-endian byte ordering. CPU Interrupts. Asserting low any of these inputs causes an interrupt to the QuickMIPS chip. These inputs are active low, level sensitive, and must be held low for at least two CPU pipeline clocks for the CPU to recognize the interrupt. CPU_EXTINT_n(6) is a Non Maskable Interrupt (NMI). Connect to 3.3 V if unused. O Test Data Out for JTAG/RAM Init. Clock Out. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization
IOCTRL(A:D)
I
TM_OVERFLOW
O
TM_ENABLE Miscellaneous Signals
I
CPU_BOOT(1:0)
I
CPU_BIGENDIAN
I
CPU_EXTINT_n(6:0)
I
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin STM I/O I Function QuickLogic Reserved Pin. Tie to GND on the PCB. Active Low CPU Reset. Asserting this signal low resets the entire ASSP portion of the QuickMIPS device (except for the PCI Controller, which has its own reset input). When low, CPU_RESET_n causes a cold reset exception to the MIPS CPU and halts all internal system clocks. This signal should be asserted for at least five CPU_PLL_CLKIN clock cycles. For reliable operation, the power supply must be stable and the clock must be running before this signal is deasserted. Active Low CPU Warm Reset. Asserting this signal low resets the entire ASSP portion of the QuickMIPS device (except for the PCI Controller, which has its own reset input). When low, CPU_WARMRESET_n causes a warm reset exception to the MIPS CPU, but all system clocks continue to operate. This signal should be asserted for at least five CPU_PLL_CLKIN clock cycles. For reliable operation, the power supply must be stable and the clock must be running before this signal is deasserted. Fabric PLL Input Clock Signal. This is the input reference clock to the Fabric PLL circuit. Connect to GND if the Fabric PLL is not used. FB_PLL_RESET_n I Fabric PLL Active Low Reset. If FB_PLL_RESET_n is low, then all PLL outputs are reset to zero. Connect to GND if the Fabric PLL is not used. FB_PLL_PADOUT ASSP PLL Signals CPU_PLL_CLKIN I Input Clock Signal. This clock input is the reference clock used by the CPU PLL. The frequency of the clock on this input is multiplied by eight to drive the MIPS CPU. Active Low PLL Enable Signal. This signal must be low to enable the ASSP-side PLL. If CPU_PLL_ENABLE_n is held high and CPU_PLL_BYPASS is held low, the QL903M is put into a power saving quiescent state. PLL Bypass. When high, the 8X multiplication of the input clock is not performed and the output clocks are equal to the input frequency. Output Clock Signal from the PLL. This output operates at the same frequency that is driven to the MIPS CPU. Leave unconnected if unused. CPU_PLL_LOCK CPU_PLL_DIV(1:0) O I PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid output clocks. Leave unconnected if unused. System Bus Clock to MIPS CPU Clock Ratio Control. See Table 2 for more details. O Fabric PLL Output Off Chip. This is the PLL output clock driven off chip. This output runs at the PLL VCO (FVCO) frequency determined by the M(1:0) input. Leave unconnected if unused.
CPU_RESET_n
I
CPU_WARMRESET_n
I
Fabric PLL Signals FB_PLL_CLKIN I
CPU_PLL_ENABLE_n
I
CPU_PLL_BYPASS
I
CPU_PLL_CLKOUT
O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 50: Pin Descriptions (Continued)
Pin GND I/O I Ground Pin. Tie to GND on the PCB. Voltage Supply Pin for Each of the Four I/O Banks. This pin provides the flexibility for the Fabric to interface with either a 1.8 V, 2.5 V, or 3.3 V device. Every I/O pin in the respective bank is tolerant of VCCIO(A:D) input signals and outputs VCCIO(A:D) level signals. This pin must be connected to either 1.8 V, 2.5 V, or 3.3 V. VCC V3V GND_FB_PLL V3V_FB_PLL GND_CPU_PLL V3V_CPU_PLL I I I I I I Supply Pin. Tie to 1.95 V supply. Supply Pin. Tie to 3.3 V supply. Fabric PLL Ground Pin. Tie to analog GND on the PCB. Fabric PLL 3.3 V Supply Pin. Tie to 3.3 V analog supply. CPU PLL Ground Pin. Tie to analog GND on the PCB. CPU PLL 3.3 V Supply Pin. Tie to 3.3 V analog supply. Function Power and Ground Signals
VCCIO(A:D)
I
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QL903M QuickMIPSTM Data Sheet Rev. H
ASSP Fabric Port Descriptions
Table 51: ASSP to Fabric Port Descriptions
Port Ethernet Controller Signals Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon detection of a collision on the medium. COL remains asserted while the collision condition persists. M1_COL, M2_COL I The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK. The QuickMIPS MAC core ignores the COL signal when operating in the fullduplex mode. Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of a collision condition. The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK. Ethernet Management Data Clock. MDC is sourced by the MAC core to the Ethernet PHY Controller as the timing reference for transfer of information on the MDI/MDO signals. MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and RXCLK. Ethernet Management Data In. This is the data input signal from the Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock during the read cycles. Ethernet Management Data Out. This is the data output signal from the MAC core that drives the control information during the Read/Write cycles to the External PHY Controller. The MAC core drives the MDO signal synchronously with respect to the MDC. Ethernet Management Data Output enable. This signal, when low, enables the Fabric IO driver to drive Mn_MDO off chip. Ethernet Receive Data. RXD(3:0) transition synchronously with respect to RXCLK. The Ethernet PHY Controller chip drives RXD(3:0). For each RXCLK period in which RXDV is asserted, RXD(3:0) transfer four bits of recovered data from the PHY to the MAC core. RXD0 is the least-significant bit. While RXDV is deasserted low, RXD(3:0) has no effect on the MAC core. Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the MAC core that it is presenting the recovered and decoded data bits on RXD(3:0) and that the data on RXD(3:0) is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXDV remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble, and is deasserted low prior to the first RXCLK that follows the final nibble. I/Oa Function
M1_CRS, M2_CRS
I
M1_MDC, M2_MDC
O
M1_MDI, M2_MDI
I
M1_MDO, M2_MDO M1_MDO_EN_N, M2_MDO_EN_N
O
O
M1_RXD(3:0), M2_RXD(3:0)
I
M1_RXDV, M2_RXDV
I
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK periods to indicate to the MAC core that an error (a coding error or any error that the PHY is capable of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame presently being transferred from the PHY to the MAC core. RXER transitions synchronously with respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC core. Ethernet Transmit Data. The QuickMIPS MAC core drives TXD(3:0). TXD(3:0) transition synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD(3:0) have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit. While TXEN is deasserted, ignore the data presented on TXD(3:0). Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC core is presenting nibbles on the MII for transmission. The QuickMIPS MAC core asserts TXEN with the first nibble of the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII. TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is transitions synchronously with respect to TXCLK. On-Chip SRAM Block 1 Address. This 10-bit address is the memory address for block 1 of the On-Chip SRAM. On-Chip SRAM Block 1 Clock. This clock drives block 1 of the On-Chip SRAM. When SRAM block 1 is connected to the Fabric, all SRAM block 1 IO signals are synchronous with this clock. On-Chip SRAM Block 1 Read Data. This 32-bit bus is the read data from OnChip SRAM block 1. On-Chip SRAM Block 1 Write Data. This 32-bit bus is the write data to On-Chip SRAM block 1. On-Chip SRAM Block 1 Write Enable. This is the active-low write enable to OnChip SRAM block 1. On-Chip SRAM Block 1 Byte Write Enable. These control signals act as active low byte write enables to On-Chip SRAM block 1. During a write operation, if a bit of SR1_WENb is low, the corresponding data byte on the SR1_WDATA bus is written to the SRAM: SR1_WENb(3) enables SR1_WDATA(31:24) SR1_WENb(2) enables SR1_WDATA(23:16) SR1_WENb(1) enables SR1_WDATA(15:8) SR1_WENb(0) enables SR1_WDATA(7:0) On-Chip SRAM Block 2 Address. This 10-bit address is the memory address for block 2 of the On-Chip SRAM. On-Chip SRAM Block 2 Clock. This clock drives block 2 of the On-Chip SRAM. When SRAM block 2 is connected to the Fabric, all SRAM block 2 IO signals are synchronous with this clock. On-Chip SRAM Block 2 Read Data. This 32-bit bus is the read data from OnChip SRAM block 2.
M1_RXER, M2_RXER
I
M1_TXD(3:0), M2_TXD(3:0)
O
M1_TXEN, M2_TXEN
O
On-Chip System SRAM Block 1 Signals SR1_ADDR(11:2) I
SR1_CLK
I
SR1_RDATA(31:0) SR1_WDATA(31:0) SR1_WEN
O I I
SR1_WENb(3:0)
I
On-Chip System SRAM Block 2 Signals SR2_ADDR(11:2) I
SR2_CLK
I
SR2_RDATA(31:0)
O
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port SR2_WDATA(31:0) SR2_WEN I/Oa I I Function On-Chip SRAM Block 2 Write Data. This 32-bit bus is the write data to On-Chip SRAM block 2. On-Chip SRAM Block 2 Write Enable. This is the active-low write enable to OnChip SRAM block 2. On-Chip SRAM Block 2 Byte Write Enable. These control signals act as active low byte write enables to On-Chip SRAM block 2. During a write operation, if a bit of SR2_WENb is low, the corresponding data byte on the SR2_WDATA bus is written to the SRAM: SR2_WENb(3) enables SR2_WDATA(31:24) SR2_WENb(2) enables SR2_WDATA(23:16) SR2_WENb(1) enables SR2_WDATA(15:8) SR2_WENb(0) enables SR2_WDATA(7:0) On-Chip SRAM Block 3 Address. This 10-bit address is the memory address for block 3 of the On-Chip SRAM. On-Chip SRAM Block 3 Clock. This clock drives block 3 of the On-Chip SRAM. When SRAM block 3 is connected to the Fabric, all SRAM block 3 IO signals are synchronous with this clock. On-Chip SRAM Block 3 Read Data. This 32-bit bus is the read data from OnChip SRAM block 3. On-Chip SRAM Block 3 Write Data. This 32-bit bus is the write data to On-Chip SRAM block 3. On-Chip SRAM Block 3 Write Enable. This is the active-low write enable to OnChip SRAM block 3. On-Chip SRAM Block 3 Byte Write Enable. These control signals act as active low byte write enables to On-Chip SRAM block 3. During a write operation, if a bit of SR3_WENb is low, the corresponding data byte on the SR3_WDATA bus is written to the SRAM: SR3_WENb(3) enables SR3_WDATA(31:24) SR3_WENb(2) enables SR3_WDATA(23:16) SR3_WENb(1) enables SR3_WDATA(15:8) SR3_WENb(0) enables SR3_WDATA(7:0) On-Chip SRAM Block 4 Address. This 10-bit address is the memory address for block 4 of the On-Chip SRAM. On-Chip SRAM Block 4 Clock. This clock drives block 4 of the On-Chip SRAM. When SRAM block 4 is connected to the Fabric, all SRAM block 4 IO signals are synchronous with this clock. On-Chip SRAM Block 4 Read Data. This 32-bit bus is the read data from OnChip SRAM block 4. On-Chip SRAM Block 4 Write Data. This 32-bit bus is the write data to On-Chip SRAM block 4. On-Chip SRAM Block 4 Write Enable. This is the active-low write enable to OnChip SRAM block 4.
SR2_WENb(3:0)
I
On-Chip System SRAM Block 3 Signals SR3_ADDR(11:2) I
SR3_CLK
I
SR3_RDATA(31:0) SR3_WDATA(31:0) SR3_WEN
O I I
SR3_WENb(3:0)
I
On-Chip System SRAM Block 4 Signals SR4_ADDR(11:2) I
SR4_CLK
I
SR4_RDATA(31:0) SR4_WDATA(31:0) SR4_WEN
O I I
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function On-Chip SRAM Block 4 Byte Write Enable. These control signals act as active low byte write enables to On-Chip SRAM block 4. During a write operation, if a bit of SR4_WENb is low, the corresponding data byte on the SR4_WDATA bus is written to the SRAM: SR4_WENb(3) enables SR4_WDATA(31:24) SR4_WENb(2) enables SR4_WDATA(23:16) SR4_WENb(1) enables SR4_WDATA(15:8) SR4_WENb(0) enables SR4_WDATA(7:0) AMBA Bus Clock. All AMBA bus transactions are synchronous with this clock. Upon entering the Fabric, hclk is automatically placed on a global clock net. hclk can be programmed to be 1/2, 1/3 or 1/4 the CPU clock rate. SeeTable 2 for more details. AMBA Bus Reset. When low, this signal indicates to the programmable Fabric that the ASSP side of the device is in the reset state. This signal should be used to reset the Fabric AHB Master, AHB Slave or APB Slave interfaces. AHB Ready Input. This signal is used by an AHB master and /or an AHB slave implemented in the Fabric. For an AHB master implemented in the Fabric: When high, this signal indicates to the AHB master that the accessed AHB slave is ready to continue the current transfer. For an AHB slave implemented in the Fabric: An AHB slave must only sample the address and control signals and ahbs_hsel when ahb_hready_in is high, indicating that the current transfer is completing. Under certain circumstances it is possible that ahbs_hsel will be asserted when ahb_hready_in is low, but the selected slave will have changed by the time the current transfer completes. AHB Master Interface Signals ahbm_haddr(31:0) I AHB Master Address. This bus contains the AHB address for the transfer initiated by the Fabric AHB master. AHB Master Burst Type. These signals indicate the length of the Fabric AHB master burst transfer. Possible burst sizes are: 000: SINGLE 001: INCR (length unspecified) 010: WRAP4 011: INCR4 100: WRAP8 101: INCR8 110: WRAP16 111: INCR16 AHB Master Bus Request. When high, this signal indicates to the AHB arbiter that the AHB master implemented in the Fabric is requesting ownership of the AHB. AHB Master Grant. When high, this signal indicates that the AHB master implemented in the Fabric is the current AHB master.
SR4_WENb(3:0)
I
AHB and APB Clock and Reset Signals
hclk
O
hresetn
O
AHB Master and AHB Slave Interface Signals
ahb_hready_in
O
ahbm_hburst(2:0)
I
ahbm_hbusreq
I
ahbm_hgrant
O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port ahbm_hprot(3:0) I/Oa I Function AHB Master Protection. Protected transfers are not supported by the QuickMIPS device. The AHB master implemented in the Fabric should tie all bits of this bus low. AHB Master Read Data. The AHB master implemented in the Fabric receives data for AHB reads on this bus. Data is received from the selected AHB slave. AHB Master Transfer Response. The AHB master implemented in the Fabric receives these signals from the accessed AHB slave. For a given transfer, the slave may respond with: 00: OKAY 01: ERROR 10: RETRY 11: SPLIT (not supported in QuickMIPS) AHB Master Transfer Size. The AHB master implemented in the Fabric drives these signals to indicate to the selected slave the size of the transfer taking place. Possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits 111: 1024 bits AHB Master Transfer Type. The AHB master implemented in the Fabric drives these signals to indicate to the selected slave the type of transfer taking place. Possible transfer types are: 00: IDLE 01: BUSY 10: NONSEQUENTIAL 11: SEQUENTIAL AHB Master Write Data. The AHB master implemented in the Fabric drives data for AHB writes on this bus. Data is received by the selected AHB slave. AHB Master Write. The AHB master implemented in the Fabric drives this signal high during an AHB write operation and low during an AHB read. AHB Slave Address. This bus contains the AHB address for the transfer intended for the AHB Fabric slave. AHB Slave Burst Type. These signals indicate the length of the transfer intended for the AHB Fabric slave. Possible burst sizes are: 000: SINGLE 001: INCR (length unspecified) 010: WRAP4 011: INCR4 100: WRAP8 101: INCR8 110: WRAP16 111: INCR16 AHB Slave Protection. Protected transfers are not supported by the QuickMIPS device. The AHB slave implemented in the Fabric ignores these signals.
(c) 2004 QuickLogic Corporation
ahbm_hrdata(31:0)
O
ahbm_hresp(1:0)
O
ahbm_hsize(2:0)
I
ahbm_htrans(1:0)
I
ahbm_hwdata(31:0) ahbm_hwrite AHB Slave Interface Signals ahbs_haddr(31:0)
I I
O
ahbs_hburst(2:0)
O
ahbs_hprot(3:0) * * * *
O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port ahbs_hrdata;(31:0) I/Oa I Function AHB Slave Read Data. The AHB slave implemented in the Fabric drives data for AHB reads on this bus. Data is received by the initiating AHB master. AHB Slave Ready Output. When high, this signal indicates to the initiating AHB master that the AHB slave implemented in the Fabric is ready to continue the current transfer. AHB Slave Transfer Response. The initiating AHB master receives these signals from the AHB slave implemented in the Fabric. For a given transfer, the slave responds with: 00: OKAY 01: ERROR 10: RETRY 11: SPLIT (not supported in QuickMIPS) AHB Slave Select. When high, this signal indicates to the AHB slave implemented in the Fabric that it is the selected slave for the current AHB transfer. AHB Slave Transfer Size. These signals indicate the size of the transfer intended for the AHB Fabric slave. Possible transfer sizes are: 000: 8 bits (byte) 001: 16 bits (halfword) 010: 32 bits (word) 011: 64 bits 100: 128 bits (4-word line) 101: 256 bits (8-word line) 110: 512 bits AHB Slave Transfer Type. These signals indicate the type of transfer intended for the AHB Fabric slave. Possible transfer types are: 00: IDLE 01: BUSY 10: NONSEQUENTIAL 11: SEQUENTIAL AHB Slave Write Data. The initiating AHB master drives data for AHB writes on this bus. Data is intended for the AHB slave in the Fabric. AHB Slave Write. During an AHB transfer, this signal is driven high during a write operation and low during a read. It is received by the AHB slave implemented in the Fabric. APB Slave Address. This bus contains the APB address for the transfer intended for an APB Fabric slave. APB Slave Enable. This signal, when high, indicates the second phase (data phase) of an APB transfer intended for an APB Fabric slave. APB Slave 0 Read Data. The APB slave 0 implemented in the Fabric drives data for APB reads on this bus. APB Slave 1 Read Data. The APB slave 1 implemented in the Fabric drives data for APB reads on this bus. APB Slave 2 Read Data. The APB slave 2 implemented in the Fabric drives data for APB reads on this bus. APB Slave 0 Select. This signal, when high, indicates that the current transfer is intended for APB slave 0 implemented in the Fabric. * * * *
ahbs_hready_out
I
ahbs_hresp(1:0)
I
ahbs_hsel
O
ahbs_hsize(2:0)
O
ahbs_htrans(1:0)
O
ahbs_hwdata(31:0)
O
ahbs_hwrite APB Slave Interface Signals apbs_paddr(15:2) apbs_penable apbs_prdata0(31:0) apbs_prdata1(31:0) apbs_prdata2(31:0) apbs_psel0
O
O O I I I O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port apbs_psel1 apbs_psel2 apbs_pwdata(31:0) I/Oa O O O Function APB Slave 1 Select. This signal, when high, indicates that the current transfer is intended for APB slave 1 implemented in the Fabric. APB Slave 2 Select. This signal, when high, indicates that the current transfer is intended for APB slave 2 implemented in the Fabric. APB Slave Write Data. All APB slaves implemented in the Fabric receive data for APB write transactions from this bus. APB Slave Write. During an APB transfer, this signal is driven high during a write operation and low during a read. It is received by all APB slaves implemented in the Fabric. Timer 1 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #1. Timer 2 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #2. Timer 3 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #3. Timer 4 External Clock. This port allows a clock generated in the Fabric to drive Timer/Counter #4. Timer Enable from Fabric. This signal, when high, indicates to the timer enable logic that the Fabric design has enabled the timer(s). Internal timer setup registers determine how this signal is used by each timer block. Timer 2 Overflow. When timer #2 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #2 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Timer 3 Overflow. When timer #3 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #3 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Timer 4 Overflow. When timer #4 is in PWM mode, it counts up to 0xFFFF and then back down to zero. This PWM output signal is asserted high when the value of the counter is less than or equal to the value programmed in timer #4 interval register. Conversely, this signal is asserted Low when the counter is greater than the interval value. Big Endian Indicator to Fabric. This signal, when high, indicates to the Fabric that the QuickMIPS device is in big endian mode. Interrupt from Fabric. This signal, when driven high by a design in the Fabric, causes an interrupt to the MIPS processor. This input is active high and level sensitive. Performance Monitor Data Cache Hit. This signal is asserted whenever there is a data cache hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Data Cache Miss. This signal is asserted whenever there is a data-cache miss. This signal is synchronous with CPU_PLL_CLKOUT.
apbs_pwrite Timer/Counter Signals tm_extclk1 tm_extclk2 tm_extclk3 tm_extclk4
O
I I I I
tm_fbenable
I
tm_overflow2
O
tm_overflow3
O
tm_overflow4
O
MIPS CPU Signals fb_bigendian O
fb_int
I
pm_dcachehit pm_dcachemiss * * * *
O O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port pm_dtlbhit pm_dtlbmiss I/Oa O O Function Performance Monitor Data TLB Hit. This signal is asserted whenever there is a hit in the data TLB. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor data TLB Miss. This signal is asserted whenever there is a miss in the data TLB. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction Cache Hit. This signal is asserted whenever there is an instruction-cache hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction Cache Miss. This signal is asserted whenever there is an instruction-cache miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction Complete. This signal is asserted each time an instruction completes in the pipeline. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction TLB Hit. This signal is asserted whenever there is an instruction TLB hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Instruction TLB Miss. This signal is asserted whenever there is an instruction TLB miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Joint TLB Hit. This signal is asserted whenever there is a joint TLB hit. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Joint TLB Miss. This signal is asserted whenever there is a joint TLB miss. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Write-Through Merge. This signal is asserted whenever there is a successful merge in the write-through buffer. This signal is synchronous with CPU_PLL_CLKOUT. Performance Monitor Write-Through Non-Merge. This signal is asserted whenever a non-merging store is written to the write-through buffer. This signal is synchronous with CPU_PLL_CLKOUT. Reduce Power Indicator to Fabric. This signal represents the state of the RP bit (27) in the MIPS CP0 Status register. Software can write this bit to indicate that the device can enter a reduced power mode. This signal is synchronous with CPU_PLL_CLKOUT. Sleep Indicator to Fabric. This signal is asserted by the MIPS core whenever the WAIT instruction is executed. The assertion of this signal indicates that the clock has stopped and that the core is waiting for an interrupt. This signal is synchronous with CPU_PLL_CLKOUT. PLL Lock Indicator. This signal, when high, indicates to the Fabric that the ASSP PLL has achieved phase lock on the incoming reference clock signal.
pm_icachehit
O
pm_icachemiss
O
pm_instncomplete
O
pm_itlbhit
O
pm_itlbmiss
O
pm_jtlbhit pm_jtlbmiss
O O
pm_wtbmerge
O
pm_wtbnomerge
O
si_rp
O
si_sleep
O
CPU PLL Status io_mips_pll_lock O
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port PCI Configuration Settings PCI Configuration Done. This signal represents the initial value (after reset) of the Config Done bit in the PCI DMA registers. After reset, the value of this register may be overwritten through the AHB. The purpose for this register is to disable the PCI interface until the MIPS processor is ready. This may be useful when the readonly ID registers in the PCI configuration space will be over-written by the MIPS processor, which will require some time. While this register is 0, retries will be signaled on the PCI bus, thus signaling that the QuickMIPS device is not ready, and the PCI transaction should be tried again at a later time. Note that the PCI Specification limits the length of time that a device can retry a transaction, and states the amount of time after the PCI reset is deasserted when a PCI configuration cycle may occur. In an embedded system, however, a designer may choose to violate certain PCI specifications if he/she knows it will not have a detrimental impact on the system. This signal is tie-low or tie-high in the Fabric only. PCI Class Code. These signals represent the initial value (after reset) of the Class Code bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. The Class Code register is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. These signals are tie-low or tie-high in the Fabric only. PCI Device ID. These signals represent the initial value (after reset) of the Device ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This field identifies the particular PCI device. This identifier is allocated by the vendor. These signals are tie-low or tie-high in the Fabric only. PCI Host. This signal represents the initial value (after reset) of the Host Mode bit in the PCI DMA registers. After reset, the value of this register may be overwritten through the AHB. This register controls whether the QuickMIPS device acts as the PCI system host or is a satellite device. A system host must configure itself as well as all the devices on the PCI bus, whereas a satellite device will be configured by another device (the host) of the PCI system. Note that while in host mode, the PCI configuration registers may only be accessed by the AHB, but while in satellite (non-host) mode, the PCI configuration registers may only be accessed by the PCI bus. This signal is tie-low or tie-high in the Fabric only. PCI Maximum Latency. These signals represent the initial value (after reset) of the Max Latency bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register is used for specifying how often the device needs to gain access to PCI bus. These signals are tie-low or tie-high in the Fabric only. PCI Minimum Grant. These signals represent the initial value (after reset) of the Min Grant bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz.These signals are tie-low or tie-high in the Fabric only. PCI Revision ID. These signals represent the initial value (after reset) of the Revision ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This register specifies a device specific revision identifier. The value is chosen by the vendor (zero is an acceptable value). This field should be viewed as a vendor defined extension to the Device ID. These signals are tie-low or tie-high in the Fabric only. I/Oa Function
AF_PCI_CFGDONE
I
AF_PCI_CLASSCODE(23:0)
I
AF_PCI_DEVID(15:0)
I
AF_PCI_HOST
I
AF_PCI_MAXLAT(7:0)
I
AF_PCI_MINGNT(7:0)
I
AF_PCI_REVID(7:0)
I
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 51: ASSP to Fabric Port Descriptions (Continued)
Port I/Oa Function PCI Subsystem ID. These signals represent the initial value (after reset) of the Subsystem ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. These registers are used to uniquely identify the expansion board or subsystem where the PCI device resides. They provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may have the same PCI controller on them. These signals are tie-low or tie-high in the Fabric only. PCI Subsystem Vendor ID. These signals represent the initial value (after reset) of the Subsystem Vendor ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. These registers are used to uniquely identify the expansion board or subsystem where the PCI device resides. They provide a mechanism for expansion board vendors to distinguish their boards from one another even though the boards may have the same PCI controller on them. These signals are tie-low or tie-high in the Fabric only. PCI Vendor ID. These signals represent the initial value (after reset) of the Vendor ID bits in the PCI Configuration Registers. After reset, the value of this register may be overwritten through the AHB. This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. These signals are tie-low or tie-high in the Fabric only.
AF_PCI_SUBSYSID(15:0)
I
AF_PCI_SUBSYSVID(15:0)
I
AF_PCI_VENID(15:0)
I
a. Interface direction is specified with respect to the ASSP portion of the device. I designates an input to the ASSP and O designates an output from the ASSP.
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QL903M QuickMIPSTM Data Sheet Rev. H
544 BGA Pinout Table
Table 52: 544 BGA Pinout Table
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 Function
GND NC NC I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) VCCIO(C) I/O(C) I/O(C) VCCIO(C) CLK(8) CLK(5) I/O(B) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) NC I/O(A) VCCIO(B) IOCTRL(A) GND I/O(D) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) GND I/O(C) I/O(C) I/O(C) I/O(C) TMS GND CLK(6) I/O(B) I/O(B) VCCIO(B) GND I/O(B) I/O(B) VCCIO(B) NC I/O(A) INREF(A) IOCTRL(A) I/O(A)
Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
Function
I/O(D) VCCIO(D) NC I/O(D) VCCIO(C) I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(B) CLK(7) I/O(B) I/O(B) INREF(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) GND I/O(A) I/O(A) I/O(A) I/O(A) I/O(D) I/O(D) GND IOCTRL(D) I/O(D) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) IO(C) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) NC GND VCCIO(A) I/O(A)
Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
Function
I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(A) I/O(A) NC I/O(D) I/O(D) I/O(D) INREF(D) NC) I/O(C) VCC VCC VCCIO(C) VCCIO(C) VCCIO(C) GND VCC VCC GND VCCIO(B) VCCIO(B) VCCIO(B) VCC GND VCC I/O(B) NC I/O(A) NC NC
Ball G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K10 K11 K12 K13 K14 K15 K16 K17 K21 K22
Function
NC I/O(D) I/O(D) I/O(C) I/O(C) GND VCC I/O(B) I/O(B) I/O(B) NC NC NC NC V3V GND I/O(C) VCC GND V3V I/O(B) VCCIO(A) NC DEDCLK/CLK(4) NC GND VCCIO(D) I/O(C) I/O(C) VCCIO(D) VCCIO(A) NC I/O(B) I/O(B) CLK(3) CLK(2) NC NC I/O(D) I/O(D) NC VCCIO(D) GND GND GND GND GND GND GND GND VCCIO(A) I/O(A)
Ball K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L10 L11 L12 L13 L14 L15 L16 L17 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M10 M11 M12 M13 M14 M15 M16 M17 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N10 N11
Function
I/O(A) I/O(A) GND GND TCK CLK(0) I/O(D) I/O(D) I/O(D) VCCIO(D) GND GND GND GND GND GND GND GND VCCIO(A) I/O(A) I/O(A) I/O(A) V3V GND GND TDI NC NC NC VCCIO(D) GND GND GND GND GND GND GND GND GND I/O(A) I/O(A) I/O(A) TRSTB NC STM TDO V3V CLK(1) V3V GND GND GND
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Table 52: 544 BGA Pinout Table (Continued)
Ball N12 N13 N14 N15 N16 N17 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P10 P11 P12 P13 P14 P15 P16 P17 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R10 R11 R12 R13 R14 R15 R16 R17 R21 R22 R23 R24 R25 R26 Function
GND GND GND GND GND GND VCC NC NC NC M2_TXCLK M2_RXCLK CPU_PLL_BYPASS CPU_PLL_ENABLE_n VCCIO(D) CPU_RESET_n V3V_CPU_PLL VCC GND GND GND GND GND GND GND GND VCC V3V_FB_PLL V3V VCCIO(A) NC EJTAG_DINT CPU_PLL_DIV(0) CPU_PLL_LOCK CPU_PLL_CLKOUT NC CPU_WARMRESET_n VCC GND GND GND GND GND GND GND GND FB_PLL_CLKIN FB_PLL_PADOUT FB_PLL_RESET_n CS_n(0) CS_n(2) CS_n(3)
Ball T1 T2 T3 T4 T5 T6 T10 T11 T12 T13 T14 T15 T16 T17 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U10 U11 U12 U13 U14 U15 U16 U17 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 V22 V23 V24 V25 V26
Function
M1_TXCLK M1_RXCLK CPU_PLL_DIV(1) TM_ENABLE NC CPU_PLL_CLKIN GND GND GND GND GND GND GND GND GND_FB_PLL CS_n(1) EJTAG_DEBUGM CS_n(4) GND CS_n(5) CPU_BOOT(1) GND CPU_BOOT(0) PCI_INTA_n PCI_REQ_n GND_CPU_PLL GND GND GND GND GND GND GND GND V3V OE_n BLS_n(3) WE_n CS_n(6) CS_n(7) GND GND PCI_AD(27) PCI_AD(31) PCI_AD(20) GND V3V ADDR(8) ADDR(5) ADDR(1) BLS_n(0) BLS_n(1)
Ball W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2
Function
PCI_RST_n TM_OVERFLOW V3V PCI_AD(23) PCI_AD(17) V3V V3V SD_CLKIN ADDR(9) V3V BLS_n(2) ADDR(0) PCI_AD(30) PCI_IDSEL PCI_GNT_n PCI_AD(29) PCI_AD(16) VCC GND ADDR(13) ADDR(2) ADDR(3) ADDR(4) ADDR(6) PCI_AD(25) PCI_AD(26) PCI_AD(28) PCI_AD(19) PCI_CLK GND GND V3V V3V V3V GND GND VCC V3V V3V GND VCC V3V V3V GND VCC ADDR(12) ADDR(7) GND ADDR(10) ADDR(11) PCI_C_BE_n(1) PCI_AD(21)
Ball AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2
Function
PCI_AD(22) PCI_AD(24) PCI_AD(18) PCI_C_BE_n(3) PCI_STOP_n PCI_TRDY_n PCI_SERR_n PCI_AD(0) EJTAG_TMS U1_DSR_n U1_CTS_n SD_CS_n(0) DATA(26) DATA(15) DATA(4) ADDR(17) ADDR(19) ADDR(20) ADDR(22) DATA(0) DATA(1) DATA(2) DATA(3) DATA(5) PCI_AD(14) V3V GND PCI_C_BE_n(0) V3V PCI_PAR PCI_IRDY_n PCI_FRAME_n V3V PCI_AD(8) CPU_EXTINT_n(5) U2_TXD_SIROUT U2_RXD_SIRIN SD_RAS_n DATA(30) DATA(19) DATA(8) ADDR(21) ADDR(16) ADDR(15) DATA(6) DATA(7) DATA(9) DATA(10) V3V DATA(11) PCI_AD(10) PCI_AD(11)
Ball AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2
Function
PCI_AD(12) PCI_AD(13) PCI_AD(5) PCI_PERR_n PCI_C_BE_n(2) PCI_DEVSEL_n PCI_AD(15) PCI_AD(4) PCI_AD(1) EJTAG_TDO EJTAG_TDI U1_RXD_SIRIN SD_DQM(3) DATA(24) DATA(14) ADDR(18) ADDR(23) ADDR(14) DATA(25) DATA(23) DATA(16) DATA(13) GND DATA(12) PCI_AD(9) PCI_AD(7) PCI_AD(3) GND CPU_EXTINT_n(6) CPU_EXTINT_n(3) GND EJTAG_TCK V3V U1_RTS_n GND U1_DCD_n V3V SD_CKE(1) SD_WE_n NC V3V GND SD_CLKOUT V3V DATA(31) DATA(29) V3V DATA(20) DATA(18) DATA(17) GND PCI_AD(6)
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
Table 52: 544 BGA Pinout Table (Continued)
Ball AF3 AF4 AF5 AF6 AF7 Function
PCI_AD(2) EJTAG_TRST_n CPU_EXTINT_n(4) CPU_EXTINT_n(2) CPU_EXTINT_n(1)
Ball AF8 AF9 AF10 AF11 AF12
Function
CPU_EXTINT_n(0) CPU_BIGENDIAN U1_DTR_n U1_RI_n U1_TXD_SIROUT
Ball AF13 AF14 AF15 AF16 AF17
Function
NC NC SD_CKE(0) SD_CAS_n NC
Ball AF18 AF19 AF20 AF21 AF22
Function
SD_CS_n(1) SD_DQM(2) SD_DQM(1) SD_DQM(0) DATA(28)
Ball AF23 AF24 AF25 AF26
Function
DATA(27) DATA(22) DATA(21) GND
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
544 BGA Pinout Drawing
Figure 57: 544 BGA Pinout Diagram
(c) 2004 QuickLogic Corporation
Preliminary
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QL903M QuickMIPSTM Data Sheet Rev. H
Ordering Information
QL QuickLogic Device Part Number: 903M 903M 175 -1 PS544 C Operating Range: C = Commercial I = Industrial
Processor Speed: 175 MHz 200 MHz Fabric Speed: -1 Fast Package Lead Count: -2 Faster PS544 = 544-ball BGA (1.0 mm)
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 6867 0273 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
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(c) 2004 QuickLogic Corporation
QL903M QuickMIPSTM Data Sheet Rev. H
Revision History
Revision A B Date May 2003 June 2003 Comments Judd Heape and Kathleen Murchek Judd Heape and Kathleen Murchek Modifications to all sections including pinout tables and AC timing parameters. Added section related to operation of on-chip SRAM. Judd Heape and Kathleen Murchek Modifications to all sections including pinout tables and AC timing parameters. Added Interrupt Controller section. Judd Heape and Kathleen Murchek General clean-up of document text and figures. Added ECU and Dual-Port RAM signals. Added text to ASSP I/O DC Characteristics and ASSP to Fabric Interface Output Timing tables. Added new section - Board Layout Recommendations. Replaced Advanced Clocks Network section. Judd Heape and Kathleen Murchek New PLL power supply filtering illustration and general clean-up of document text. Modified Multiple I/O Banks figure. Judd Heape and Kathleen Murchek Changed Tjmax number from 150C to 125C in Package Thermal Characteristics section. Added ICC(STATIC) row to DC Characteristics table. Added an AHB Master and AHB Slave Interface Signals section with an ahb_hready_in row to ASSP to Fabric Port Descriptions table. Changed VCC supply specification to 1.95 0.05 V. Judd Heape and Kathleen Murchek Removed Fabric RAM modes 512x4 and 1024x2. Updated AC and DC Characteristics including all Fabric timing and ASSP to Fabric interface timing. Added Fabric PLL timing data and modified clock network figures. Added System SRAM timing data and added timing diagrams. Modified Power-Up Sequencing section. Modified security and flexibility fuse descriptions in JTAG section. Modified EJTAG pin descriptions. Added Fabric I/O voltage and current graphs to DC Characteristics section. Judd Heape and Kathleen Murchek Removed IFAB_PLL and ICPU_PLL sections from DC Characteristics table. Changed all instances of VCC_FB_PLL and VCC_CPU_PLL to VCC. Removed VCC_FB_PLL and VCC_CPU_PLL from pin description table and PLL Power Supply Filtering Circuits figure. Removed instances of analog VCC, FB_PLL_VCC and CPU_PLL_VCC from PLL Power Supply Filtering section. Updated text and tables in Fabric PLL Signals section
C
June 2003
D
July 2003
E
July 2003
F
December 2003
G
March 2004
H
September 2004
(c) 2004 QuickLogic Corporation
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QL903M QuickMIPSTM Data Sheet Rev. H
Copyright and Trademark Information
Copyright (c) 2004 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
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(c) 2004 QuickLogic Corporation

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