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| Released PM7800 PALADIN 10 Digital Correction Signal Processor OVERVIEW The PALADIN family of digital multicarrier chip technologies enables the development of spectrally efficient and power efficient 2G and 3G base stations that use fewer and less expensive components than traditional feedforward designs. PALADIN products include PALADIN 10, PALADIN 15, and PALADIN Waveshaper. All PALADIN products make extensive use of proprietary advanced high-speed DSP based architectures and techniques. efficiency, digitally controlled amplifier units that can replace expensive, lowefficiency, feedforward-based multicarrier power amplifiers (MCPA) commonly used in many BTS designs. The PALADIN 10 system comprises the Digital Correction Signal Processor (DCSP) PM7800 chip and the Adaptive Control Processor Compensation Engine (ACPCE). The DCSP applies corrective parameters to each sample in real time, while the ACPCE automatically adapts the corrective parameters to maintain optimum performance as the distortions change over time. Key features of PALADIN 10 include: * Input signal bandwidth up to 10MHz. * Output sample rate up to 80MHz. * Variable input sample rate. * 32-bit complex baseband reference signal input. * 32-bit complex baseband or 16-bit IF output. * 16- or 32-bit observation signal input. * Digital correction of Analog Quadrature Modulation distortion for practical zeroIF upconversion. * Automatic adjustment of corrective parameters in response to changing RMS signal levels. * State-of-the-art firmware * Firmware upgradeable to accommodate new features PACKAGING * Industrial temperature range (-40 C to +85 C). * 304-pin SBGA with a body size of 31mm x 31mm. FEATURES PALADIN 10 inhibits distortion in the power amplifier and transmitter chain of cellular base stations using digital adaptive predistortion techniques. The PALADIN 10 solution transforms inexpensive Class AB power amplifiers into wideband, multi-carrier, high- APPLICATIONS * Multi-carrier WCDMA, cdmaOne, CDMA2000 1xRTT, and CDMA2000 EV-DO base station transmitters. BLOCK DIAGRAM PALADIN 10 Padring JTAG DCLK REFCLK CPUCLK PALADIN 10 Core RESET_N VREF SCS_N SD SCLK HOP_N Input Module Predistortion and AQM Correction Engines Modulation Circuitry VD VOBS Capture Module CPU Interface GPIO Control ADR DAT PMC-2001613 (r4) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE (c) Copyright PMC-Sierra, Inc. 2004 Released PM7800 PALADIN 10 Digital Correction Signal Processor TYPICAL APPLICATIONS PALADIN 10 MCPA-EQUIPPED WCDMA BTS PMC-Sierra Solution Baseband (I,Q) 1 Baseband (I,Q) 2 Baseband Cards (Modems) PALADIN Waveshaper PM7819 SPI Digital Multi-carrier Baseband I/Q PALADIN 10 PM7800 DAC RF Upconverter HPA To Antenna ADC RF Downconverter PALADIN ACPCE DSP Local Host BTS Control Processor SPI 2-Carrier WCDMA PALADIN 10 MCPA-EQUIPPED CDMA2000 BTS PMC-Sierra Solution Baseband (I,Q) 1 Baseband (I,Q) 2 Baseband Cards (Modems) Baseband (I,Q) 3 Baseband (I,Q) 4 PALADIN Waveshaper PM7819 Cascade Input Digital Multi-carrier Baseband I/Q PALADIN 10 PM7800 DAC RF Upconverter HPA To Antenna ADC RF Downconverter SPI Baseband (I,Q) 5 Baseband (I,Q) 6 Baseband Cards (Modems) Baseband (I,Q) 7 Baseband (I,Q) 8 PALADIN Waveshaper PM7819 SPI PALADIN ACPCE DSP SPI 8-Carrier CDMA2000 Local Host BTS Control Processor Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: +1.604.415.6000 Fax: +1.604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-2001613 (r4) (c) Copyright PMC-Sierra, Inc. 2004. All rights reserved. For a complete list of PMC-Sierra's trademarks and registered trademarks, please visit: http://www.pmc-sierra.com/legal/ PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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