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HV9931
Initial Release
HV9931 Unity Power Factor LED Lamp Driver
Features
Constant Output Current Large Step-Down Ratio Unity Power Factor Low Input Current Harmonic Distortion Fixed Frequency or Fixed Off-Time Operation Internal 450V Linear Regulator Input and output current sensing Input Current limit Enable, PWM and Phase Dimming
General Description
The HV9931 is a fixed frequency PWM controller IC designed to control an LED lamp driver using a single-stage PFC buckboost-buck topology. It can achieve a unity power factor and a very high step-down ratio that enables driving a single high-brightness LED from the 85-264VAC input without a need for a power transformer. This topology allows reducing the filter capacitors and using non-electrolytic capacitors to improve reliability. The HV9931 uses open-loop peak current control to regulate both the input and the output current. This control technique eliminates a need for loop compensation, limits the input inrush current, and is inherently protected from input under-voltage condition. Capacitive isolation protects the LED Lamp from failure of the switching MOSFET. HV9931 provides a low-frequency PWM dimming input that can accept an external control signal with a duty ratio of 0100% and a frequency of up to a few kilohertz. The PWM dimming capability enables HV9931 phase control solutions that can work with standard wall dimmers.
Applications
Offline LED Lamps and Fixtures Street lamps Traffic Signals Decorative Lighting
Typical Application Circuit
D1
VIN
D4
L1
C1
D2
L2
CIN ~AC ~AC RS1 Q1 D3 RS2 VO
+
Rref1
RCS1
RCS2
HV9931
RT VIN GATE CS1 GND RT PWMD CS2 VDD C2
Rref2
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Ordering Information
Package Options DEVICE 8-Lead SOIC HV9931 HV9931LG-G 8-Lead DIP HV9931P-G
HV9931
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
VIN to GND VDD to GND CS1, CS2 to GND PWMD to GND GATE to GND -0.5V to +470V -0.3V to +13.5V -0.3V to VDD + 0.3V -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) 900mW 630mW -40C to +85C +125C -65C to +150C
Continuous Power Dissipation (TA = +25C) - Also limited by package power dissipation limit, whichever is lower. 8-Pin DIP (derate 9mW/C above +25C) 8-Pin and 14-Pin SO (derate 6.3mW/C above +25C) Operating Temperature Range Junction Temperature Storage Temperature Range
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(The * denotes the specifications which apply over the full operating junction temperature range of -40C < TA < +85C, otherwise the specifications are at TA = 25C, VIN = 100V, unless otherwise noted)
Symbol
Input VINDC IINSD
Parameter
Input DC supply voltage range* Shut-Down mode supply current*
Min
8
Typ
Max
450
Units
V mA
Conditions
DC input voltage PWMD connected to GND, VIN = 12V
0.5
1
Internal Regulator VDD UVLO UVLO Internally regulated voltage* VDD undervoltage lockout threshold VDD undervoltage lockout hysteresis 7.12 6.45 7.5 6.7 500 7.88 6.95 V V mV VIN = 8-450V, IDD(ext) = 0, GATE open VIN rising
PWM Dimming VPWMD(lo) VPWMD(hi) RPWMD GATE VGATE(hi) VGATE(lo) TRISE TFALL TDELAY TBLANK GATE high output voltage* GATE low output voltage* GATE output rise time GATE output fall time Delay from CS trip to GATE Blanking delay 150 VDD-0.3 0 30 30 150 215 VDD 0.3 50 50 300 280 V V ns ns ns ns IGATE = 10mA IGATE = -10mA CGATE = 500pF CGATE = 500pF VIN = 12V, VCSI, VCS2 = -50mV VCSI, VCS2 = -0.15V PWMD input low voltage* PWMD input high voltage* PWMD pull-down resistance 2.4 50 100 150 1.0 V V k VIN = 8-450V VIN = 8-450V VPWMD = 5V
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HV9931
Symbol
Oscillator FOSC FT Initial Accuracy Temperature Stability 80 100 3 120 kHz % RT = 230K Tj = -40C to +125C
Parameter
Min
Typ
Max
Units
Conditions
Comparators VOFFSET1 VOFFSET2 VOFFSET1 VOFFSET2 Comparator Input offset voltage* -12 12 mV
Input offset voltage temperature drift
10
V/C
Tj = -40C to +125C
Pin Description
VIN - This pin is the input of a high voltage regulator. VDD - This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND. GATE - This pin is the output gate driver for an external N-channel power MOSFET. GND - Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. RT - Oscillator control. A resistor connected between this pin and GND sets the PWM frequency. A resistor connected between this pin and GATE sets the PWM off-time. PWMD - When this pin is pulled to GND, switching of the HV9931 is disabled. When the PWMD pin is released, or external TTL high level is applied to it, switching will resume. This feature is provided for applications that require PWM dimming of the LED lamp. CS1 and CS2 - These pins are used to sense the input and output currents of the converter. They are the inverting inputs of the internal comparators.
Pinout
SOIC-8, DIP-8
1 8
VIN
RT
CS1
2
7
CS2
HV9931
GND 3 6 VDD
GATE
4
5
PWMD
Functional Block Diagram
VIN
REGULATOR
7.5V
VDD
CS1
S RQ
OSC
RT
GATE
CS2
PWMD
AGND
HV9931
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Typical Performance Characteristics (T
VDD vs. Junction Temperature (LIN = 2mA)
7.7
HV9931
Blanking Delay vs. Junction Temperature
300
= 25OC, VIN=100V unless otherwise noted) J
7.65
250
200
TBLANK (ns)
-20 0 20 40 60 80 100 120
7.6
VDD (V)
150
7.55
100
7.5
50
7.45 -40
Junction Tem perature (C)
0 -40
-20
0
20
40
60
80
100
120
Junction Tem perature (C)
Frequency vs. Junction Temperature (RT = 226K)
93
8 7.5
VDD vs. Regulator Current (VIN = 100V)
92
7
Frequency (kHz)
VDD (V)
91
6.5 6 5.5 5
90
89
4.5
88 -40
4
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
Junction Tem perature (C)
IIN (mA)
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Functional Description
Power Topology
The HV9931 is optimized to drive Supertex's proprietary singlestage, single-switch, non-isolated topology, cascading an input power factor correction (PFC) buck-boost stage and an output buck converter power stage. This power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (HB LED). These advantages include unity power factor, low harmonic distortion of the input AC line current, and low output current ripple. The output load is decoupled from the input voltage with a capacitor making the driver inherently failure-safe for the output load. The power converter topology also permits reducing the size of a filter capacitor needed, enabling use of non-electrolytic capacitors. The latter advantage greatly improves reliability of the overall solution. The HV9931 is a peak current-mode controller that is specifically designed to drive a constant current buckboost-buck power converter. This patent pending control scheme features two identical current sense comparators for detecting negative current signal levels. One of the comparators regulates the output LED current. The other one is used for sensing the input inductor current. The second comparator is mainly responsible for the converter startup. The control scheme inherently features low inrush current and input under-voltage protection. The HV9931 can operate with programmable constant frequency or constant off-time. In many cases, the constant off-time operating mode is preferred, since it improves line regulation of the output current, reduces voltage stress of the power components and simplifies regulatory EMI compliance. (See Application Note AN-H52.) Input Voltage Regulator The HV9931 can be powered directly from its VIN pin and takes a voltage from 8V to 450V. When a voltage is applied at the VIN pin, the HV9931 seeks to maintain a constant 7.5V at the VDD pin. The VDD voltage can be also used as a reference for the current sense comparators. The regulator is equipped with an under-voltage protection circuit which shuts off the HV9931 when the voltage at the VDD pin falls below 6.2V. The VDD pin must be bypassed by a low ESR capacitor ( 0.1F) to provide a low impedance path for the high frequency current of the output gate driver. The HV9931 can also be operated by supplying a voltage at the VDD pin greater than the internally regulated voltage. This will turn off the internal linear regulator and the HV9931 will function by drawing power from the external voltage source connected to the VDD pin. PWM Dimming and Wall Dimmer Compatibility PWM Dimming can be achieved by applying a TTL-compatible square wave signal at the PWMD pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or connected to GND, the gate driver is disabled and the external MOSFET turns off. The HV9931 is designed so that the signal at the PWMD pin inhibits the driver only, and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The power topology requires little filter capacitance at the output, since the output current of the buck stage is continuous, and since AC line filtering is accomplished through the middle capacitor rather
5
HV9931
than the output one. Therefore, disabling the HV9931 via its PWMD or VIN pins can interrupt the output LED current in accordance with the phase-controlled voltage waveform of a standard wall dimmer. Oscillator Connecting an external resistor from RT pin to GND programs switching frequency:
FS [kHz ] =
25000 RT [K ]+ 22
Connecting the resistor from RT pin to GATE programs constant off-time:
TOFF [ s ] =
RT [K ]+ 22 25
Input and Output Current Feedback Two current sense comparators are included in the HV9931. Both comparators have their non-inverting inputs internally connected to ground (GND). The CS1 and CS2 inputs are inverting inputs of the comparators. Connecting a resistor divider into either of these inputs from a positive reference voltage and a negative current sense signal programs the current sense threshold of the comparator. The VDD voltage of the HV9931 can be used as the reference voltage. (If more accuracy is needed, an external reference voltage can be applied.) When either the CS1 or the CS2 pin voltage falls below GND, the GATE pulse is terminated. A leading edge blanking delay of 215ns (typ) is added. The GATE voltage becomes high again upon receiving the next clock pulse of the oscillator circuit. Referring to the Functional Circuit Diagram, the CS2 comparator is responsible for regulating output current. The output LED current can be programmed using the following equation:
RCS 2 =
Io +
1 I L2 2 RREF 2 RS 2 7.5V
where IL2 is the peak-to-peak current ripple in L2. The CS1 comparator limits the current in the input inductor L1. There is no charge in the capacitor C1 upon the start-up of the converter. Therefore, L2 cannot develop the output current, and the HV9931 starts-up in the input current limiting mode. The CS1 current threshold must be programmed such that no input current limiting occurs in normal steady-state operation. The CS1 threshold can be programmed in accordance with a similar equation:
RCS 1 =
I L1( PK ) 7.5V
RREF 1 RS 1
where IL1(PK) is the maximum peak current in L1. MOSFET Gate Driver Typically, the gate driving capability of the HV9931 is limited by the amount of power dissipation in its linear regulator. Thus, care must be taken selecting a switching MOSFET to be used in the circuit. An optimal trade-off must be found between the gate charge and the on-resistance of the MOSFET to minimize the input regulator current.
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Functional Circuit Diagram
D1
HV9931
VIN
D4
L1
C1
L2 D2
iL1 CIN ~AC ~AC RS1
+
Q1
VC1
_
D3
iL2 VO RS2
+ _
RCS2
RCS1
RT
_ VS1 +
+
VS2
GATE
PWMD
RT
OSC
SQ R
CS1
CS2
Rref1
Rref2
RE G
VIN VDD GND
HV9931
7.5V
CDD
Switching Waveform
VDD
GATE
0
t
iL2
0
t
iL1
0
t
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8-Lead Small Outline Package (LG)
0.192 0.005 (4.8895 0.1143)
D
HV9931
H
0.236 0.008 (5.9944 0.2032)
E
H1
0.154 0.004 (3.9116 0.1016)
0.193 0.012 (4.9022 0.3048)
7 (4 PLCS) 0.010 0.002 C (0.254 0.0508) 45
h
0.020 0.009 (0.508 0.2286)
0.061 0.008 A (1.5494 0.2032)
e A1 B
L1
0 - 8 0.016 0.002 (0.4064 0.0508)
L
0.007 0.003 (0.1778 0.0762)
0.050 TYP. (1.270)
0.035 0.015 (0.889 0.381)
0.0275 0.0025 (0.6985 0.0635)
8-Lead Plastic Dual In-Line Package (P)
0.040 (1.016) TYP 0.395 max
0.250 0.015
0.250 0.005
0.030 0.110
1
0.300 - 0.320
0.130 0.005
0.125 min.
0.020
0.020 min.
0 - 10
0.018 0.003 0.100 0.010 0.325 +0.025 -0.015
0.009 - 0.015
Note: Circle (e.g. B ) indicates JEDEC Reference.
Measurement Legend =
Dimensions in Inches (Dimensions in Millimeters)
Doc.# DSFP - HV9931
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