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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Features * PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. * Distributes one differential clock input pair to five differential clock output pairs. * Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 * Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 * External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the input clocks. * Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers * Packaging (Pb-free & Green available): - 28-pin TSSOP (L) Description PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The PI6CV855 is able to track Spread Spectrum Clocking to reduce EMI. Block Diagram Pin Configuration Y0 Y0 CLK CLK FBIN FBIN GND Y0 Y0 VDDQ CLK CLK AVDD AGND GND Y1 Y1 VDDQ Y2 Y2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Y4 Y4 VDDQ GND FBOUT FBOUT VDDQ FBIN FBIN GND VDDQ Y3 Y3 GND Y1 Y1 PLL Y2 Y2 Y3 Y3 Y4 Y4 28-Pin L 23 22 21 20 19 18 17 16 15 AVDD Logic and Test Ciruit FBOUT FBOUT 1 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Pinout Table Pin Name CLK CLK Y[0:4] Y[0:4] FBOUT FBOUT FBIN FBIN VDDQ AVDD AGND GND Pin No. 5 6 3,11,13,17,27 2,10,14,16,28 23 24 21 20 4,12,18,22,26 7 8 1,9,15,19,25 I O I/O Type I Reference Clock input Clock outputs. Complement Clock outputs. Feedback output, and Complement Feedback Output Feedback input, and Complement Feedback input Power Supply for I/O pins. Power Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When DD AVDD is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs. Ground Analog/core ground. Provides the ground reference for the analog/core circuitry Ground for I/O pins. De s cription Function Table Inputs AVDD GND GND 2.5V(nom) 2.5V(nom) CLK L H L H CLK H L H L Y[0:4] L H L H Y[0:4] H L H L Outputs FBOUT L H L H FBOUT H L H L Bypassed/Off Bypassed/Off on on PLL State 2 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Absolute Maximum Ratings (Over operating free-air temperature range) Symbol VDDQ, AVDD VI VO Tstg Parame te r I/O supply voltage range and analog/core supply voltage range Input voltage range Output voltage range Storage temperature M in. - 0.5 - 0.5 - 0.5 - 65 VDDQ+0.5 M a x. 3.6 V Units 15 0 oC Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Timing Requirements (Over recommended operating free-air temperature) Symbol De s cription Operating clock frequency(1,2) Application clock frequency(3) Input clock duty cycle PLL stabilization time after powerup AVDD, VDDQ = 2.5V 0.2V M in. 60 95 40 M a x. 170 17 0 60 100 Units fCK tDC tSTAB MHz % s Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters. 3 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory DC Specifications Recommended Operating Conditions Symbol AVDD VDDQ VOH VOL VIX VOX VIN VID VOD TA Analog/core supply voltage Output supply voltage High- level output voltage Low- level output voltage Input differential- pair crossing voltage Output differential- pair crossing voltage at the SDRAM clock input Input voltage level Input differential voltage between CLK and CLK Output differential voltage between Y[n] and Y[n] and FBOUT and FBOUT Operating free air temperature Parame te r M in. 2.3 2.3 1. 8 0 (VDDQ/2) -0.2 (VDDQ/2) -0.2 -0.3 0.36 0.7 0 Nom. 2.5 2.5 M ax. 2.7 2.7 VDDQ 0.5 (VDDQ/2) +0.2 (VDDQ/2) +0.2 VDDQ +0.3 VDDQ +0.6 VDDQ +0.6 70 C V Units Electrical Characteristics Parame te r VIK II IDDQ IADD CI All inputs CLK, FBIN Dynamic supply current of VDDQ Dynamic supply current of AVDD CLK and CLK FBIN and FBIN Te s t Conditions II = -18mA VI = VDDQ or GND VDD = 2.7V (1) VDD = 2.7V (1) VI = VDD or GND 2.5V 2.0 AVDD, VDDQ 2.3V 2.7V M in. Typ. M ax. -1.2 10 300 12 3.0 Units V A mA mA pF Notes: 1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz. 4 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory AC Specifications Switching characteristics over recommended operating free-air temperature range, fCLK > 100 MHz (unless otherwise noted). (See Figure 1 and 2) Parame te r t() tjit(cc) tjit(per) tjit(hper) tsl(i) tsl(o) tsk(o) De s cription Static phase offset(1) Cycle- to- cycle jitter Period jitter Half- period jitter Input clock slew rate(2) Output clock slew rate(2) Output clock skew Diagram Figure 4 Figure 3 Figure 6 Figure 7 Figure 8 Figure 8 Figure 5 AVCC, VDDQ = 2.5V 0.2V M in. -50 -75 -75 -100 1.0 1.0 Nom. 0 M ax 50 75 75 100 2.0 2.0 10 0 Units ps V/ns ps The PLL on the PI6CV855 meets all the above parameters while supporting SSC synthesizers with the following parameters(3). SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth Phase angle Notes: 1. Static Phase offset does not include jitter. 2. The slew rate is determined from the IBIS model with test load shown in Figure 1. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 30.0 0.00 2 50.0 -0.50 kHz % MHz -0.031 degrees 5 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 -VDDQ/2 VDDQ/2 VDD Z = 60 Z = 60 Figure 2. Output Load Test Circuit Figure 1. IBIS Model Output Load Z = 60 Z = 60 -VDDQ/2 -VDDQ/2 C=14pF C=14pF R =120 6 R =10 R =10 Z = 50 Z = 50 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory DDR SDRAM DDR SDRAM SCOPE R = 50 R = 50 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Yx,FBOUT Yx,FBOUT t cycle n t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 Figure 3. Cycle-to-Cycle Jitter CLK CLK FBIN FBIN t( )n t( n=N ) n+1 t 1 = t( )n (N is a large number of samples) N Figure 4. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT t sk(o) Figure 5. Output Skew 7 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Yx, FBOUT Yx, FBOUT t cycle n Yx, FBOUT Yx, FBOUT 1 fO t jit(per) = t cycle n Figure 6. Period Jitter 1 fO Yx, FBOUT Yx, FBOUT t half period n 1 fO t n+1 half period t jit(hper) = t half period n Figure 7. Half-Period Jitter 1 2*f O 80% 80% VDDQ Clock Inputs and Outputs 20% 20% 0V t sl(i), t sl(o) t sl(i), t sl(o) Figure 8. Input and Output Slew Rates 8 PS8545C 09/16/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Packaging Mechanical: 28-Pin TSSOP (L) 28 .169 .177 4.3 4.5 1 .378 .386 9.6 9.8 .047 1.20 Max SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4 .004 .008 0.09 0.20 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS .0256 BSC 0.65 .007 .012 0.19 0.30 .002 .006 0.05 0.15 Ordering Information Ordering Code PI6CV855L PI6CV855LE Package Code L L Package Type 28-pin 173-mil wide TSSOP Pb-free & Green, 28-pin 173-mil wide TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 9 PS8545C 09/16/04 |
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