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OPA
691
OPA6 91
OPA691
SBOS226A - DECEMBER 2001- REVISED SEPTEMBER 2002
Wideband, Current Feedback OPERATIONAL AMPLIFIER With Disable
FEATURES
q FLEXIBLE SUPPLY RANGE: +5V to +12V Single-Supply 2.5V to 6V Dual-Supply q UNITY-GAIN STABLE: 280MHz (G = 1) q HIGH OUTPUT CURRENT: 190mA q OUTPUT VOLTAGE SWING: 4.0V q HIGH SLEW RATE: 2100V/s q LOW dG/d: 0.07% /0.02 q LOW SUPPLY CURRENT: 5.1mA q LOW DISABLED CURRENT: 150A q WIDEBAND +5V OPERATION: 190MHz (G = +2)
APPLICATIONS
q q q q q q q q xDSL LINE DRIVER BROADBAND VIDEO BUFFERS HIGH-SPEED IMAGING CHANNELS PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS WIDEBAND INVERTING SUMMING HIGH SFDR IF AMPLIFIER
DESCRIPTION
The OPA691 sets a new level of performance for broadband current feedback op amps. Operating on a very low 5.1mA supply current, the OPA691 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. This gives exceptional single-supply operation. Using a single +5V supply, the OPA691 can deliver a 1V to 4V output swing with over 150mA drive current and 190MHz bandwidth. This combination of features makes the OPA691 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. The OPA691's low 5.1mA supply current is precisely trimmed at 25C. This trim, along with low drift over-temperature,
ensures lower maximum supply current than competing products. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA691 supply current drops to less than 150A while the output goes into a high impedance state. This feature may be used for power savings.
OPA691 RELATED PRODUCTS
SINGLES Voltage Feedback Current Feedback Fixed Gain OPA690 OPA681 OPA692 DUALS OPA2690 OPA2691 TRIPLES OPA3690 OPA3691 OPA3692
+5V DIS
50 V1 50 V2 50 V3 50 V4 50 V5 -5V 30 100
50
VO = -(V1 + V2 + V3 + V4 + V5) RG-58 50
OPA691
100MHz, -1dB Compression = 15dBm
200MHz RF Summing Amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2001, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
Power Supply .............................................................................. 6.5VDC Internal Power Dissipation(2) ............................ See Thermal Information Differential Input Voltage .................................................................. 1.2V Input Voltage Range ............................................................................ VS Storage Temperature Range: ID, IDBV ......................... -40C to +125C Lead Temperature (soldering, 10s) .............................................. +300C Junction Temperature (TJ ) ........................................................... +175C ESD Performance: HBM .............................................................................................. 2000V CDM .............................................................................................. 1500V NOTES:: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Packages must be derated based on specified JA. Maximum TJ must be observed.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING OPA691 ORDERING NUMBER OPA691ID OPA691IDR OPA691IDBVT OPA691IDBVR TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000
PRODUCT OPA691ID
PACKAGE-LEAD SO-8
"
OPA691IDBV
"
SOT23-6
"
DBV
"
-40C to +85C
"
OAFI
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View SO Top View SOT
Output
1
6
+VS
-VS
2
5
DIS
NC Inverting Input Noninverting Input -VS
1 2 3 4
8 7 6 5
DIS +VS Output
6 5 4 Noninverting Input 3 4 Inverting Input
NC
NC = No Connection
OAFI
1 2 3 Pin Orientation/Package Marking
2
OPA691
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SBOS226A
ELECTRICAL CHARACTERISTICS: VS = 5V
Boldface limits are tested at +25C.
RF = 402, RL = 100, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. OPA691ID, IDBV TYP MIN/MAX OVER-TEMPERATURE 0C to PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (VO = 0.5Vp-p) CONDITIONS G = +1, RF = 453 G = +2, RF = 402 G = +5, RF = 261 G = +10, RF = 180 G = +2, VO = 0.5Vp-p RF = 453, VO = 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100 RL 500 RL = 100 RL 500 f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 RL = 37.5 G = +2, NTSC, VO = 1.4Vp, RL = 150 RL = 37.5 VO = 0V, RL = 100 VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V +25C 280 225 210 200 90 0.2 200 2100 1.6 1.9 12 8 -70 -79 -74 -93 1.7 12 15 0.07 0.17 0.02 0.07 225 0.5 +15 5 +25C(1) 70C(2) -40C to +85C(2) UNITS MHz MHz MHz MHz MHz dB MHz V/s ns ns ns ns dBc dBc dBc dBc nV/HZ pA/HZ pA/HZ % % deg deg k mV V/C A nA/C A nA/C V dB k || pF V V mA mA mA A ns ns dB pF mV mV V V A V V mA mA dB C C/W C/W MIN/
TEST
MAX LEVEL(3) typ min typ typ min max typ min typ typ typ typ max max max max max max max typ typ typ typ min max max max max max max min min typ typ min min min min typ typ max typ typ typ typ typ typ min max max typ max max min min typ typ typ C B C C B B C B C C C C B B B B B B B C C C C A A B A B A B A A C C A A A A C C A C C C C C C A A A C A A A A C C C
200
190
180
Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase
40 1 1400
35 1.5 1375
20 2 1350
-63 -70 -72 -87 2.5 14 17
-60 -67 -70 -82 2.9 15 18
-58 -65 -68 -78 3.1 15 19
DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range(5) Common-Mode Rejection Noninverting Input Impedance Inverting Input Resistance (RI) OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (-PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, JA D SO-8 DBV SOT23-6
2.5
+35
125
25 3.4
52
110 3.2 12 +43 -300 30 90 3.3 51
100 3.9 20 +45 -300 40 200 3.2 50
VCM = 0V Open-Loop No Load 100 Load VO = 0 VO = 0 VO = 0 G = +2, f = 100kHz VDIS = 0 VIN = 1V VIN = 1V G = +2, 5MHz G = +2, RL = 150, VIN = 0 G = +2, RL = 150, VIN = 0 VDIS = 0
3.5 56 100 || 2 35 4.0 3.9 +190 -190 250 0.03 -150 400 25 70 4 50 20 3.3 1.8 75 5
3.8 3.7
+160 -160
3.7 3.6 +140 -140
3.6 3.3 +100 -100
-300
-350
-400
3.5 1.7 130
3.6 1.6 150
3.7 1.5 160
VS = 5V VS = 5V Input Referred
6
5.3 4.9 52
5.1 5.1 58 -40 to +85
6 5.5 4.7 50
6 5.7 4.5 49
Junction-to-Ambient 125 150
NOTES: (1) Junction temperature = ambient for 25C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +10C at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at CMIR limits.
OPA691
SBOS226A
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3
ELECTRICAL CHARACTERISTICS: VS = +5V
Bolace limits are tested at +25C.
RF = 453, RL = 100 to VS/2, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted. OPA691ID, IDBV TYP MIN/MAX OVER-TEMPERATURE +25C(1) 0C to 70C(2) -40C to +85C(2) MIN/ TEST MAX LEVEL(3) typ min typ typ min max typ min typ typ typ typ max max max max typ typ typ min max max max max max max max min min typ typ min min max max min min typ typ max typ typ typ typ min max typ typ max max min typ typ typ typ C B C C B B C B C C C C B B B B B B B A A B A B A B A A A C C A A A A A A C C A C C C C A A C C A A A C C C C
PARAMETER AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth (VO = 0.5Vp-p)
CONDITIONS G = +1, RF = 499 G = +2, RF = 453 G = +5, RF = 340 G = +10, RF = 180 G = +2, VO < 0.5Vp-p RF = 649, VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100 to VS /2 RL 500 to VS /2 RL = 100 to VS /2 RL 500 to VS /2 f > 1MHz f > 1MHz f > 1MHz VO = VS /2, RL = 100 to VS /2 VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V
+25C 210 190 180 155 90 0.2 210 850 2.0 2.3 14 10 -66 -73 -71 -77 1.7 12 15 200 0.5 +20 5
UNITS MHz MHz MHz MHz MHz dB MHz V/s ns ns ns ns dBc dBc dBc dBc nV/Hz pA/Hz pA/Hz k mV V/C A nA/C A nA /C V V dB k || pF V V V V mA mA mA A dB pF mV mV V V A V V mA mA dB C C/W C/W
168
160
140
Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Inverting Input Resistance (RI ) OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single-Supply Operating Voltage Max Single-Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (-PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, JA D SO-8 DBV SOT23-6
40 1 600
30 2.5 575
25 3.0 550
-58 -65 -68 -72 2.5 14 17 100
-57 -63 -67 -70 2.9 15 18 90 3.6 12 +46 -250 25 112 1.7 3.3 49
-56 -62 -65 -69 3.1 15 19 80 4.3 20 +56 -250 35 250 1.8 3.2 48
3
+40
20
1.6 3.4 50
VCM = VS /2 Open-Loop No Load RL = 100 to VS /2 No Load RL = 100 to VS /2 VO = VS /2 VO = VS /2 VO = VS/2 G = +2, f = 100kHz VDIS = 0 G = +2, 5MHz G = +2, RL = 150, VIN = VS /2 G = +2, RL = 150, VIN = VS /2 VDIS = 0
1.5 3.5 54 100 || 2 38 4 3.9 1 1.1 +160 -160 250 0.03 -150 65 4 50 20 3.3 1.8 75 5
3.8 3.7 1.2 1.3 +120 -120
3.7 3.6 1.3 1.4 +100 -100
3.5 3.4 1.5 1.6 +80 -80
-300
-350
-400
3.5 1.7 130
3.6 1.6 150
3.7 1.5 160
VS = +5V VS = +5V Input Referred
4.5 4.5 55 -40 to +85
12 4.8 4.1
12 5.0 4.0
12 5.2 3.8
Junction-to-Ambient 125 150
NOTES: (3) Test levels: (A) 100% tested at 25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (1) Junction temperature = ambient for 25C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +10C at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at CMIR limits.
4
OPA691
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SBOS226A
TYPICAL CHARACTERISTICS: VS = 5V
G = +2, RF = 402, and RL = 100, unless otherwise noted (see Figure 1).
SMALL-SIGNAL FREQUENCY RESPONSE 1 0
Normalized Gain (1dB/div)
LARGE-SIGNAL FREQUENCY RESPONSE 7.0 6.5 6.0
Gain (0.5dB/div)
G = +1, RF = 453 G = +2, RF = 402
G = +2, RL = 100 2Vp-p 1Vp-p
-1 -2 -3 -4 -5 -6 -7 -8 0 VO = 0.5Vp-p 125MHz Frequency (25MHz/div) G = +5, RF = 261
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 7Vp-p 4Vp-p
G = +10, RF = 180
250MHz
0
125MHz Frequency (25MHz/div)
250MHz
SMALL-SIGNAL PULSE RESPONSE +400
LARGE-SIGNAL PULSE RESPONSE +4 +3 G = +2 VO = 5Vp-p
Output Voltage (100mV/div)
+300 +200 +100 0 -100 -200 -300 -400 Time (5ns/div)
G = +2 VO = 0.5Vp-p
Output Voltage (1V/div)
+2 +1 0 -1 -2 -3 -4 Time (5ns/div)
COMPOSITE VIDEO dG/dP 0.2 0.18 0.16 0.14
dG/dP (%/)
402 -5 Video In +5 Video Loads
DISABLED FEEDTHROUGH vs FREQUENCY -45 -50 -55 VDIS = 0
OPA691
402
No Pull-Down With 1.3k Pull-Down dG
Feedthrough (5dB/div)
-60 -65 -70 -75 -80 -85 -90 -95 -100 Forward Reverse
Optional 1.3k Pull-Down
0.12 0.1 0.08 0.06 0.04 0.02 0 1 2 3 4 Number of 150 Loads dP dP dG
0.3
1
10 Frequency (MHz)
100
OPA691
SBOS226A
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5
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
G = +2, RF = 402, and RL = 100, unless otherwise noted (see Figure 1).
HARMONIC DISTORTION vs LOAD RESISTANCE -60 -65
Harmonic Distortion (dBc)
HARMONIC DISTORTION vs SUPPLY VOLTAGE -60 VO = 2Vp-p RL = 100 f = 5MHz
VO = 2Vp-p f = 5MHz
Harmonic Distortion (dBc)
-70 2nd-Harmonic -75 -80 -85 3rd-Harmonic -90 -95 -100 100 Load Resistance () 1000
-65
2nd-Harmonic
-70
-75 3rd-Harmonic -80
-85 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage (V)
HARMONIC DISTORTION vs FREQUENCY -50 dBc = dB Below Carrier
HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 RL = 100 f = 5MHz
Harmonic Distortion (dBc)
2nd-Harmonic
Harmonic Distortion (dBc)
-60
VO = 2Vp-p RL = 100
2nd-Harmonic
-70
-70 3rd-Harmonic
-75 3rd-Harmonic
-80
-90
-80
-100 0.1 1 Frequency (MHz) 10 20
-85 0.1 1 Output Voltage Swing (Vp-p) 5
HARMONIC DISTORTION vs NONINVERTING GAIN -50 VO = 2Vp-p RL = 100 f = 5MHz -60 2nd-Harmonic
-50
HARMONIC DISTORTION vs INVERTING GAIN VO = 2Vp-p RL = 100 f = 5MHz RF = 402
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
2nd-Harmonic
-70
-70 3rd-Harmonic -80
-80
3rd-Harmonic
-90 1 Gain (V/V) 10
-90 1 Inverting Gain (V/V) 10
6
OPA691
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SBOS226A
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
G = +2, RF = 402, and RL = 100, unless otherwise noted (see Figure 1).
INPUT VOLTAGE AND CURRENT NOISE DENSITY 100
3rd-Order Spurious Level (dBc)
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 -40 20MHz -50 10MHz -60 -70 -80 -90 Load Power at Matched 50 Load -8 -6 -4 -2 0 2 4 6 8 10 dBc = dB below carriers 50MHz
Current Noise (pA/Hz) Voltage Noise (nV/Hz)
Inverting Input Current Noise (15pA/Hz)
10 Noninverting Input Current Noise (12pA/Hz)
Voltage Noise (1.7nV/Hz)
1 100 1k 10k 100k 1M 10M Frequency (Hz)
Single-Tone Load Power (dBm)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
70 60 50
9 6 3 CL = 22pF 0
VIN
CL = 10pF
RS ()
40 30 20 10 0 1 10 100 1k Capacitive Load (pF)
-3 -6
RS
OPA691
CL = 47pF
VO 1k
402 402
CL
1k is optional.
CL = 100pF 125MHz 250MHz
-9 0 Frequency (25MHz/div)
CMRR AND PSRR vs FREQUENCY 65
Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB)
120
Transimpedance Gain (20dB/div)
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE 0 | ZOL| ZOL -40 -80 -120 -160 -200 -240 10k 100k 1M 10M 100M 1G Frequency (Hz)
Transimpedance Phase (40/div)
+PSRR 60 55 50 45 40 35 30 25 20 1k 10k 100k 1M 10M 100M Frequency (Hz) -PSRR CMRR
100 80 60 40 20 0
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SBOS226A
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7
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
G = +2, RF = 402, and RL = 100, unless otherwise noted (see Figure 1).
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 10 Sourcing Output Current
Output Current (50mA/div) Supply Current (2mA/div)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
250
5 4 1W Internal Power Limit
Output Current Limit
8 Sinking Output Current 6
200
3 2
VO (V)
150
1 0 -1 -2 -3 -4 Output Current Limit -300 -250 -200 -150 -100 -50 0 25 Load Line 50 Load Line 100 Load Line 1W Internal Power Limit +50 +100 +150 +200 +250 +300
4
Quiescent Supply Current
100
2
50
0 -50 -25 0 25 50 75 100 125 Ambient Temperature (C)
0
-5 IO (mA)
TYPICAL DC DRIFT OVER TEMPERATURE 2 1.5 40 30 10
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
+5
Input Offset Voltage (mV)
Output Impedance ()
1 0.5 0 -0.5 -1 -1.5 -2 -50 -25
20 10
Input Bias Currents (A)
Noninverting Input Bias Current (IB+)
50
OPA691
402
1
-5 402
ZO
Inverting Input Bias Current (IB-) Input Offset Voltage (VOS) 0 25 50 75 100 125
0 -10 -20 -30 -40
0.1
0.01 10k 100k 1M Frequency (Hz) 10M 100M
Ambient Temperature (C)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS (2V/div) 6.0 Output Voltage (400mV/div) VDIS 4.0 2.0 0 2.0 1.6 1.2 0.8 0.4 0 VIN = +1V Output Voltage
DISABLE/ENABLE GLITCH 4.0 Output Voltage (10mV/div) VDIS 30 20 10 0 -10 -20 -30 VIN = 0V Time (20ns/div) Output Voltage (0V Input) 2.0 0 VDIS (2V/div) 6.0
Time (200ns/div)
8
OPA691
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SBOS226A
TYPICAL CHARACTERISTICS: VS = +5V
G = +2, RF = 453, and RL = 100 to +2.5V, unless otherwise noted (see Figure 2).
SMALL-SIGNAL FREQUENCY RESPONSE 1 0
Normalized Gain (1dB/div)
LARGE-SIGNAL FREQUENCY RESPONSE 7.0 6.5 6.0
Gain (0.5dB/div)
G = +1, RF = 499 G = +2, RF = 453 G = +5, RF = 340
VO = 0.5Vp-p
-1 -2 -3 -4 -5 -6 -7 -8 0 VO = 0.5Vp-p G = +10, RF = 180 125MHz Frequency (25MHz/div) 250MHz
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 125MHz Frequency (25MHz/div) 250MHz G = +2 RL = 100 to 2.5V VO = 1Vp-p VO = 2Vp-p
SMALL-SIGNAL PULSE RESPONSE 2.9 2.8 Output Voltage (100mV/div) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 Time (5ns/div) Output Voltage (400mV/div) G = +2 VO = 0.5Vp-p 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9
LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 2Vp-p
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
50 40 RS () 30 20 10 0 1 10 Capacitive Load (pF) 100
Normalized Gain to Capacitive Load (dB)
60
9 6 3 CL = 47pF 0
+5V
CL = 10pF
CL = 22pF
VO RS
-3 -6 -9 0
VI
0.1F 57.6
806 806 OPA691 CL
CL = 100pF
453 453 0.1F
1k
1k is optional.
125MHz Frequency (25MHz/div)
250MHz
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SBOS226A
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TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
G = +2, RF = 453, and RL = 100 to +2.5V, unless otherwise noted (see Figure 2).
HARMONIC DISTORTION vs LOAD RESISTANCE -60 VO = 2Vp-p f = 5MHz
Harmonic Distortion (dBc)
-50
HARMONIC DISTORTION vs FREQUENCY VO = 2Vp-p RL = 100 to 2.5V -60 2nd-Harmonic -70
-65 2nd-Harmonic -70
Harmonic Distortion (dBc)
3rd-Harmonic -75
-80
3rd-Harmonic
-80 100 Resistance () 1000
-90 0.1 1 Frequency (MHz) 10 20
HARMONIC DISTORTION vs OUTPUT VOLTAGE -60
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 dBc = dB below carriers 50MHz -50 -60 -70 10MHz -80 -90 -100 Load Power at Matched 50 Load -14 -12 -10 -8 -6 -4 -2 0 2 20MHz
3rd-Order Spurious Level (dBc)
3
RL = 100 to 2.5V f = 5MHz
Harmonic Distortion (dBc)
2nd-Harmonic
-40
-65
-70 3rd-Harmonic -75
-80 0.1 1 Output Voltage Swing (Vp-p)
Single-Tone Load Power (dBm)
10
OPA691
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SBOS226A
APPLICATIONS INFORMATION
WIDEBAND CURRENT FEEDBACK OPERATION
The OPA691 gives the exceptional AC performance of a wideband current feedback op amp with a highly linear, high power output stage. Requiring only 5.1mA quiescent current, the OPA691 will swing to within 1V of either supply rail and deliver in excess of 160mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA691 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100 on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA691 achieves a comparable power gain with much better linearity. The primary advantage of a current feedback op amp over a voltage feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. For similar AC performance at low gains, with improved DC accuracy, consider the high slew rate, unity-gain stable, voltage feedback OPA690. Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the 5V Electrical Characteristic tables and Typical Characteristic curves. For test purposes, the input impedance is set to 50 with a resistor to ground and the output impedance is set to 50 with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50 load. For the circuit of Figure 1, the total effective load will be 100 || 804 = 89. The disable control line (DIS) is typically left open to ensure normal amplifier operation. One optional component is included in Figure 1. In addition to the usual power-supply de-coupling capacitors to ground, a 0.1F capacitor is included between the two power-supply
pins. In practical PC board layouts, this optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical Characteristic tables and Typical Characteristic curves. Though not a "rail-to-rail" design, the OPA691 requires minimal input and output voltage headroom compared to other very wideband current feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband singlesupply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806 resistors). The input signal is then ACcoupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6) used for testing is adjusted to give a 50 input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1--which puts the input DC bias voltage (2.5V) on the output as well. The feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V, gain of +2, operation (see Setting Resistor Values to Optimize Bandwidth). Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 120mA output current. A demanding 100 load to a mid-point bias is used in this characterization circuit. The new output stage used in the OPA691 can deliver large bipolar output currents into this mid-point load with minimal crossover distortion, as shown by the +5V supply, 3rd-harmonic distortion plots.
+5V +VS 0.1F 6.8F +
+5V +VS
0.1F
50 Source DIS VI 50 VO 50 50 Load
+
6.8F
806 0.1F VI DIS 806 VO 100 VS/2
OPA691
57.6
OPA691
0.1F
RF 402
RF 453
RG 402 + -VS -5V 6.8F 0.1F
RG 453 0.1F
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification and Test Circuit.
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SINGLE-SUPPLY ADC INTERFACE
Most modern, high performance ADCs (such as the Texas Instruments ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA691 make it an ideal single-supply ADC driver. Figure 3 shows an example input interface to a very high performance, 10-bit, 60MSPS CMOS converter. The OPA691 in the circuit of Figure 3 provides > 180MHz bandwidth operating at a signal gain of +4 with a 2Vp-p output swing. One of the primary advantages of the current feedback internal architecture used in the OPA691 is that high bandwidth can be maintained as the signal gain is increased. The noninverting input bias voltage is referenced to the midpoint of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. With the gain resistor (RG) AC-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. Tested performance at a 20MHz analog input frequency and a 60MSPS clock rate on the converter gives > 58dBc SFDR.
the sum of RF + (RI * NG) where RI is the impedance looking into the inverting input from the summing junction (see the Setting Resistor Values to Optimize Performance section). Using 100 feedback (to get a signal gain of -2 from each input to the output pin) requires an additional 30 in series with the inverting input to increase the feedback impedance. With this resistor added to the typical internal RI = 35, the total feedback impedance is 100 + (65 * 6) = 490, which is equal to the required value to get a maximum bandwidth flat frequency response for NG = 6. Tested performance shows more than 200MHz small-signal bandwidth and a -1dBm compression of 15dBm at the matched 50 load through 100MHz.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple "Wired-OR Video Multiplexer" can be easily implemented using the OPA691, see Figure 4. Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The "make-before-break" disable characteristic of the OPA691 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that presented in Figure 4. Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5 in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75 output impedance to the cable. The video multiplexer connection (see Figure 4)
WIDEBAND INVERTING SUMMING AMPLIFIER
Since the signal bandwidth for a current feedback op amp may be controlled independently of the noise gain (NG, which is normally the same as the noninverting signal gain), very broadband inverting summing stages may be implemented using the OPA691. The circuit on the front page of this data sheet shows an example inverting summing amplifier where the resistor values have been adjusted to maintain both maximum bandwidth and input impedance matching. If each RF signal is assumed to be driven from a 50 source, the NG for this circuit will be (1 + 100/(100/5)) = 6. The total feedback impedance (from VO to the inverting error current) is
+5V
RF 360 Clock 50
+5V
0.1F
RG 120 OPA691
ADS823 10-Bit 60MSPS Input 22pF Input CM
0.5Vp-p 0.1F
2Vp-p DIS 2k
+3.5V REFT 0.1F
+2.5V DC Bias 2k
+1.5V REFB 0.1F
FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver.
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also ensures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated 1.2V maximum for standard video signal levels. The section on Disable Operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than 50mV. Where two outputs are switched (see Figure 6), the output line is always under the
control of one amplifier or the other due to the "make-beforebreak" disable timing. In this case, the switching glitches for two 0V inputs drop to < 20mV.
4-CHANNEL FREQUENCY CHANNELIZER
The circuit of Figure 5 is a 4-channel multiplexer. In this circuit the OPA691 provides the drive for all 4 channels.
+5V 2k VDIS +5V Video 1 DIS 75
OPA691
82.5
340
-5V
402 75 Cable
340 +5V
402 82.5
RG-59
Video 2 75 2k
OPA691
DIS -5V
FIGURE 4. 2-Channel Video Multiplexer.
+5V 75 #1
DIS 1 59
OPA691
75 -5V 402 RO
402 +5V 75 #2 59 DIS 2
OPA691
+5V 75 -5V 402 75 Cable VOUT 402 -5V 75 #3 59 RG-59 +5V DIS 3 75 Load RO
OPA691
OPA691
75 -5V 402 RO
402 75 #4
+5V
DIS 4 59
OPA691
75 -5V 402 RO
402
FIGURE 5. 4-Channel Frequency Channelizer.
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Each channel includes a bandpass filter. Each bandpass filter is set for a different frequency band. This allows the channelizing part of this circuit. The role of the channelizers OPA691s is to provide impedance isolation. This is done through the use of four matching resistances (59 in this case). These matching resistors ensure that the signals will combine during the transition between channels. They have been used to get a gain of +1 at the load. This circuit may be used with a different number of channels. Its limitation comes from the drive requirement for each channel as well as the minimum acceptable return loss. The output resistor value (RO) to keep a gain of +1 at the load depends on the number of channels. For the OPA691 with a gain of 2 using RF = 402 and RG = 402, Equation 1 is: (1)
RO =
[75 * (n - 1) + 804] *
2
1+
[
241200 - 1 75 * (n - 1) + 804
Bringing the signal in through a step-up transformer to the inverting input gain resistor has several advantages for the OPA691. First, the decoupling capacitor on the noninverting input eliminates the contribution of the noninverting input current noise to the output noise. Secondly, the noninverting input noise voltage of the op amp is actually attenuated if reflected to the input side of RG. Using the 1:2 (turns ratio) step-up transformer reflects the 50 source impedance at the primary through to the secondary as a 200 source impedance (and the 200 RG resistor is reflected through to the transformer primary as a 50 input matching impedance). The noise gain to the amplifier output is then 1 + 600/400 = 2.5V/V. Taking the op amp's 2.2nV/Hz input voltage noise times this noise gain to the output, then reflecting this noise term to the input side of the RG resistor, divides it by 3. This gives a net gain of 0.833 for the noninverting input voltage noise when reflected to the input point for the op amp circuit. This is further reduced when referred back to the transformer primary. The relatively low-gain IF amplifier circuit of Figure 6 gives a 12dB noise figure at the input of the transformer. Increasing the RF resistor to 600 (once RG is set to 200 for input impedance matching) will slightly reduce the bandwidth. Measured results show 150MHz small-signal bandwidth for the circuit of Figure 6 with exceptional flatness through 30MHz. Although the OPA691 does not show an intercept characteristic for the 2-tone, 3rd-order intermodulation distortion, it does hold a very high Spurious-Free Dynamic Range (SFDR) through high output powers and frequencies. The maximum single-tone power at the matched load for the single-supply circuit of Figure 6 is 1dBm (this requires a 2.8Vp-p swing at the output pin of the OPA691 for the 2-tone envelope). Measured 2-tone SFDR at this maximum load power for the circuit of Figure 6 exceeds 55dBc for frequencies to 20MHz.
]
SINGLE-SUPPLY "IF" AMPLIFIER
The high bandwidth provided by the OPA691 while operating on a single +5V supply lends itself well to IF amplifier applications. One of the advantages of using an op amp like the OPA691 as an IF amplifier is that precise signal gain is achieved along with much lower 3rd-order intermodulation versus quiescent power dissipation. In addition, the OPA691 in the SOT23-6 package offers a very small package with a power shutdown feature for portable applications. One concern with using op amps for an IF amplifier is their relatively high noise figures. It is sometimes suggested that an optimum source resistance can be used to minimize op amp noise figures. Adding a resistor to reach this optimum value may improve the noise figure, but will actually decrease the signal-to-noise ratio. A more effective way to move towards an optimum source impedance is to bring the signal in through an input transformer. Figure 6 shows an example that is particularly useful for the OPA691.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA691 in its two package styles. All of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below.
BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER SBOU009 SBOU010
+5V
Power-supply decoupling not shown. 5k DIS 50 1F 5k
OPA691
VO 50 Load
PRODUCT OPA691ID OPA691IDBV
PACKAGE SO-8 SOT23-6
50 Source VI 1:2
RG 200
RF 600
To request any of these boards, check the Texas Instruments web site at www.ti.com.
= 3V/V (9.54dB)
VO VI 0.1F
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF
FIGURE 6. Low-Noise, Single-Supply IF Amplifier.
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amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA691 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/d characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance.
RI, the buffer output impedance, is a critical portion of the bandwidth control equation. The OPA691 is typically about 35. A current feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response. This is analogous to the openloop voltage gain curve for a voltage feedback op amp. Developing the transfer function for the circuit of Figure 7 gives Equation 1:
R 1 + F RG VO NG = = VI RF 1 + RF + RI NG RF + RI 1 + ZS RG 1+ Z (S ) R NG = 1 + F RG
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
A current feedback op amp like the OPA691 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is shown in the Typical Characteristic curves; the small-signal bandwidth decreases only slightly with increasing gain. Those curves also show that the feedback resistor has been changed for each gain setting. The resistor "values" on the inverting side of the circuit for a current feedback op amp can be treated as frequency response compensation elements while their "ratios" set the signal gain. Figure 7 shows the smallsignal frequency response analysis circuit for the OPA691.
(2)
This is written in a loop-gain analysis format where the errors arising from a non-infinite open-loop gain are shown in the denominator. If Z(S) were infinite over all frequencies, the denominator of Equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation 1 determines the frequency response. Equation 2 shows this as the loop-gain equation:
Z (S ) RF + RI NG = Loop Gain
VI VO RI iERR Z(S) iERR RF
(3)
RG
FIGURE 7. Recommended Feedback Resistor versus Noise Gain. The key elements of this current feedback op amp model are: Buffer gain from the noninverting input to the inverting input RI Buffer output impedance iERR Feedback error current signal Z(s) Frequency dependent open-loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however, set the CMRR for a single op amp differential amplifier configuration. For a buffer gain < 1.0, the CMRR = -20 * log (1- ) dB.
If 20 * log (RF + NG * RI) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(S) rolls off to equal the denominator of Equation 2 at which point the loop gain has reduced to 1 (and the curves have intersected). This point of equality is where the amplifier's closed-loop frequency response given by Equation 1 will start to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage feedback op amp. The difference here is that the total impedance in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG). The OPA691 is internally compensated to give a maximally flat frequency response for RF = 402 at NG = 2 on 5V supplies. Evaluating the denominator of Equation 2 (which is the feedback transimpedance) gives an optimal target of 472. As the signal gain changes, the contribution of the NG * RI term in the feedback transimpedance will change, but the total can be held constant by adjusting RF . Equation 4 gives an approximate equation for optimum RF over signal gain: RF = 472 - NG RI (4)
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As the desired signal gain increases, this equation will eventually predict a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a minimum value of 20. Lower values will load both the buffer stage at the input and the output stage if RF gets too low-- actually decreasing the bandwidth. Figure 8 shows the recommended RF versus NG for both 5V and a single +5V operation. The values for RF versus gain shown here are approximately equal to the values used to generate the Typical Characteristics. They differ in that the optimized values used in the Typical Characteristics are also correcting for board parasitics not considered in the simplified analysis leading to Equation 3. The values shown in Figure 8 give a good starting point for design where bandwidth optimization is desired.
(e.g., integrators, transimpedance, and some filters) should consider the unity-gain stable voltage feedback OPA680, since the feedback resistor is the compensation element for a current feedback op amp. Wideband inverting operation (and especially summing) is particularly suited to the OPA691. See Figure 9 for a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration.
+5V Power-supply decoupling not shown. DIS OPA691 VO 50 50 Load
600 500
50 Source VI
+5V
RG 188
RF 374
Feedback Resistor ()
400 300 200 5V 100 0 0 5 10 Noise Gain 15 20
RM 68.1 -5V
FIGURE 9. Inverting Gain of -2 with Impedance Matching. In the inverting configuration, two key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PC board trace, or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. RG by itself is normally not set to the required input impedance since its value, along with the desired gain, will determine an RF which may be non-optimal from a frequency response standpoint. The total input impedance for the source becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and will have slight effect on the bandwidth through Equation 1. The values shown in Figure 9 have accounted for this by slightly decreasing RF (from Figure 1) to re-optimize the bandwidth for the noise gain of Figure 9 (NG = 2.73) In the example of Figure 9, the RM value combines in parallel with the external 50 source impedance, yielding an effective driving impedance of 50 || 68 = 28.8. This impedance is added in series with RG for calculating the noise gain--which gives NG = 2.73. This value, along with the RF of Figure 9 and the inverting input impedance of 35, are inserted into Equation 3 to get a feedback transimpedance nearly equal to the 472 optimum value. Note that the noninverting input in this bipolar supply inverting application is connected directly to ground. It is often suggested that an additional resistor be connected to ground
FIGURE 8. Feedback Resistor vs Noise Gain. The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of Equation 2), decreasing the bandwidth. This approach to bandwidth control is used for the inverting summing circuit on the front page. The internal buffer output impedance for the OPA691 is slightly influenced by the source impedance looking out of the noninverting input terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. For those single-supply applications which develop a midpoint bias at the noninverting input through high valued resistors, the decoupling capacitor is essential for power-supply noise rejection, noninverting input noise current shunting, and to minimize the high frequency value for RI in Figure 7.
INVERTING AMPLIFIER OPERATION
Since the OPA691 is a general-purpose, wideband current feedback op amp, most of the familiar op amp application circuits are available to the designer. Those applications that require considerable flexibility in the feedback element
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on the noninverting input to achieve bias current error cancellation at the output. The input bias currents for a current feedback op amp are not generally matched in either magnitude or polarity. Connecting a resistor to ground on the noninverting input of the OPA691 in the circuit of Figure 9 will actually provide additional gain for that input's bias and noise currents, but will not decrease the output DC error since the input bias currents are not matched.
OUTPUT CURRENT AND VOLTAGE
The OPA691 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. Under no-load conditions at 25C, the output voltage typically swings closer than 1V to either supply rail; the +25C swing limit is within 1.2V of either rail. Into a 15 load (the minimum tested load), it is tested to deliver more than 160mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage * current, or V-I product, which is more relevant to circuit operation. Refer to the "Output Voltage and Current Limitations" plot in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA691's output drive capabilities, noting that the graph is bounded by a "Safe Operating Area" of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA691 can drive 2.5V into 25 or 3.5V into 50 without exceeding the output capabilities or the 1W dissipation limit. A 100 load line (the standard test circuit load) shows the full 3.9V output swing capability, as shown in the Typical Specifications. The minimum specified output voltage and current overtemperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE's (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. To protect the output stage from accidental shorts to ground and the power supplies, output short-circuit protection is included in the OPA691. The circuit acts to limit the maximum source or sink current to approximately 250mA.
prove ADC linearity. A high-speed, high open-loop gain amplifier like the OPA691 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA691. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA691 output pin (see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA691 provides good distortion performance into a 100 load on 5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network--in the noninverting configuration (see Figure 1) this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1F) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate while the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the 2nd-harmonic increases by less than the expected 6dB while the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC--including additional external capacitance which may be recommended to im-
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dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50 load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall 2-tone envelope at the output pin), the Typical Characteristics show 48dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies.
Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 6. (6)
4kTRF 2 I R EN = ENI2 + (IBNR S ) + 4kTRS + BI F + NG NG
2
NOISE PERFORMANCE
Wideband current feedback op amps generally have a higher output noise than comparable voltage feedback op amps. The OPA691 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/Hz) is significantly lower than earlier solutions while the input voltage noise (1.7nV/Hz) is lower than most unity-gain stable, wideband, voltage feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (12pA/Hz). As long as the AC source impedance looking out of the noninverting node is less than 100, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 10 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/Hz or pA/Hz.
Evaluating these two equations for the OPA691 circuit and component values (see Figure 1) will give a total output spot noise voltage of 8.0nV/Hz and a total equivalent input spot noise voltage of 4.0nV/Hz. This total input-referred spot noise voltage is higher than the 1.7nV/Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high gain configurations (as suggested previously), the total inputreferred voltage noise given by Equation 5 will approach just the 1.7nV/Hz of the op amp itself. For example, going to a gain of +10 using RF = 180 will give a total input-referred noise of 2.1nV/Hz.
DC ACCURACY AND OFFSET CONTROL
A current feedback op amp like the OPA691 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Typical Specifications show an input offset voltage comparable to high-speed voltage feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage feedback op amps, they do not generally reduce the output DC offset for wideband current feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: (NG * VOS(MAX)) + (IBN * RS/2 * NG) (IBI * RF) where NG = noninverting signal gain = (2 * 2.5mV) + (35A * 25 * 2) (402 * 25A) = 5mV + 1.75mV 10.05mV = -13.3mV +16.8mV A fine-scale, output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most simple adjustment techniques do not correct for temperature drift. It is possible to combine a lower speed, precision op amp with the OPA691 to get the DC accuracy of the precision op amp along with the signal bandwidth of the OPA691. See Figure 11 for a noninverting G = +10 circuit that holds an output offset voltage less than 7.5mV overtemperature with > 150MHz signal bandwidth. This DC-coupled circuit provides very high signal bandwidth using the OPA691. At lower frequencies, the output voltage is attenuated by the signal gain and compared to the original
ENI
RS
OPA691 IBN
EO
ERS 4kTRS RF 4kTRF 4kT = 1.6E -20J at 290K
4kT RG
RG
IBI
FIGURE 10. Op Amp Noise Analysis Model.
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 5 shows the general form for the output noise voltage using the terms shown in Figure 10. (5)
2 2 EO = ENI2 + (IBNR S ) + 4kTRS NG2 + (IBIRF ) + 4kTRFNG
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input voltage at the inputs of the OPA237 (this is a low-cost, precision voltage feedback op amp with 1.5MHz gain bandwidth product). If these two don't agree (due to DC offsets introduced by the OPA691), the OPA237 sums in a correction current through the 2.86k inverting summing path. Several design considerations will allow this circuit to be optimized. First, the feedback to the OPA237's noninverting input must be precisely matched to the high-speed signal gain. Making the 2k resistor to ground an adjustable resistor would allow the low and high frequency gains to be precisely matched. Secondly, the crossover frequency region where the OPA237 passes control to the OPA691 must occur with exceptional phase linearity. These two issues reduce to designing for pole/zero cancellation in the overall transfer function. Using the 2.86k resistor will nominally satisfy this requirement for the circuit in Figure 11. Perfect cancellation over process and temperature is not possible. This initial resistor setting and precise gain matching, however, will minimize long-term pulse settling tails.
+5V
+VS
15k
Q1
25k VDIS IS Control
110k
-VS
FIGURE 12. Simplified Disable Control Circuit. When disabled, the output and input nodes go to a high impedance state. If the OPA691 is operating in a gain of +1, this will show a very high impedance (4pF || 1M) at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input-tooutput isolation. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 13 shows these glitches for the circuit of Figure 1 with the input signal set to 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. The transition edge rate (dV/dT) of the DIS control line will influence this glitch. For the plot of Figure 12, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the VDIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2k series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing.
Power supply de-coupling not shown
VI
DIS
OPA691
1.8k +5V
VO
2.86k
-5V 180
OPA237
20 -5V 18k
2k
FIGURE 11. Wideband, DC Connected Composite Circuit.
DISABLE OPERATION
The OPA691 provides an optional disable feature that may be used to reduce system power. If the DIS control pin is left unconnected, the OPA691 will operate normally. To disable, the control pin must be asserted LOW. Figure 12 shows a simplified internal circuit for the disable control feature. In normal operation, base current to Q1 is provided through the 110k resistor while the emitter current through the 15k resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1's emitter. As V DIS is pulled LOW, additional current is pulled through the 15k resistor eventually turning on these two diodes ( 75A). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 12. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break).
4.0
Output Voltage (10mV/div)
VDIS 30 20 10 0 -10 -20 -30 Time (20ns/div) Output Voltage (0V Input)
2.0 0
FIGURE 13. Disable/Enable Glitch.
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VDIS (2V/div)
6.0
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THERMAL ANALYSIS
Due to the high output power capability of the OPA691, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 175C. Operating junction temperature (TJ) is given by TA + PD * JA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 * RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA691IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85C and driving a grounded 20 load to +2.5V DC: PD = 10V * 5.7mA + 52/(4 * (20 || 804)) = 377m Maximum TJ = +85C + (0.377W * (150C/W) = 141.5C Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. Remember, this is a worst-case internal power dissipation--use your actual signal and load to computer PDL. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The "Output Voltage and Current Limitations" plot shown in the Typical Characteristics includes a boundary for 1W maximum internal power dissipation under these conditions.
b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1F decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2F to 6.8F) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA691. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a highfrequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402 feedback resistor used in the Electrical Characteristic tables at a gain of +2 on 5V supplies is a good starting point for design. Note that a 453 feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS versus Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA691 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA691 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
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design handbook for microstrip and stripline layout techniques). A 50 environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion, as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA691 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA691 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS versus Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA691 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA691 onto the board.
INPUT AND ESD PROTECTION
The OPA691 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 14. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with 15V supply parts driving into the OPA691), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
+V CC
External Pin
Internal Circuitry
-V CC
FIGURE 14. Internal ESD Protection.
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PACKAGE DRAWINGS
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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PACKAGE DRAWINGS (Cont.)
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,95 6 4
6X
0,50 0,25
0,20 M
1,70 1,50
3,00 2,60
0,15 NOM
1 3,00 2,80
3
Gage Plane
0,25 0 -8 0,55 0,35
Seating Plane 1,45 0,95 0,05 MIN 0,10
4073253-5/G 01/02
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
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