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 OPA300
SBOS271 - MAY 2003
Low-Noise, High-Speed, 16-Bit Accurate, CMOS OPERATIONAL AMPLIFIER
FEATURES
D D D D D D D D
High Bandwidth: 180MHz 16-Bit Settling in 150ns Low Noise: 3nV/Hz Low Distortion: 0.003% Low Power: 9.5mA (typ) on 5.5V Shutdown to 5A Unity Gain Stable Excellent Output Swing: (V+) - 100mV to (V-) + 100mV
DESCRIPTION
The OPA300 series high-speed, voltage-feedback, CMOS operational amplifiers are designed for 16-bit resolution systems. The OPA300 is unity gain stable and features excellent settling and harmonic distortion specifications. Low power applications benefit from the low quiescent current of the OPA300, and a digital shutdown (Enable) function provides additional power savings during idle periods. Optimized for single-supply operation, the OPA300 offers superior output swing and excellent common-mode range. The OPA300 has 180MHz of unity gain bandwidth, 500MHz of available bandwidth, low 3nV/Hz voltage noise, and 0.1% settling within 30ns. Single-supply operation on 2.7V (1.35V) and 5.5V (2.75V) and a shutdown function that reduces supply current to 5A are useful for portable low-power applications. The OPA300 is available in SO-8 packages, with SOT23-6 packages to be available Q3, 2003. The OPA300 is specified over the industrial temperature range of -40C to +125C.
D Single Supply: +2.7V to +5.5V D Tiny Packages: SO-8 and SOT23-6
(SOT23-6 available Q3, 2003)
APPLICATIONS
D D D D
16-Bit ADC Input Drivers Low-Noise Preamplifiers IF/RF Amplifiers Active Filtering
OPA300 NC -In +In V- 1 2 3 4 SO-8 NC = Not Connected 8 7 6 5 Enable V+ VOUT NC
OPA300 Out V- +In 1 2 3 6 5 4 SOT23-6(1) (1) Available Q3, 2003 V+ Enable -In
OPA300 VIN
16-Bit ADC
Typical Application of the OPA300
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
www.ti.com
OPA300
www.ti.com SBOS271 - MAY 2003
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) D DBV SPECIFIED TEMPERATURE RANGE -40C to +125C 40C 125C -40C to +125C 40C 125C PACKAGE MARKING 300A A52 ORDERING NUMBER OPA300AID OPA300D OPA300DBV(2) SO-8 SO 8 SOT23-6 SOT23 6 OPA300AIDR OPA300AIDBVT OPA300AIDBVR TRANSPORT MEDIA, QUANTITY Tube, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500
(1) For the most current specification and package information, refer to our web site at www.ti.com. (2) Shaded area indicates availability Q3, 2003.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) Power Supply V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Signal Input Terminals(2), Voltage . . . . . . . . . . . 0.5V to (V+) + 0.5V Current . . . . . . . . . . . . . . . . . . . . . 10mA Open Short-Circuit Current(3) . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature Range . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -60C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. (3) Short-circuit to ground; one amplifier per package.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN ASSIGNMENTS
TOP VIEW OPA300 OPA300(1) NC -In +In NC 1 2 3 4 8 7 6 5 Enable Out V+ V- Vout +In NC 3 4 -In 2 5 Enable 1 6 V+ SO TOP VIEW SOT23
NC = Not Connected
(1) Available Q3, 2003
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OPA300
www.ti.com SBOS271 - MAY 2003
ELECTRICAL CHARACTERISTICS: VS = 2.7V TO 5.5V
Boldface limits apply over the temperature range, TA = -40C to +125C.
All specifications at TA = +25C, RL = 2k connected to VS/2, VOUT = VS/2, and VCM = VS/2, unless otherwise noted.
OPA300 PARAMETER OFFSET VOLTAGE Input Offset Voltage Over Temperature Drift vs. Power Supply INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio INPUT BIAS CURRENT Input Bias Current Input Offset Current INPUT IMPEDANCE Differential Common-Mode NOISE Input Voltage Noise, f = 0.1Hz to 1MHz Input Voltage Noise Density, f = 100kHz Input Current Noise Density, f = 1kHz Differential Gain Error Differential Phase Error OPEN-LOOP GAIN Open-Loop Voltage Gain Over Temperature Over Temperature 40 Vpp nV/Hz fA/Hz % dB dB 106 dB dB 75 300 70 See Typical Characteristic 180 G = +1 VS = 5V, 2V Step, G = +1 Gain = -1 80 90 30 30 0.003 2.7 2.7 to 5.5 IO = 0 9.5 5.5 12 13 40 5 (V-) - 0.2 (V-) + 2.5 3 -40 -55 -65 (V-) + 0.8 (V+) + 0.2 5 125 150 150 200 MHz V/s ns ns ns % V V mA mA ns s V V A C C C C/W C/W 100 500 mV mV mA 1013 || 3 1013 || 6 || pF || pF TEST CONDITIONS MIN TYP 1 2.5 VS = 2.7V to 5.5V, VCM < (V+) -0.9V (V-) - 0.2 (V-) - 0.2V < VCM < (V+) - 0.9V 66 80 0.1 0.5 5 5 50 200 (V+) - 0.9 MAX 5 7 UNITS mV mV V/C V/V V dB pA pA
VOS
dVOS/dT
VS = 5V
PSRR VCM CMRR IB IOS
en in
RL = 150 RL = 150
3 1.5 0.01 0.1 95 90 95 90 106
AOL
VS = 5V, RL = 2k, 0.1V < VO < 4.9V VS = 5V, RL = 2k , 0.1V < VO < 4.9V VS = 5V, RL = 100, 0.5V < VO < 4.5V VS = 5V, RL = 100 , 0.5V < VO < 4.5V RL = 2k, AOL > 95dB RL = 100, AOL > 95dB
OUTPUT
Voltage Output Swing from Rail Short-Circuit Current Capacitive Load Drive FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time, 0.01% 0.1% Overload Recovery Time Total Harmonic Distortion + Noise POWER SUPPLY Specified Voltage Range Operating Voltage Range Quiescent Current (per amplifier) Over Temperature SHUTDOWN tOFF tON VL (shutdown) VH (amplifier is active) IQSD TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SO-8
ISC CLOAD GBW SR tS
THD+N VS IQ
VS = 5V, VO = 3Vpp, G = +1, f = 1kHz
JA
3
OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
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OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
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OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
6
OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
7
OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
8
OPA300
www.ti.com SBOS271 - MAY 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25C, V+ = 5V, RF = 310, and RL = 150 connected to VS/2 unless otherwise noted.
9
OPA300
www.ti.com SBOS271 - MAY 2003
APPLICATIONS INFORMATION
Built on HPA07, the latest TI high-precision analog process, the OPA300 single-supply CMOS op amp is designed to interface with high-speed 16-bit analog-to-digital converters (ADCs). Featuring wide 180MHz bandwidth, fast 150nS settling time to 16 bits, and high open loop gain, the OPA300 series offer excellent performance in a small SO-8 package.
PCB LAYOUT
As with most high-speed operational amplifiers, board layout requires special attention to maximize AC and DC performance. Extensive use of ground planes, short lead lengths, and high-quality bypass capacitors will minimize leakage that can compromise signal quality. Guard rings applied with potential as near to the input pins as possible help minimize board leakage.
THEORY OF OPERATION
The OPA300 uses a classic two-stage topology, shown in Figure 1. The differential input pair is biased to maximize slew rate without compromising stability or bandwidth. The folded cascode adds the signal from the input pair and presents a differential signal to the class AB output stage. The class AB output stage allows rail to rail output swing, with high-impedance loads (> 2k), typically 100mV from the supply rails. With 10 loads, a useful output swing can be achieved and still maintain high open-loop gain. See the typical characteristic Output Voltage Swing vs Output Current.
INPUT AND ESD PROTECTION
All OPA300 pins are static protected with internal ESD protection diodes tied to the supplies, as shown in Figure 2. These diodes will provide overdrive protection if the current is externally limited to 10mA, as stated in the Absolute Maximum Ratings. Any input current beyond the Absolute Maximum Ratings, or long-term operation at maximum ratings, will shorten the lifespan of the amplifier.
Figure 2. ESD Protection Diodes
ENABLE FUNCTION
The shutdown function of the OPA300 is referenced to the negative supply voltage of the operational amplifier. A logic level HIGH enables the op amp. A valid logic HIGH is defined as 2.5V above the negative supply applied to the enable pin. A valid logic LOW is defined as < 0.8V above the negative supply pin. If dual or split power supplies are used, care should be taken to ensure logic input signals are properly referred to the negative supply voltage. If this pin is not connected to a valid high ot low voltage, the internal circuitry will pull the node high and enable the part to function. The logic input is a high-impedance CMOS input. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 10s; disable time is 1s. When disabled, the output assumes a high-impedance state. This allows the OPA300 to be operated as a gated amplifier, or to have its output multiplexed onto a common analog output bus.
Figure 1. OPA300 Classic Two-Stage Topology
OPERATING VOLTAGE
OPA300 op amp parameters are fully specified from +2.7V to +5.5V. Supply voltages higher than 5.5V (absolute maximum) can cause permanent damage to the amplifier. Many specifications apply from -40C to +125C. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics.
10
OPA300
www.ti.com SBOS271 - MAY 2003
DRIVING CAPACITIVE LOADS
When using high-speed operational amplifiers, it is extremely important to consider the effects of capacitive loading on amplifier stability. Capacitive loading will interact with the output impedance of the operational amplifier, and depending on the capacitor value, may significantly decrease the gain bandwidth, as well as introduce peaking. To reduce the effects of capacitive loading and allow for additional capacitive load drive, place a series resistor between the output and the load. This will reduce available bandwidth, but permit stable operation with capacitive loading. Figure 3 illustrates the recommended relationship between the resistor and capacitor values.
DRIVING A 16-BIT ADC
The OPA300 features excellent THD+noise, even at frequencies greater than 1MHz, with a 16-bit settling time of 150ns. Figure 4 shows a total single supply solution for high-speed data acquisition. The OPA300 directly drives the ADS8401, a 1.25 mega sample per second (MSPS) 16-bit data converter. The OPA300 is configured in an inverting gain of 1, with a 5V single supply. Results of the OPA300 performance are summarized in Table 1.
Figure 4. The OPA300 Drives the 16-Bit ADS8401
PARAMETER
RESULTS 99.3dB 101.3dB 107.4dB 103.5dB
Figure 3. Recommended RS and CL Combinations Amplifiers configured in unity gain are most susceptible to stability issues. The typical characteristic, Frequency Response vs Capacitive Load, describes the relationship between capacitive load and stability for the OPA300. In unity gain, the OPA300 is capable of driving a few picofarads of capacitive load without compromising stability. Board level parasitic capacitance can often fall into the range of a picofarad or more, and should be minimized through good circuit-board layout practices to avoid compromising the stability of the OPA300.
THD+Noise SFDR 2nd Harmonic 3rd Harmonic
Table 1. OPA300 Performance Results Driving a 1.25MSPS ADS8401
11
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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