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OPA 269 0
OPA2690
SBOS238B - JUNE 2002 - REVISED JULY 2003
OPA 2690
Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER With Disable
FEATURES
q FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply 2.5V to 6V Dual Supplies q WIDEBAND +5V OPERATION: 220MHz (G = 2) q HIGH OUTPUT CURRENT: 190mA q OUTPUT VOLTAGE SWING: 4.0V q HIGH SLEW RATE: 1800V/s q LOW SUPPLY CURRENT: 5.5mA/ch q LOW DISABLED CURRENT: 100A/ch
DESCRIPTION
The OPA2690 represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full-power bandwidth previously found only in wideband current-feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These give exceptional singlesupply operation. Using a single +5V supply, the OPA2690 can deliver a 1V to 4V output swing with over 120mA drive current and 150MHz bandwidth. This combination of features makes the OPA2690 an ideal RGB line driver or singlesupply Analog-to-Digital Converter (ADC) input driver. The low 5.5mA/ch supply current of the OPA2690 is precisely trimmed at +25C. This trim, along with low temperature drift, ensures lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, will operate the OPA2690I14D normally. If pulled LOW, the OPA2690I-14D supply current drops to less than 200A/ch while the output goes into a high-impedance state.
APPLICATIONS
q q q q q q q VIDEO LINE DRIVING xDSL LINE DRIVER/RECEIVER HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS
+5V +2.5V +2.5V 100pF 0.1F +5V 2k 499 0.1F 499 1k 35 IN 10pF VIN 499 1k 2.5VCM 2Vp-p 35 IN 10pF REFB REFT 100 2k
OPA2690 RELATED PRODUCTS
SINGLES Voltage-Feedback Current-Feedback Fixed Gain OPA690 OPA691 OPA692 DUALS OPA2680 OPA2691 -- TRIPLES OPA3690 OPA3691 OPA3692
1/2 OPA2690
HARMONIC DISTORTION vs FREQUENCY FOR THE SINGLE-SUPPLY ADC DRIVER -50
ADS825
-55
Harmonic Distortion (dBc)
2VPP Differential Output
10-Bit 40MSPS
-60 -65 -70 -75 -80 -85 -90 -95 -100 1 Frequency (MHz) 10 20 2nd-Harmonic 3rd-Harmonic
1/2 OPA2690
+2.5V 499
Clock
Single-Supply Differential ADC Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ............................................................................... 6.5VDC Internal Power Dissipation ....................... See Thermal Analysis Section Differential Input Voltage .................................................................. 1.2V Input Voltage Range ............................................................................ VS Storage Temperature Range: D, 14D ............................ -40C to +125C Lead Temperature (soldering, 10s) .............................................. +300C Junction Temperature (TJ ) ........................................................... +150C ESD Resistance: HBM .................................................................... 2000V CDM .................................................................... 1500V MM ........................................................................ 200V NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING OPA2690 ORDERING NUMBER OPA2690ID OPA2690IDR OPA2690I-14D OPA2690I-14DR TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Rails, 58 Tape and Reel, 2500
PRODUCT OPA2690
PACKAGE-LEAD SO-8
"
OPA2690
"
SO-14
"
D
"
-40C to +85C
"
OPA2690
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View SO Top View SO
-In A +In A
1 2 3 4 5 6 7
14 Out A 13 NC 12 NC 11 +VS 10 NC 9 8 NC Out B
Out A -In A +In A -VS
1 2 3 4 A B
8 7 6 5
+VS Out B -In B +In B
DIS A -VS DIS B +In B -In B
2
OPA2690
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SBOS238B
ELECTRICAL CHARACTERISTICS: VS = 5V
Boldface limits are tested at +25C.
RF = 402, RL = 100, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP MIN/MAX OVER TEMPERATURE +25C(1) 0C to 70C(2) -40C to +85C(2) MIN/ TEST MAX LEVEL(3)
PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth
CONDITIONS
+25C
UNITS
G = +1, VO = 0.5VPP, RF = 25 G = +2, VO = 0.5VPP G = +10, VO = 0.5VPP
500 220 30 300 30 4 200 1800 1.4 2.8 12 8 -68 -77 -70 -81 5.5 3.1 0.06 0.03 -85 69 1.0 +5 0.1 58 56 5.0 12 11 20 1.4 1 3.5 54 5.2 12 12 40 1.6 1.5 3.2 56 -64 -70 -68 -78 -62 -68 -66 -76 -60 -66 -64 -75 1400 1200 900 165 20 200 160 19 190 150 18 180
MHz MHz MHz MHz MHz dB MHz V/s ns ns ns ns dBc dBc dBc dBc nV/Hz pA/Hz % deg dBc dB mV V/C A nA/C A nA/C V dB k || pF M || pF
typ min min min typ typ typ min typ typ typ typ max max max max typ typ typ typ typ min max max max max max max min min typ typ min min min min typ typ
C B B B C C C C C C C C
Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance
G 10 G = +2, VO < 0.5VPP VO < 0.5VPP G = +2, VO = 5VPP G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2VPP RL = 100 RL 500 RL = 100 RL 500 f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2, NTSC, VO = 1.4Vp, RL = 150 f = 5MHz, Input Referred VO = 0V, RL = 100 VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V
B B B C C C C C A A B A B A B A A C C A A A A C C
4.5 10 1.0
3.4
60
3.3 57
VCM = 1V VCM = 0 VCM = 0 No Load 100 Load VO = 0 VO = 0 VO = 0 G = +2, f = 100kHz
68 190 || 0.6 3.2 || 0.9 4.0 3.9 +190 -190 250 0.04
3.8 3.7
+160 -160
3.7 3.6 +140 -140
3.6 3.3 +100 -100
V V mA mA mA
(1) Junction temperature = ambient for +25C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at CMIR limits.
OPA2690
SBOS238B
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3
ELECTRICAL CHARACTERISTICS: VS = 5V (Cont.)
Boldface limits are tested at +25C.
RF = 402, RL = 100, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP MIN/MAX OVER TEMPERATURE +25C(1) 0C to 70C(2) -40C to +85C(2) MIN/ TEST MAX LEVEL(3 )
PARAMETER DISABLE (SO-14 Only) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current (2 Channels) Minimum Quiescent Current (2 Channels) Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specified Operating Range D, 14D Package Thermal Resistance, JA D 14D SO-8 SO-14
CONDITIONS Disabled LOW VDIS = 0, Both Channels VIN = 1VDC VIN = 1VDC G = +2, 5MHz G = +2, RL = 150, VIN = 0 G = +2, RL = 150, VIN = 0
+25C
UNITS A ns ns dB pF mV mV
-200 200 25 70 4 50 20 3.3 1.8
-400
-480
-520
max typ typ typ typ typ typ min max max typ max max min min typ typ typ
A C C C C C C A A A C A A A A C C C
3.5 1.7 130
3.6 1.6 150
3.7 1.5 160
V V A V
VDIS = 0, Each Channel
75 5
6
VS = 5V VS = 5V Input Referred 11 11 75 -40 to +85 Junction-to-Ambient 125 100 11.6 10.6 68
6 12.2 10.2 66
6 12.6 9.4 64
V mA mA dB C C/W C/W
(1) Junction temperature = ambient for +25C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at CMIR limits.
4
OPA2690
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SBOS238B
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25C.
RF = 402, RL = 100 to VS/2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP MIN/MAX OVER TEMPERATURE +25C(1) 0C to 70C(2) -40C to +85C(2) MIN/ TEST MAX LEVEL(3)
PARAMETER AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth
CONDITIONS G = +1, VO < 0.5VPP, RF = 25 G = +2, VO < 0.5VPP G = +10, VO < 0.5VPP G 10 G = +2, VO < 0.5VPP VO < 0.5VPP G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2VPP RL = 100 to VS/2 RL 500 to VS/2 RL = 100 to VS/2 RL 500 to VS/2 f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS/2 G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS/2 VO = 2.5V, RL = 100 to 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V
+25C
UNITS
Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance
400 190 25 250 20 5 220 1000 1.6 2.0 12 8 -65 -75 -68 -77 5.6 3.2 0.06 0.02
150 18 180
145 17 170
140 16 160
700
670
550
MHz MHz MHz MHz MHz dB MHz V/s ns ns ns ns dBc dBc dBc dBc nV/Hz pA/Hz % deg
typ min min min typ typ typ min typ typ typ typ max max max max typ typ typ typ
C B B B C C C B C C C C B B B B C C C C
-60 -70 -64 -73
-59 -68 -62 -71
-56 -66 -60 -70
63 1.0 +5
56
54 4.8 10 11 20
52 5.2 10 12 40 1.6 9 1.8 3.2 54
dB mV V/C A nA/C A nA/C V V dB k || pF M || pF
min max max max max max max max min min typ typ min min max max min min typ typ
A A B A B A B A A A C C A A A A A A C C
4.5 10
0.3
1.0
1.4 7
VCM = 2.5V 0.5V VCM = 2.5V VCM = 2.5V No Load RL = 100 to 2.5V No Load RL = 100 to 2.5V
1.5 3.5 63 92 || 1.4 2.2 || 1.5 4 3.9 1 1.1 +160 -160 250 0.04
1.6 3.4 58
1.7 3.3 56
3.8 3.7 1.2 1.3 +120 -120
3.6 3.5 1.4 1.5 +100 -100
3.5 3.4 1.5 1.7 +80 -80
VO = VS/2 G = +2, f = 100kHz
V V V V mA mA mA
(1) Junction temperature = ambient for +25C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at CMIR limits.
OPA2690
SBOS238B
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5
ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.)
Boldface limits are tested at +25C.
RF = 402, RL = 100 to VS/2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP MIN/MAX OVER TEMPERATURE +25C(1) -400 0C to 70C(2) -480 -40C to +85C(2) -520 MIN/ TEST MAX LEVEL(3) max typ typ typ typ min max typ typ max max min typ typ typ typ A C C C C A A C C B A A C C C C
PARAMETER DISABLE (SO-14 Only) Power-Down Supply Current (+VS) Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) POWER SUPPLY Specified Single-Supply Operating Voltage Maximum Single-Supply Operating Voltage Maximum Quiescent Current (2 Channels) Minimum Quiescent Current (2 Channels) Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, 14D Thermal Resistance, JA D SO-8 14D SO-14
CONDITIONS Disabled LOW VDIS = 0, Both Channels G = +2, 5MHz G = +2, RL = 150, VIN = VS /2 G = +2, RL = 150, VIN = VS /2
+25C -200 65 4 50 20 3.3 1.8 75 5
UNITS A dB pF mV mV V V A V V mA mA dB C C/W C/W
VDIS = 0, Each Channel
3.5 1.7 130
3.6 1.6 150
3.7 1.5 160
VS = +5V VS = +5V Input Referred
9.8 9.8 72 -40 to +85
12 10.4 9.4
12 10.9 8.6
12 11.4 8
Junction-to-Ambient 125 100
(1) Junction temperature = ambient for +25C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at CMIR limits.
6
OPA2690
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SBOS238B
TYPICAL CHARACTERISTICS: VS = 5V
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 1 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE 6 3 VO = 0.5VPP G = +1 RF = 25
LARGE-SIGNAL FREQUENCY RESPONSE 9
Normalized Gain (3dB/div)
6
0 -3 -6 G = 10 -9 -12 -15 0.7 10 Frequency (MHz) 100 700 G=5
Gain (3dB/div)
G=2
VO = 2VPP 3 VO = 1VPP 0 VO = 4VPP -3 VO = 7VPP -6 0.5 1 10 Frequency (MHz) 100 500
SMALL-SIGNAL PULSE RESPONSE 400 300 +4 G = +2 VO = 0.5VPP +3
LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 5VPP
Output Voltage (100mV/div)
Output Voltage (1V/div)
Time (5ns/div)
200 100 0 -100 -200 -300 -400
+2 +1 0 -1 -2 -3 -4 Time (5ns/div)
COMPOSITE VIDEO dG/dP 0.200 0.175 0.150
dG/dP (%/degree)
Video In 75 1/2 OPA2690 402 402 Optional 1.3k Pull-Down +5V
CHANNEL-TO-CHANNEL CROSSTALK -55 -60 -65
dG
Crosstalk (5dB/div)
No Pull-Down With 1.3k Pull-Down
0.125 0.100 0.075 0.050 0.025 0 1
-70 -75 -80 -85 -90 -95 -100 Input Referred 1 10 Frequency (MHz) 100
dG
-5V
dP
dP
2
3
4
Number of 150 Loads
OPA2690
SBOS238B
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7
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE -60 -65 -70 2nd-Harmonic -75 3rd-Harmonic -80 -85 -90 100 Resistance () 1000 VO = 2VPP f = 5MHz
-60
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE VO = 2VPP RL = 100 f = 5MHz -65
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
2nd-Harmonic
-70
3rd-Harmonic
-75
-80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply Voltage (VS)
HARMONIC DISTORTION vs FREQUENCY -40 -50 -60 2nd-Harmonic -70 -80 3rd-Harmonic -90 -100 0.1 1 Frequency (MHz) 10 20 VO = 2VPP RL = 100 -60
HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 100 f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
2nd-Harmonic -65
-70 3rd-Harmonic -75
-80 0.1 1 Output Voltage Swing (Vp-p) 5
HARMONIC DISTORTION vs NONINVERTING GAIN -40 VO = 2VPP RL = 100 f = 5MHz -40
HARMONIC DISTORTION vs INVERTING GAIN VO = 2VPP RL = 100 f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-50
-60 2nd-Harmonic 3rd-Harmonic -70
-60
2nd-Harmonic 3rd-Harmonic
-70
-80
-90 1 Noninverting Gain (V/V) 10 20
-80 1 Inverting Gain (V/V) 10 20
8
OPA2690
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SBOS238B
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 1 for AC performance only), unless otherwise noted.
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 -35 -40 -45 -50 -55 -60 -65
INPUT VOLTAGE AND CURRENT NOISE DENSITY 100
3rd-Order Spurious Level (dBc)
50MHz
Voltage Noise (nV/Hz) Current Noise (pA/Hz)
10 Voltage Noise 5.5nV/Hz
20MHz
Current Noise 3.1pA/Hz
10MHz
-70 -75 -8 -6 -4 -2
1 100 1k 10k 100k 1M 10M Frequency (Hz)
Load Power at Matched 50 Load, see Figure 1 0 2 4 6 8 10
Single-Tone Load Power (dBm)
RECOMMENDED RS vs CAPACITIVE LOAD 80
Gain-to-Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 G = +2
70 60 50
RS ()
CL = 10pF
6
CL = 100pF
3
CL = 22pF
0
40 30 20 10 0 10 100 Capacitive Load (pF) 1000
CL = 47pF
-3 -6 -9 0 20 40 60 80 100 120 140 160 180 200 Frequency (20MHz/div)
VIN 1/2 OPA2690 402 RS VOUT CL 1k
402
1k is optional.
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
VDIS (2V/div)
DISABLE FEEDTHROUGH vs FREQUENCY
6 VDIS 4 2 0 2.0 1.6 1.2 0.8 0.4 0 G = +2 VIN = +1V Output Voltage
Each Channel SO-14 Package Only
-45 -50 -55
Feedthrough (5dB/div)
VDIS = 0
-60 -65 -70 -75 -80 -85 -90 -95 -100 100k Forward 1M Frequency (Hz) 10M 100M Reverse
Output Voltage (0.4V/div)
Time (50ns/div)
OPA2690
SBOS238B
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9
TYPICAL CHARACTERISTICS: VS = 5V (Cont.)
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 1 for AC performance only), unless otherwise noted.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 3 2 1 1W Internal Power Limit One Channel Only Output Current Limited
2 1.5
TYPICAL DC DRIFT OVER TEMPERATURE 20
Input Offset Voltage (mV)
1 0.5 0 -0.5 -1
Input Bias Current (IB)
10
VO (V)
Input Offset Current (IOS)
0
0 -1 -2 -3 -4 Output Current Limit -200 -100 0 IO (mA) 100
25 Load Line 50 Load Line 100 Load Line 1W Internal Power Limit 200 300
-10
Input Offset Voltage (VOS)
-1.5 -2 -50 -25 0 25 50 75 100 125 Ambient Temperature (C) -20
-5 -300
COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY 100 90 80 70
PSRR (dB) CMRR (dB)
14
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 250
-PSRR CMRR
Supply Current (2mA/div)
12
Sourcing Output Current
Sinking Output Current
10 150
60 50 40 30 20 10 0 10k 100k 1M Frequency (MHz) 10M 100M +PSRR
Quiescent Supply Current
8 100
6
50
4 -50 -25 0 25 50 75 100 Ambient Temperature (C)
0 125
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10
+5V
OPEN-LOOP GAIN AND PHASE 70 60 Open-Loop Gain
Open-Loop Gain (dB)
0 -30 Open-Loop Phase
Open-Loop Phase ()
Output Impedance ()
1/2 200 OPA2690
50 40 30 20 10 0 -10
-60 -90 -120 -150 -180 -210 -240 1k 10k 100k 1M 10M 100M -270 1G
1
-5V 402 402
ZO
0.1
0.01 10k 100k 1M Frequency (Hz) 10M 100M
-20 Frequency (MHz)
10
OPA2690
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SBOS238B
Output Current (50mA/div)
200
Input Bias and Offset Currents (A)
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 2 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.5VPP G = +1 RF = 25 6 9
LARGE-SIGNAL FREQUENCY RESPONSE VO = 2VPP
Normalized Gain (3dB/div)
3
0 G = +5 -3 G = +10 -6
Gain (3dB/div)
G = +2
3
VO = 3VPP VO = 1VPP
0
-3
-9 0.7 1 10 Frequency (Hz) 100 700
-6 0.5 1 10 Frequency (MHz) 100 500
SMALL-SIGNAL PULSE RESPONSE 2.9 4.1 G = +2 VO = 0.5VPP
LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 2VPP
Output Voltage (100mV/div)
2.7 2.6 2.5 2.4 2.3 2.2 2.1 Time (5ns/div)
Output Voltage (400mV/div)
2.8
3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD 50 45 40 35
RS () Gain-to-Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD 9
CL = 10pF
6
CL = 100pF
3 0
+5V 0.1F 58 714 714 714 OPA2690 402 +5V 402
1/2
30 25 20 15 10 5 0 1 10 100 1000 Capacitive Load (pF)
CL = 22pF
RS V OUT CL
-3 -6 -9
VIN
CL = 47pF
0
20
40
60
80
100 120
140 160
180 200
Frequency (20MHz/div)
OPA2690
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TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25C, G = +2, RF = 402, and RL = 100 (see Figure 2 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE -60 VO = 2VPP f = 5MHz
Harmonic Distortion (dBc)
-40 -50 -60
HARMONIC DISTORTION vs FREQUENCY VO = 2VPP RL = 100 to 2.5V
-65
Harmonic Distortion (dBc)
2nd-Harmonic -70 -80 3rd-Harmonic -90 -100
-70 3rd-Harmonic -75
2nd-Harmonic
-80 100 Resistance () 1000
0.1
1 Frequency (MHz)
10
20
HARMONIC DISTORTION vs OUTPUT VOLTAGE -60
3rd-Order Spurious Level (dBc)
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 -35 -40 -45 -50
RL = 100 to 2.5V f = 5MHz
Harmonic Distortion (dBc)
50MHz
-65
3rd-Harmonic
-70 2nd-Harmonic -75
20MHz
-55 -60 -65 -70 -75 Load Power at Matched 50 Load, see Figure 2 -14 -12 -10 -8 -6 -4 -2 0 2
10MHz
-80 0.1 1 Output Voltage Swing (VPP) 3
Single-Tone Load Power (dBm)
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APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
The OPA2690 provides an exceptional combination of high output power capability in a dual, wideband, unity-gain stable, voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage-feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA2690 uses a new input stage that places the transconductance element between two input buffers, using their output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This provides very high slew rate (1800V/s) while consuming relatively low quiescent current (5.5mA/ch). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 5.5nV/Hz input voltage noise for the OPA2690 is exceptionally low for this type of input stage. Figure 1 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the 5V Electrical and Typical Characteristics. This is for one channel; the other channel is connected similarly. For test purposes, the input impedance is set to 50 with a resistor to ground and the output impedance is set to 50 with a series output resistor. Voltage swings reported in the electrical characteristics are taken directly at the input and output pins, whereas output powers (dBm) are at the matched 50 load. For the circuit of Figure 1, the total effective load will be 100 || 804. The disable control line (SO-14 package only) is typically left open for normal amplifier operation. Two optional components are included in Figure 1. An additional resistor (175) is included in series with the noninverting input. Combined with the 25
+5V +VS 0.1F 6.8F +
DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200 source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1F capacitor is included between the two powersupply pins. In practical PC board layouts, this optional-added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA2690 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with > 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698 resistors). Separate bias networks would be required at each input. The input signal is then AC-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (59) used for testing is adjusted to give a 50 input load when the parallel combination of the biasing divider network is included. Again, an additional resistor (50 in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the DC source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies (> 500MHz) using the input parasitic capacitance. The gain resistor (RG) is
+5V +VS
0.1F
50 Source 175 VD 50 DIS
+
6.8F
698
50 50 Load
VI
1/2 OPA2690
VO
0.1F VI 59
50 VD 698
DIS
1/2 OPA2690
RF 402
VO
100 VS/2
0.1F
RF 402
RG 402 + 6.8F 0.1F
RG 402 0.1F
-VS -5V
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification and Test Circuit.
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AC-coupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) on the output as well. The output voltage can swing to within 1V of either supply pin while delivering > 100mA output current. A demanding 100 load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA2690 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the +5V supply harmonic distortion plots.
70 68 66 64
VO = 2VPP, 10MHz
SFDR (dBc)
62 60 58 56 54
SINGLE-SUPPLY ADC INTERFACE
Most modern, high-performance ADCs (such as the ADS8xx and ADS9xx series from Texas Instruments) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA2690 make it an ideal single-supply ADC driver. The circuit on the front page shows one possible interface particularly suited to differential I/O, AC-coupled requirements. Figure 3 shows the AC-coupled test circuit of Figure 2 modified for a capacitive (ADC) load and with an optional output pull-down resistor (RB). This circuit would be suitable to dual-channel ADC driving with a single-ended I/O. The OPA2690 in the circuit of Figure 3 provides > 200MHz bandwidth for a 2VPP output swing. Minimal 3rd-harmonic distortion or 2-tone, 3rd-order intermodulation distortion will be observed due to the very low crossover distortion in the OPA2690 output stage. The limit of output Spurious-Free Dynamic Range (SFDR) will be set by the 2nd-harmonic distortion. Without RB, the circuit of Figure 3 measured at 10MHz shows an SFDR of 57dBc. This can be improved by pulling additional DC bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5V for Figure 3). Adjusting IB gives the improvement in
+5V
52 50 0 1 2 3 4 5 6 7 8 9 10 Output Pull-Down Current (mA)
FIGURE 4. SFDR vs IB. SFDR shown in Figure 4. SFDR improvement is achieved for IB values up to 5mA, with worse performance for higher values. Using the dual OPA2690 in an I/Q receiver channel will give matched AC performance through high frequencies.
HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER
High-frequency DDS Digital-to-Analog Converters (DACs) require a low distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 5 for a differential output drive implementation. The diagram shows the signal output current(s) connected into the virtual ground summing junction(s) of the OPA2690, which is set up as a transimpedance stage or I-V converter. If the DAC requires its outputs terminated to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting inputs of the OPA2690. The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD in Figure 5) will produce a zero
698 0.1F VI 1VPP 59 698 50
Power-supply decoupling not shown. RS 30
1/2 OPA2690
2.5V DC 1V AC 50pF ADC Input
402
402 0.1F
RB
IB
FIGURE 3. Single-Supply ADC Input Driver. One of two channels.
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WIDEBAND VIDEO MULTIPLEXING
50
1/2 OPA2690 High-Speed DAC
RF1 CF1 IO CD1 RF2
V O = IO R F
One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OP2690I-14D (SO-14 package only), as shown in Figure 6. Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The make-before-break disable characteristic of the OPA2690 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 6. As both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5 in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75 output impedance to the cable. The video multiplexer connection (as shown in Figure 6) also ensures that the maximum differential voltage across the inputs of the unselected channel does not exceed the rated 1.2V maximum for standard video signal levels. See the Disable Operation section for the turn-on and turnoff switching glitches using a 0V input for a single channel is typically less than 50mV. Where two outputs are switched (as shown in Figure 6), the output line is always under the control of one amplifier or the other due to the make-beforebreak disable timing. In this case, the switching glitches for two 0V inputs drops to < 20mV.
CF2 IO CD2
1/2 OPA2690
50
V O = IO R F
GBP Gain Bandwidth Product (Hz) for the OPA2690
FIGURE 5. High-Speed DAC--Differential Transimpedance Amplifier. in the noise gain for the OPA2690 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to:
1/ 2RF CF = GBP / 4 RF CD
which will give a cutoff frequency f-3dB of approximately:
(1)
f -3dB = GBP / 2RF CD
(2)
+5V 2k VDIS +5V 146
Video 1
1/2 OPA2690
75
DISA
340
-5V
82.5 402 75 Cable
340 +5V
402
RG-59 75 Load 82.5
Video 2
146
1/2 OPA2690
DISB
75 -5V 2k
FIGURE 6. 2-Channel Video Multiplexer (SO-14 package only).
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HIGH-SPEED DELAY CIRCUIT
The OPA2690 makes an ideal amplifier for a variety of active filter designs. Shown in Figure 7 is a circuit that uses the two amplifiers within the dual OPA2690 to design a 2-stage analog delay circuit. For simplicity, the circuit uses a dualsupply (5V) operation, but it can also be modified to operate on a signal supply. The input to the first filter stage is driven by the OPA692 wideband buffer amplifier to isolate the signal input from the filter network. Each of the two filter stages is a 1st-order filter with a voltage gain of +1. The delay time through one filter is given by Equation 3. tGR0 = 2RC (3) For a more accurate analysis of the circuit, consider the group delay for the amplifiers. For example, in the case of the OPA2690, the group delay in the bandwidth from 1MHz to 100MHz is approximately 1.0ns. To account for this, modify the transfer function, which now comes out to be: tGR = 2 (2RC + TD) (4) with TD = (1/360) * (d/df) = delay of the op amp itself. The values of resistors RF and RG should be equal and low to avoid parasitic effects. If the all-pass filter is designed for
very low delay times, include parasitic board capacitances to calculate the correct delay time. Simulating this application using the PSPICE model of the OPA2690 will allow this design to be tuned to the desired performance.
DIFFERENTIAL RECEIVER/DRIVER
A very versatile application for a dual operational amplifier is the differential amplifier configuration shown in Figure 8. With both amplifiers of the OPA2690 connected for noninverting operation, the circuit provides a high input impedance whereas the gain can easily be set by just one resistor, RG. When operated in low gains, the output swing may be limited as a result of the common-mode input swing limits of the amplifier itself. An interesting modification of this circuit is to place a capacitor in series with the RG. Now the DC gain for each side is reduced to +1, whereas the AC gain still follows the standard transfer function of G = 1 + 2RF/RG. This might be advantageous for applications processing only a frequency band that excludes DC or very low frequencies. An input DC voltage resulting from input bias currents is not amplified by the AC gain and can be kept low. This circuit can be used as a differential line receiver, driver, or as an interface to a differential input ADC.
C VIN OPA692 R R RG 402 RF 402 1/2 OPA2690 C 1/2 OPA2690 VOUT
RG 402
RF 402
FIGURE 7. 2-Stage, All-Pass Network.
50 VI
1/2 OPA2690
RF 402
RO
RG
RF 402
VDIFF = 1 +
2RF RG
VI - VI
50 VI
1/2 OPA2690
RO
FIGURE 8. High-Speed Differential Receiver.
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SINGLE-SUPPLY MFB DIFFERENTIAL ACTIVE FILTER: 10MHz BUTTERWORTH CONFIGURATION
The active filter circuit shown in Figure 9 can be easily implemented using the OPA2690. In this configuration, each amplifier of the OPA2690 operates as an integrator. For this reason, this type of application is also called infinite gain filter implementation. A Butterworth filter can be implemented using the following component ratios.
1 0 -1 -2
Gain (dB)
-3 -4 -5 -6
1 (cutoff frequency) 2* *R*C R1 = R2 = 0.65 * R O = R3 = 0.375 * R C1 = C C2 = 2 * C
+12V 6k
-7 -8 -9 0.1 1 Frequency (MHz) 10 20
FIGURE 10. Multiple Feedback Filter Frequency Response. The circuit shown on the front page has a 195MHz, -3dB bandwidth that can be easily bandlimited by using a capacitor in parallel with the feedback resistors. Refer to Figure 11 for more details. The -3dB frequency is given by Equation 5.
f -3dB = 1 2RF CF
VCM
50 1/2 OPA2690
1000pF R1A 102
6k R3A 60 R2A 102 C1A 100pF
(5)
9 6
Differential Gain (dB)
VIN
C2 200pF
R2B 102 R3B 60 C1B 100pF
VOUT
3 0 -3 -6 -9 -12 0.1 1 10 Frequency (MHz) 100 500 CF = 8.6pF
R1B 102
50 VCM
1/2 OPA2690
FIGURE 9. Single-Supply, MFB Active Filter. 10MHz LP Butterworth. The frequency response for a 10MHz Butterworth filter is shown in Figure 10. One advantage for using this type of filter is the independent setting of WO and Q. Q can be easily adjusted by changing the R3A, B resistors without affecting WO.
FIGURE 11. Single-Supply Differential ADC Driver. For example, CF = 8.6pF in parallel with RF = 402 will control the -3dB frequency to 18MHz.
SINGLE-SUPPLY DIFFERENTIAL ADC DRIVER
The single-supply differential ADC driver shown on the front page is ideal for driving high-frequency ADCs. As shown in the plot on the front page, "Harmonic Distortion vs Frequency for the Single-Supply Differential ADC Driver," the 2ndharmonic reacts as expected and drops to a -95dBc at 1MHz and -87dBc at 5MHz--a significant improvement in going to differential from single-ended.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA2690 in its two package styles. All of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown below:
BOARD PART NUMBER DEM-OPA268xU DEM-OPA268xN
PRODUCT OPA2690ID OPA2690I-14D
PACKAGE SO-8 SO-14
ORDERING NUMBER SBOU003 SBOU002
Consult the Texas Instruments web site (www.ti.com) to request any of these boards.
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MACROMODELS
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2690 (use two OPA690 SPICE models) is available through the Texas Instruments Internet web page (http://www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance.
OPA2690 is compensated to give a slightly peaked response in a noninverting gain of 2 (see Figure 1). This results in a typical gain of +2 bandwidth of 220MHz, far exceeding that predicted by dividing the 300MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 300MHz. The frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the +2 signal gain, is to add an 804 resistor across the two inputs in the circuit of Figure 1. A similar technique may be used to reduce peaking in unity gain (voltage follower) applications. For example, by using a 402 feedback resistor along with a 402 resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of Figure 2. Reducing the value of the resistor across the op amp inputs will further limit the frequency response due to increased noise gain. The OPA2690 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared with 5V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
As the OPA2690 is a unity-gain stable voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unitygain follower application, the feedback connection should be made with a 25 resistor, not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200 and 1.5k. Below 200, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA2690. Above 1.5k, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor can cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of R F and RG (see Figure 1) to be less than approximately 300. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300 will keep this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several k at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.
INVERTING AMPLIFIER OPERATION
As the OPA2690 is a general-purpose, wideband voltagefeedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 12 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration.
+5V
+ 0.1F 0.1F RO 50 50 Load 6.8F
BANDWIDTH vs GAIN: NONINVERTING OPERATION
Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the electrical characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90, as it does in high gain configurations. At low gains (increased feedback factor), most amplifiers will exhibit a more complex response with lower phase margin. The
50 Source VI RM 67
RB 146
1/2 OPA2690
VO
RG 200
RF 402
VO = -2 VI
0.1F
+
6.8F
-5V
FIGURE 12. Gain of -2 Example Circuit.
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In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductor), RG can be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of -2, setting RG to 50 for input matching eliminates the need for RM but requires a 100 feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50 source impedance--the same as the noninverting circuits considered in the previous section. The amplifier output, however, will now see the 100 feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200 to 1.5k range. In this case, it is preferable to increase both the RF and RG values (see Figure 8), and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 12, the RM value combines in parallel with the external 50 source impedance, yielding an effective driving impedance of 50 || 67 = 28.6. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.8 for Figure 12, as opposed to only 2 if RM could be eliminated as discussed above. The bandwidth will, therefore, be slightly lower for the gain of -2 circuit of Figure 12 than for the gain of +2 circuit of Figure 1. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to (Input Offset Current) * RF. If the 50 source impedance is DC-coupled in Figure 10, the total resistance to ground on the inverting input will be 228. Combining this in parallel with the feedback resistor gives the RB = 146 used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350, the capacitor is not required because the total noise contribution of all other terms will be less than that of the op amp input noise voltage. As a minimum, the OPA2690 requires an RB value of 50 to damp out parasitic-induced peaking--a direct short to ground on the noninverting input runs the risk of a very high frequency instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
The OPA2690 provides exceptional output voltage and current capabilities in a low-cost monolithic op amp. Under noload conditions at +25C, the output voltage typically swings closer than 1V to either supply rail; the specified swing limit is within 1.2V of either rail. Into a 15 load (the minimum tested load), it will deliver more than 160mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage * current, or V-I product, which is more relevant to circuit operation. Refer to the "Output Voltage and Current Limitations" plot in the Typical Characteristics. The X- and Y-axes of this graph shows the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2690 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation for each channel separately. Superimposing resistor load lines onto the plot shows that the OPA2690 can drive 2.5V into 25 or 3.5V into 50 without exceeding the output capabilities or the 1W dissipation limit. A 100 load line (the standard test circuit load) shows the full 3.9V output swing capability (see the Electrical Characteristics). The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold start-up will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the over-temperature specifications because the output stage junction temperatures is higher than the minimum specified operating ambient. To protect the output stage from accidental shorts to ground and the power supplies, output short-circuit protection is included in the OPA2690. This circuit acts to limit the maximum source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC--including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA2690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the open-loop output resistance of the amplifier is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external
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solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2690. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2690 output pin (see the Board Layout Guidelines section). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA2690 operating in a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will reduce the peaking as described previously. The circuit of Figure 13 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load.
margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA2690 operated at higher signal gains without RNG.
100 90 80 70
RS ()
NG = 2
60 50 40 30 20 10 0 1 10 100 1000 Capacitive Load (pF) NG = 3 NG = 4
FIGURE 14. Required RS vs Noise Gain.
DISTORTION PERFORMANCE
The OPA2690 provides good distortion performance into a 100 load on 5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 1) this is the sum of RF + RG, whereas in the inverting configuration it is just RF. Also, providing an additional supply-decoupling capacitor (0.1F) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). Operating differentially also lowers 2nd-harmonic distortion terms (see the plot on the front page). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The new output stage used in the OPA2690 actually holds the difference between fundamental power and the 2nd- and 3rd-harmonic powers relatively constant with increasing output power until very large output swings are required (> 4VPP). This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with 10dBm/tone into a matched 50 load (i.e., 2VPP for each tone at the load, which requires 8VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show 46dBc difference
+5V 50 175 Power-supply decoupling not shown. 1/2 OPA2690 R VO CLOAD
50
RNG
402
402 -5V
FIGURE 13. Capacitive Load Driving with Noise Gain Tuning. This gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique will reduce the required RS resistor for a given capacitive load, it does increase the noise at the output. It also will decrease the loop gain, nominally decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 14 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 13 with RNG adjusted to increase the noise gain (increasing the phase
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between the test tone powers and the 3rd-order intermodulation spurious powers. This exceptional performance improves further when operating at lower frequencies or powers.
flatness considerations. As the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 12 is not required.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 5.5nV/Hz input voltage noise for the OPA2690 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 15 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/Hz or pA/Hz.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide variety of applications. The power-supply current trim for the OPA2690 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically 5A out of each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, and using worstcase +25C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: (NG * VOS(MAX)) (RF * IOS(MAX)) = (2 * 4.5mV) (402 * 1A)
ENI 1/2 OPA2690 IBN
RS
EO
ERS 4kTRS RF 4kTRF 4kT = 1.6E - 20J at 290K
= 9.4mV - (NG = noninverting signal gain) A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input can be considered. However, the DC offset voltage on the summing junction sets up a DC current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, see Figure 16 for one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This ensures that the adjustment circuit has minimal effect on the loop gain and hence, the frequency response.
4kT RG
RG
IBI
FIGURE 15. Op Amp Noise Analysis Model. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 6 shows the general form for the output noise voltage using the terms shown in Figure 15.
2 2 EO = ENI2 + (IBN RS ) + 4kTRS NG2 + (IBI RF ) + 4kTRF NG (6)
Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 7.
4kTRF 2 I R EN = ENI2 + (IBN RS ) + 4kTRS + BI F + (7) NG NG
2
Evaluating these two equations for the OPA2690 circuit and component values, see Figure 1, gives a total output spot noise voltage of 12.3nV/Hz and a total equivalent input spot noise voltage of 6.1nV/Hz. This is including the noise added by the bias current cancellation resistor (175) on the noninverting input. This total input-referred spot noise voltage is only slightly higher than the 5.5nV/Hz specification for the op amp voltage noise alone. This is the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300. Keeping both (RF || RG) and the noninverting input source impedance less than 300 will satisfy both noise and frequency response
DISABLE OPERATION (SO-14 Package Only)
The OPA2690I-14D provides an optional disable feature that can be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2690I-14D will operate normally. To disable, the control pin must be asserted LOW. See Figure 17 for a simplified internal circuit for the disable control feature.
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+5V Power-supply decoupling not shown.
0.1F
328
1/2 OPA2690
VO
impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 18 shows these glitches for the circuit of Figure 1 with the input signal at 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage.
-5V +5V VI 20k 10k 0.1F 5k VO VI -5V RF RG 200mV Output Adjustment RG 500 5k RF 1k
VDIS
4 2 0
=-
= -2
Output Voltage (10mV/div)
30 20 10 0 -10 -20 -30
Output Voltage VO = 0
FIGURE 16. DC-Coupled, Inverting Gain of -2, with Offset Adjustment.
+VS
Time (20ns/div)
FIGURE 18. Disable/Enable Glitch.
15k
Q1
25k VDIS IS Control
110k
-VS
The transition edge rate (dv/dt) of the DIS control line influences this glitch. For the plot of Figure 18, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate can be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2k series resistor between the logic gate and the DIS input pin provides adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing.
FIGURE 17. Simplified Disable Control Circuit.
THERMAL ANALYSIS
In normal operation, base current to Q1 is provided through the 110k resistor, while the emitter current through the 15k resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1's emitter. As VDIS is pulled LOW, additional current is pulled through the 15k resistor eventually turning on those two diodes (100A). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 16. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a highimpedance state. If the OPA2690 is operating in a gain of +1, this will show a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the Due to the high output power capability of the OPA2690, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described following. In no case should the maximum junction temperature be allowed to exceed 150C. Operating junction temperature (TJ) is given by TA + PD * JA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 * RL), where RL includes feedback network loading.
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VDIS (2V/div)
6
Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2690ID (SO-8 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85C and with both outputs driving a grounded 20 load to +2.5V. PD = 10V * 12.6mA + 2 [52/(4 * (20 || 804))] = 766mW Maximum TJ = +85C + (0.766W * 125C/W) = 180C. This absolute worst-case condition exceeds the specified maximum junction temperature. Actual PDL is normally less than that considered here. Carefully consider maximum TJ in your application.
shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5k, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402 feedback used in the Electrical Characteristics is a good starting point for design. Note that a 25 feedback resistor, rather than a direct short, is suggested for the unity-gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause additional peaking in the gain of +1 frequency response. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of "Recommended RS vs Capacitive Load." Low parasitic capacitive loads (< 3pF) may not need an RS because the OPA2690 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin, see Figure 14). If a long trace is required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50 environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2690 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2690 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of "Recommended RS vs Capacitive Load." This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA2690 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high frequency 0.1F decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1F) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2F to 6.8F) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA2690. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance
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e) Socketing a high-speed part like the OPA2690 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2690 onto the board.
+V CC
External Pin
Internal Circuitry
-V CC
INPUT AND ESD PROTECTION
The OPA2690 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 19.
FIGURE 19. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with 15V supply parts driving into the OPA2690), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
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PACKAGE DRAWING
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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