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| QUAD 2-PORT REGISTER The SN54 / 74LS398 and SN54 / 74LS399 are Quad 2-Port Registers. They are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources). The selected data is transferred to the output register on the LOW-to-HIGH transition of the Clock input. The SN54/ 74LS398 features both Q and Q inputs, while the SN54 / 74LS399 has only Q outputs. SN54/74LS398 SN54/74LS399 QUAD 2-PORT REGISTER LOW POWER SCHOTTKY * * * * Select From Two Data Sources Fully Positive Edge-Triggered Operation Both True and Complemented Outputs on SN54 / 74LS398 Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Qd 20 19 Qd 18 Iod 17 I1d 16 I1c 15 I0c 14 Qc 13 Qc 12 CP 11 16 J SUFFIX CERAMIC CASE 620-09 1 SN54 / 74LS398 N SUFFIX PLASTIC CASE 648-08 1 1 S 2 Qa 3 Qa 4 I0a 5 I1a 6 I1b 7 I0b 8 Qb 9 Qb 10 GND 16 VCC = PIN 20 GND = PIN 10 VCC 16 Qd 15 I0d 14 I1d 13 I1c 12 I0c 11 Qc 10 CP 9 16 1 D SUFFIX SOIC CASE 751B-03 SN54 / 74LS399 20 J SUFFIX CERAMIC CASE 732-03 1 1 S 2 Qa 3 I0a 4 I1a 5 I1b 6 I0b 7 Qb 8 GND VCC = PIN 16 GND = PIN 8 PIN NAMES LOADING (Note a) HIGH S CP I0a - I0d I1a - I0d Qa - Qd Qa - Q d Common Select Input Clock (Active HIGH Going Edge) Input Data Inputs From Source 0 Data Inputs From Source 1 Register True Outputs (Note b) Register Complementary Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXDW SN74LSXXXD Ceramic Plastic SOIC SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. FAST AND LS TTL DATA 5-1 SN54/74LS398 * SN54/74LS399 FUNCTIONAL BLOCK DIAGRAM IOA S IIA R IOB S IIB R IOC S IIC R IOD S IID R * SN54 / 74LS398 only *Q D QD * QC *Q B QC *Q A QB S QA FUNCTIONAL DESCRIPTION The SN54 / 74LS398 and SN54 / 74LS399 are high-speed Quad 2-Port Registers. They select four bits of data from two sources (Ports) under the control of a common Select Input (S). The selected data is transferred to a 4-Bit Output Register synchronous with the LOW-to-HIGH transition of the Clock in- put (CP). The 4-Bit RS type output register is fully edge-triggered. The Data inputs (I) and Select inputs (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The SN54 / 74LS398 has both Q and Q Outputs available. FUNCTION TABLE INPUTS S I I h h I0 I h X X I1 X X I h Q L H L H OUTPUTS Q* H L H L *SN54 / 74LS398 only I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial FAST AND LS TTL DATA 5-2 SN54/74LS398 * SN54/74LS399 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 13 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tPLH tPHL Parameter P Propagation Delay, Clock to Output Q Min Typ 18 21 Max 27 32 Unit Ui ns Test C di i T Conditions VCC = 5.0 V CL = 15 pF FAST AND LS TTL DATA 5-3 SN54/74LS398 * SN54/74LS399 AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol S bl tW ts ts th Parameter P Clock Pulse Width Data Setup Time Select Setup Time Hold Time, Any Input Min 20 25 45 0 Typ Max Unit Ui ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions DEFINITIONS OF TERMS SETUP TIME(ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME(th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative Hold Time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. AC WAVEFORMS I0 I1 * ts(L) CP 1.3 V 1.3 V th(L) ts(H) tW(H) 1.3 V th(H) S* ts(L) 1.3 V CP 1.3 V th(L) = 0 1.3 V ts(H) 1.3 V th(H) = 0 1.3 V tW(L) tPHL Q 1.3 V tPLH 1.3 V Q or Q 1.3 V Q = I0 1.3 V Q = I1 Figure 1 Figure 2 CP 1.3 V tPHL 1.3 V Q 1.3 V 1.3 V tPLH Q 1.3 V tPLH 1.3 V tPHL Figure 3 *The shaded areas indicate when the input is permitted to change for predictable output performance. FAST AND LS TTL DATA 5-4 |
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