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| SN54/74LS375 4-BIT D LATCH The SN54 / 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 D3 15 Q3 14 Q3 13 E2,3 12 Q2 11 Q2 10 D2 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. J SUFFIX CERAMIC CASE 620-09 16 1 1 D0 2 Q0 3 Q0 4 E0,1 5 Q1 6 Q1 7 D1 8 GND 16 N SUFFIX PLASTIC CASE 648-08 1 TRUTH TABLE (Each latch) tn D H L PIN NAMES tn+1 Q H L NOTES: tn = bit time before enable g gg negative-going transition. tn+1 = bit time after enable negative-going transition. 16 1 D SUFFIX SOIC CASE 751B-03 LOADING (Note a) HIGH LOW 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC D1 - D4 E0 - 1 E2 - 3 Q1 - Q4 Q1 - Q4 Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC SYMBOL 1 D0 7 D1 9 D2 15 D3 LOGIC DIAGRAM DATA ENABLE TO OTHER LATCH Q Q 4 12 E0,1 E2,3 Q0 2 3 Q1 6 5 Q2 10 11 Q3 14 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS375 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 D Input E Input IIH Input HIGH Current D Input E Input Input LOW Current D Input E Input - 20 0.1 0.4 - 0.4 - 1.6 - 100 12 mA mA mA mA VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX 0.35 0.5 20 80 V A 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIL IOS ICC Short Circuit Current (Note 1) Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter P Propagation Delay, Data to Q Propagation Delay, Data to Q Propagation Delay, Enable to Q Propagation Delay, Enable to Q Min Typ 15 9.0 12 7.0 15 14 16 7.0 Max 27 17 20 15 27 25 30 15 Unit Ui ns ns ns ns Test C di i T Conditions VCC = 5.0 V 50 CL = 15 pF FAST AND LS TTL DATA 5-2 SN54/74LS375 LOGIC DIAGRAM DATA ENABLE TO OTHER LATCH Q (SN54LS/74LS375 ONLY) Q GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits S bl Symbol tW ts th P Parameter Enable Pulse Width Setup Time Hold Time Min 20 20 0 Typ Max Ui Unit ns ns ns VCC = 5.0 V 50 T Test C di i Conditions AC WAVEFORMS D 1.3 V ts 1.3 V th 1.3 V 1.3 V E 1.3 V tPLH Q tPLH 1.3 V tPHL tPHL 1.3 V Q tPHL tPHL 1.3 V tPLH tPLH 1.3 V DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. FAST AND LS TTL DATA 5-3 |
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