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| SN54/74LS253 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL / MSI SN54 / 74LS253 is a Dual 4-Input Multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY * * * * Schottky Process for High Speed Multifunction Capability Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects 16 J SUFFIX CERAMIC CASE 620-09 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0b 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 N SUFFIX PLASTIC CASE 648-08 1 E0a 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC S0, S1 Multiplexer A E0a I0a - I3a Za Multiplexer B E0b I0b - I3b Zb Common Select Inputs Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. LOGIC SYMBOL 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. 14 2 1 654 3 10 11 12 13 15 NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges. EIIII IIIIE S0 0a 0a 1a 2a 3a 0b 1b 2b 3b 0b S1 Za Zb 7 VCC = PIN 16 GND = PIN 8 9 FAST AND LS TTL DATA 5-1 SN54/74LS253 LOGIC DIAGRAM E0b 15 I3b 13 I2b 12 I1b 11 I0b 10 S0 14 S1 2 I3a 3 I2a 4 I1a 5 I0a 6 E0a 1 Zb 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Za 7 FUNCTIONAL DESCRIPTION The LS253 contains two identical 4-Input Multiplexers with 3-state outputs. They select two bits from four sources selected by common select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (E0a, E0b) inputs which when HIGH, forces the outputs to a high impedance (high Z) state. The LS253 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below: Za = E0a (I0a S1 S0 + I1a S1 S0 I2a S1 S0 + I3a S1 S0) Zb = E0b (I0b S1 S0 + I1b S1 S0 I2b S1 S0 + I3b S1 S0) TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT ENABLE E0 H L L L L L L L L OUTPUT Z (Z) L H L H L H L H If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. H = HIGH Level L = LOW Level X = Irrelevant (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections. FAST AND LS TTL DATA 5-2 SN54/74LS253 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 1.0 - 2.6 12 24 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 14 mA - 30 - 0.4 - 130 12 0.35 0.5 20 - 20 20 V A A A mA mA mA mA 2.4 3.1 0.25 0.4 V V 2.4 - 0.65 3.4 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX, VE = 0 V VCC = MAX, VE = 4.5 V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) See SN54LS251 for Waveforms Limits Symbol S bl tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter P Propagation Delay, Data to Output Propagation Delay, Select to Output Output Enable Time Output Disable Time Min Typ 17 13 30 21 15 15 27 18 Max 25 20 45 32 28 23 41 27 Unit Ui ns ns ns ns Figure 1 Figure 1 Figures 4, 5 Figures 3, 5 CL = 5.0 pF, RL = 667 CL = 45 pF, F RL = 667 Test C di i T Conditions FAST AND LS TTL DATA 5-3 |
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