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SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
The MC74F160A and MC74F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74F162A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. * Synchronous Counting and Loading * High-Speed Synchronous Expansion * Typical Count Rate of 120 MHz CONNECTION DIAGRAM
VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9
MC74F160A MC74F162A
SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
FASTTM SHOTTKY TTL
J SUFFIX CERAMIC CASE 620-09
16 1
16 1
N SUFFIX PLASTIC CASE 648-08
1 *R
2 CP
3 P0
4 P1
5 P2
6 P3
7 CEP
8 GND
*MR for MC74F160A *SR for MC74F162A
16 1
D SUFFIX SOIC CASE 751B-03
FUNCTION TABLE
SR L H H H H PE X L H H H CET X X H L X CEP X X H X L ACTION ON THE RISING CLOCK EDGE ( Reset (Clear) Load (Pn Qn) )
ORDERING INFORMATION
MC74FXXXAJ MC74FXXXAN MC74FXXXAD Ceramic Plastic SOIC
Count (Increment) No Change (Hold) No Change (Hold)
9 3 4 5 6
LOGIC SYMBOL
H = HIGH Voltage Level; L = LOW Voltage Level; X = Don't Care
STATE DIAGRAM
0 15 14 13 1 2 3 4 5
7 10 2
PE CEP CET CP *R
P0
P1
P2
P3 TC 15
Q0
Q1
Q2
Q3
1 6 7 11 10 9 8
14
13
12
11
VCC = PIN 16 GND = PIN 8
12
*MR for MC74F160A *SR for MC74F162A
FAST AND LS TTL DATA 4-124
MC74F160A * MC74F162A
LOGIC DIAGRAM
P0 PE MC74F160A MC74F162A P1 P2 P3
CEP CET
MC74F162A ONLY TC
CP
CP D CD Q0
CP
MC74F160A ONLY
CP Q
D Q DETAIL A Q0 DETAIL A DETAIL A
MR (MC74F160A)
DETAIL A
SR (MC74F162A) Q0 Q1 Q2 Q3
NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FUNCTIONAL DESCRIPTION The MC74F160A and MC74F162A count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus, all changes of the Q outputs (except due to Master Reset of the MC74F160A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (MC74F160A), synchronous reset (MC74F162A), parallel load, count-up and hold. Five control inputs -- Master Reset (MR, MC74F160A), Synchronous Reset (SR, MC74F162A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) -- determine the mode of operation, as shown in the Function Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (MC74F160A) or SR (MC74F162A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74F160A and MC74F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
FAST AND LS TTL DATA 4-125
MC74F160A * MC74F162A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 -1.0 20 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 3.4 3.4 0.35 0.5 20 0.1 IIL IOS ICC Input LOW Current MR, Data, CEP, Clock PE, CET, SR Output Short Circuit Current (Note 2) Power Supply Current -60 37 -0.6 -1.2 - 150 55 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A mA mA mA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20 mA VCC = 4.50 V VCC = 4.75 V VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.5 V VCC = MAX, VOUT = 0 V VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters, or registers. In the MC74F160A and
MC74F162A decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram. Logic Equations: Count Enable = CEP * CET * PE TC = Q0 * Q1 * Q2 * Q3 * CET
FAST AND LS TTL DATA 4-126
MC74F160A * MC74F162A
AC CHARACTERISTICS
74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Parameter Maximum Count Frequency Propagation Delay, Count CP to Qn (PE Input HIGH) Propagation Delay CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qn (MC74F160A) Propagation Delay MR to TC (MC74F160A) Min 100 3.5 3.5 3.5 4.0 5.0 4.5 2.5 2.5 5.5 4.5 7.5 10 8.5 8.5 14 14 7.5 7.5 12 10.5 Max Min 90 3.5 3.5 3.5 4.0 5.0 4.5 2.5 2.5 5.5 4.5 8.5 11 9.5 9.5 15 15 8.5 8.5 13 11.5 ns ns ns ns ns 74F TA = 0C to 70C VCC = 5.0 V 10% CL = 50 pF Max Unit MHz
AC OPERATING REQUIREMENTS
74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) tH(L) tw(H) tw(L) tw(H) tw(L) tw(L) trec Parameter Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE or SR to CP Hold Time, HIGH or LOW PE or SR to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width, LOW (MC74F160A) Recovery Time, MR to CP (MC74F160A) Min 5.0 5.0 2.0 2.0 11 8.5 2.0 0 11 5.0 0 0 5.0 5.0 4.0 6.0 5.0 6.0 Max Min 5.0 5.0 2.0 2.0 11.5 9.5 2.0 0 11.5 5.0 0 0 5.0 5.0 4.0 7.0 5.0 ns 6.0 ns ns ns ns ns 74F TA = 0C to 70C VCC = 5.0 V 10% CL = 50 pF Max Unit
FAST AND LS TTL DATA 4-127
-A-
Case 751B-03 D Suffix 16-Pin Plastic SO-16
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03.
16
9
-B1 8
P
8 PL
0.25 (0.010)
M
B
M
R X 45 G -TD 16 PL
0.25 (0.010)
M
C
SEATING PLANE
K
T B
S
M
F
J
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX
9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25
INCHES MIN MAX
0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049
1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50
0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019
Case 648-08 N Suffix 16-Pin Plastic -A16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08.
B
1 8
F S
C -TK
SEATING PLANE
L
H G D 16 PL
0.25 (0.010)
M
J
M
T
A
M
DIM A B C D F G H J K L M S
MILLIMETERS MIN MAX
18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77
INCHES MIN MAX
0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070
2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.51 0.38 3.30 7.74 10 1.01
0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.020 0.015 0.130 0.305 10 0.040
-A16 9
Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
-B1 8
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
C
L
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09.
-TSEATING PLANE
K E F D 16 PL
0.25 (0.010)
M
N G
T A
S
M J 16 PL
0.25 (0.010)
M
T
B
S
DIM A B C D E F G J K L M N
MILLIMETERS MIN MAX
19.05 6.10 19.55 7.36 4.19 0.39 0.53
INCHES MIN MAX
0.750 0.240 0.770 0.290 0.165 0.015 0.021
1.27 BSC 1.40 1.77
0.050 BSC 0.055 0.070
2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.39 15 0.88
0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 0.015 15 0.035
FAST AND LS TTL DATA 4-128
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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FAST AND LS TTL DATA 4-129

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