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DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD) Link -- 65 MHz
August 1998
DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-- 65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-- 65 MHz
General Description
The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will inter-operate with a Falling edge Receiver (DS90CF384) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support n Programmable Transmitter (DS90C383) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption < 250 mW (typ) n Power-down mode (< 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. n Up to 227 Megabytes/sec bandwidth n Up to 1.8 Gbps throughput n Narrow bus reduces cable size and cost n 290 mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package n Falling edge data strobe Receiver n Compatible with TIA/EIA-644 LVDS standard n ESD rating >7 kV
Block Diagrams
Application
DS012887-2
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1998 National Semiconductor Corporation
DS012887
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Block Diagrams
(Continued) DS90C383
DS012887-1
Order Number DS90C383MTD See NS Package Number MTD56 DS90CF384
DS012887-24
Order Number DS90CF384MTD See NS Package Number MTD56
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) -0.3V to +4V CMOS/TTL Input Voltage -0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 4 sec) +260C Maximum Package Power Dissipation Capacity 25C MTD56 (TSSOP) Package:
DS90C383 DS90CF384 Package Derating: DS90C383 DS90CF384 ESD Rating (HBM, 1.5 k, 100 pF)
1.63 W 1.61 W 12.5 mW/C above +25C 12.4 mW/C above +25C
> 7 kV
Recommended Operating Conditions
Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 -10 0 Nom 3.3 +25 Max 3.6 +70 2.4 100 Units V C V mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOD VOS VOS IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between complimentary output states Offset Voltage (Note 4) Change in VOS between complimentary output states Output Short Circuit Current Output TRI-STATE (R) Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case ICCTG Transmitter Supply Current 16 Grayscale RL = 100, CL = 5 pF, Worst Case Pattern f = 32.5 MHz f = 37.5 MHz f = 65 MHz f = 32.5 MHz f = 37.5 MHz f = 65 MHz 31 32 37 23 28 31 45 50 55 35 40 45 mA mA mA mA mA mA VOUT = 0V, RL = 100 Power Down = 0V, VOUT = 0V or VCC VCM = +1.2V -100 +100 mV mV A A -3.5 -5 mA A 1.125 1.25 1.375 35 V mV IOH = -0.4 mA IOL = 2 mA ICL = -18 mA VOUT = VCC, GND, 2.5V or 0.4V VOUT = 0V RL = 100 250 Conditions Min 2.0 GND 2.7 3.3 0.06 -0.79 0.3 -1.5 Typ Max VCC 0.8 Units V V V V V A mA mV mV CMOS/TTL DC SPECIFICATIONS
5.1
-60 345
10
-120 450 35
LVDS DC SPECIFICATIONS
1
10
10 10
(Figures 1, 3 )
RL = 100, CL = 5 pF, 16 Grayscale Pattern
(Figures 2, 3 )
3
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Electrical Characteristics
Symbol ICCTZ Parameter Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case ICCRG Receiver Supply Current, 16 Grayscale ICCRZ Receiver Supply Current Power Down
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. Conditions Power Down = Low Driver Outputs in TRI-STATE (R) under Power Down Mode C = 8 pF, f = 32.5 MHz f = 37.5 MHz f = 65 MHz f = 32.5 MHz f = 37.5 MHz f = 65 MHz 49 53 78 28 30 43 10 65 70 105 45 47 60 55 mA mA mA mA mA mA A Min Typ 10 Max 55 Units A TRANSMITTER SUPPLY CURRENT
L
Worst Case Pattern
(Figures 1, 4 )
C
L
= 8 pF,
16 Grayscale Pattern
(Figures 2, 4 )
Power Down = Low
Receiver Outputs Stay Low during Power Down Mode
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). Note 4: VOS previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TCIT TCCS TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TCIP TCIH TCIL TSTC THTC TCCD TPLLS TPDD Parameter LVDS Low-to-High Transition Time (Figure 3 ) LVDS High-to-Low Transition Time (Figure 3 ) TxCLK IN Transition Time (Figure 5 ) TxOUT Channel-to-Channel Skew (Figure 6 ) Transmitter Output Pulse Position for Bit 0 (Figure 17 ) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 TxCLK IN Period (Figure 7) TxCLK IN High Time (Figure 7) TxCLK IN Low Time (Figure 7) TxIN Setup to TxCLK IN (Figure 7 ) TxIN Hold to TxCLK IN (Figure 7 ) TxCLK IN to TxCLK OUT Delay 25C, VCC = 3.3V (Figure 9 ) Transmitter Phase Lock Loop Set (Figure 11 ) Transmitter Power Down Delay (Figure 15 ) f = 65 MHz f = 65 MHz -0.4 1.8 4.0 6.2 8.4 10.6 12.8 15 0.35T 0.35T 2.5 0 3 5.5 10 100 250 0 2.2 4.4 6.6 8.8 11 13.2 T 0.5T 0.5T 0.3 2.5 4.7 6.9 9.1 11.3 13.5 50 0.65T 0.65T Min Typ 0.75 0.75 Max 1.5 1.5 5 Units ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified Symbol CLHT CHLT RSPos0 RSPos1 RSPos2 RSPos3 RSPos4 RSPos5 RSPos6 RSKM RCOP RCOH RCOL RSRC RHRC RCCD RPLLS RPDD Parameter CMOS/TTL Low-to-High Transition Time (Figure 4 ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) Receiver Input Strobe Position for Bit 0 (Figure 18 ) Receiver Input Strobe Position for Bit 1 Receiver Input Strobe Position for Bit 2 Receiver Input Strobe Position for Bit 3 Receiver Input Strobe Position for Bit 4 Receiver Input Strobe Position for Bit 5 Receiver Input Strobe Position for Bit 6 RxIN Skew Margin (Note 5) (Figure 19 ) RxCLK OUT Period (Figure 8) RxCLK OUT High Time (Figure 8 ) RxCLK OUT Low Time (Figure 8) RxOUT Setup to RxCLK OUT (Figure 8 ) RxOUT Hold to RxCLK OUT (Figure 8 ) RxCLK IN to RxCLK OUT Delay 25C, VCC = 3.3V (Figure 10 ) Receiver Phase Lock Loop Set (Figure 12 ) Receiver Power Down Delay (Figure 16 ) f = 65 MHz f = 65 MHz f = 65 MHz 0.7 2.9 5.1 7.3 9.5 11.7 13.9 400 15 7.3 3.45 2.5 2.5 5 T 8.6 4.9 6.9 5.7 7.1 9 10 1 50 Min Typ 2.2 2.2 1.1 3.3 5.5 7.7 9.9 12.1 14.3 Max 5 5 1.4 3.6 5.8 8.0 10.2 12.4 14.6 Units ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ms s
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
DS012887-3
FIGURE 1. "Worst Case" Test Pattern
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AC Timing Diagrams
(Continued)
DS012887-4
FIGURE 2. "16 Grayscale" Test Pattern (Notes 6, 7, 8, 9)
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 7: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 9: Recommended pin to signal mapping. Customer may choose to define differently.
DS012887-5
FIGURE 3. DS90C383 (Transmitter) LVDS Output Load and Transition Times
DS012887-6
FIGURE 4. DS90CF384 (Receiver) CMOS/TTL Output Load and Transition Times
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AC Timing Diagrams
(Continued)
DS012887-7
FIGURE 5. DS90C383 (Transmitter) Input Clock Transition Time
DS012887-8
Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges. TxCLK Differential Low High Edge
FIGURE 6. DS90C383 (Transmitter) Channel-to-Channel Skew
DS012887-9
FIGURE 7. DS90C383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS012887-10
FIGURE 8. DS90CF384 (Receiver) Setup/Hold and High/Low Times
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AC Timing Diagrams
(Continued)
DS012887-11
FIGURE 9. DS90C383 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
DS012887-12
FIGURE 10. DS90CF384 (Receiver) Clock In to Clock Out Delay
DS012887-13
FIGURE 11. DS90C383 (Transmitter) Phase Lock Loop Set Time
DS012887-14
FIGURE 12. DS90CF384 (Receiver) Phase Lock Loop Set Time
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AC Timing Diagrams
(Continued)
DS012887-15
FIGURE 13. Seven Bits of LVDS in Once Clock Cycle
DS012887-16
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
DS012887-17
FIGURE 15. Transmitter Power Down Delay
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AC Timing Diagrams
(Continued)
DS012887-18
FIGURE 16. Receiver Power Down Delay
DS012887-26
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
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AC Timing Diagrams
(Continued)
DS012887-25
FIGURE 18. Receiver LVDS Input Strobe Position
11
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AC Timing Diagrams
(Continued)
DS012887-21
C -- Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos -- Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11) Cable Skew -- typically 10 ps-40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHZ Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 19. Receiver LVDS Input Skew Margin
DS90C383 Pin Description -- FPD Link Transmitter
Pin Name TxIN TxOUT+ TxOUT- FPSHIFT IN R_FB RTxCLK OUT+ TxCLK OUT- PWR DOWN VCC GND PLL VCC PLL GND LVDS VCC LVDS GND I/O I O O I I O O I I I I I I I No. 28 4 4 1 1 1 1 1 3 4 1 2 1 3 Description TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines -- FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. Programmable strobe select. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. Power supply pins for TTL inputs. Ground pins for TTL inputs. Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs.
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DS90CF384 Pin Description -- FPD Link Receiver
Pin Name RxIN+ RxIN- RxOUT RxCLK IN+ RxCLK IN- FPSHIFT OUT PWR DOWN VCC GND PLL VCC PLL GND LVDS VCC LVDS GND I/O I I O I I O I I I I I I I No. 4 4 28 1 1 1 1 4 5 1 2 1 3 Positive LVDS differentiaI data inputs. Negative LVDS differential data inputs. TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines -- FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differential clock input. Negative LVDS differential clock input. TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT. TTL level input. When asserted (low input) the receiver outputs are low. Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. Description
Applications Information
The DS90C383 and DS90CF384 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CR583, DS90CR584, DS90CF583 and DS90CF584). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of both the transmitter and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90C383 (transmitter) incorporates a rise/fall strobe select pin. This select function is on pin 17, formerly a VCC connection on the 5V products. When the rise/fall strobe select pin is connected to VCC, the part is configured with a rising edge strobe. In a system currently using a 5V rising edge strobe transmitter (DS90CR583), no layout changes are required to accommodate the new rise/fall select pin on the 3.3V transmitter. The VCC signal may remain at pin 17, and the device will be configured with a rising edge strobe. When converting from a 5V falling edge transmitter (DS90CF583) to the 3V transmitter a minimal board layout change is necessary. The 3.3V transmitter will not be configured with a falling edge strobe if VCC remains connected to the select pin. To guarantee the 3.3V transmitter functions with a falling edge strobe pin 17 should be connected to ground OR left unconnected. When not connected (left open) and internal pull-down resistor ties pin 17 to ground, thus configuring the transmitter with a falling edge strobe. 3. The DS90C383 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
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Pin Diagram
DS90C383 DS90CF384
DS012887-22
DS012887-23
Truth Table
TABLE 1. Programmable Transmitter Pin R_FB R_FB Condition R_FB = VCC R_FB = GND Strobe Status Rising edge strobe Falling edge strobe
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DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD) Link -- 65 MHz
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C383, DS90CF384 NS Package Number MTD56
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