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NJU6855
TENTATIVE 160COMMON x 128RGB LCD DRIVER FOR 65,536-COLOR STN DISPLAY
GENERAL DESCRIPTION PACKAGE
The NJU6855 is a 160COMMONx128RGB LCD driver for 65,536-color STN display. It contains common drivers, RGB drivers, a serial and a parallel MPU interface circuit, an internal LCD power supply, grayscale palettes and 327,680-bit display data RAM. The segment drivers for RGB (Red, Green, Blue) independently produce optimum 64 or 32 grayscales from a built-in grayscale palette, and the LSI achieves 65,536 colors (64x32x32). In addition, the NJU6855 operates with a low voltage of 1.7V and a low operating current, therefore it is ideally suited for battery-powered handheld applications.
BUMP CHIP
FEATURES
65,536-color STN LCD driver Built-in LCD Drivers : 160-common x 128RGB (384-segment drivers) Built-in Display Data RAM (DDRAM) : 327,680 bits for Graphic Display Programmable Display Mode - 64 grayscales(Green) - 32 grayscales(Red, Blue) 2 Areas Partial Display 8-/16-bit Parallel Interface Selectable 8-/16-bit Bus Length for Display Data Selectable 3-/4-line Serial Interface Selectable Programmable Duty Ratio and Bias Ratio Programmable Internal Voltage Booster : Maximum 7 times Programmable Contrast Control : 256-step Electronic Volume Register (EVR) Various Useful Instructions Low Operating Current Low Logic Voltage : 1.7V to 3.3V Wide LCD Voltage Range : 5.0V to 18.0V C-MOS Technology Slim Chip for COG Package : Bump Chip
Ver.2004-03-05
-1-
NJU6855
PAD LOCATION
258
258:DMY39 259:DMY40 260:COM67 : 299:COM28 300:DMY41 : 304:DMY45 305:COM27 : 332:COM0 333:DMY46 334:DMY47 335:SEGA0 336:SEGB0 337:SEGC0 : 716:SEGA127 717:SEGB127 718:SEGC127 719:DMY19 720:DMY20 721:COM80 : 748:COM107 749:DMY48 : 753:DMY52 754:COM108 : 793:COM147 794:DMY53 795:DMY54
257
TOP VIEW
NJU6855 CHIP SIZE
With scribe lane 170um Chip size : 18.69mm x 2.27mm
795
1:DMY1 2:DMY2 3:DMY3 4:COM148 : 15:COM159 16:DMY(ATRIM0) : 30:DMY16 31:TEST1 32:TEST2 33:TEST3 34:TEST3 35:TEST4 36:TEST4 37:VREF 38:VREF 39:OSC2 40:OSC2 41:CLK 42:CLK 43:RESB 44:RESB 45:CS2 46:CS2 47:VDD 48:VDD 49:CSB 50:CSB 51:VSS 52:VSS 53:RS 54:RS 55:P/S 56:P/S 57:VDD 58:VDD 59:VSS 60:VSS 61:SEL68 62:SEL68 63:WRB 64:WRB 65:RDB 66:RDB 67:D0 68:D0 69:D1 70:D1 71:D2 72:D2 73:D3 74:D3 75:D4 76:D4 77:D5 78:D5 79:D6 80:D6 81:D7 82:D7 83:D8 84:D8 85:D9 86:D9 87:D10 88:D10 89:D11 90:D11 91:D12 92:D12 93:D13 94:D13 95:D14 96:D14
97:D15 98:D15 99:CL 100:CL 101:FLM 102:FLM 103:FR 104:FR 105:VDD1 : 110:VDD1 111:VSS1 : 116:VSS1 117:VDD2 : 122:VDD2 123:VSS2 : 128:VSS2 129:VR 130:VR 131:VLCD : 135:VLCD 136:VCL1 : 140:VCL1 141:VCL2 : 145:VCL2 146:VCL3 : 150:VCL3 151:VCL4 : 155:VCL4 156:VDD3 : 161:VDD3 162:VSS3 : 167:VSS3 168:VOUT : 172:VOUT 173:C5P : 177:C5P 178:C5N : 182:C5N 183:C4P : 187:C4P 188:C4N : 192:C4N 193:C3P : 197:C3P 198:C3N : 202:C3N 203:VREG : 207:VREG 208:C2P : 212:C2P 213:C2N : 217:C2N 218:C1P :
222:C1P 223:C1N : 227:C1N 228:DMY21 : 242:DMY35 243:COM79 : 254:COM68 255:DMY36 : 257:DMY38
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Ver.2004-03-05
NJU6855
BLOCK DIAGRAM
VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 VDD VSS VLCD VCL1 VCL2 VCL3 VCL4 SEGA126 SEGB126 SEGC126 SEGC127 SEGA127 SEGB127 COM158 COM159 CL FLM FR CLK OSC2
SEGC0
SEGC1
SEGA0
SEGB0
SEGA1
SEGB1
LCD Bias Voltage Generator
Segment Driver Grayscale Controller
COM0
COM Driver COM Controller
Programmable 2~7x boosting VOUT VREG C5P C5N C4N C3P C3N C2P C2N C1P C1N (temperature compensation) C4P
Line address decoder
Y address decoder
Y address counter
7x booster
Display data RAM (DD RAM) 128 x 16x 160 = 327680 bit
X address decoder X address counter
VREF / EVOL
Line counter Display timing generator Oscillator
D6/SRCK D5 D4
Display controller
VREF
TEST1 TEST2 TEST3 TEST4 VR
RAM interface
Instruction Decoder
MPU interface
WRB
D8 D7/SDI
CS2 RS
RDB
CSB
P/S
SEL68 RESB
D9
COM1 D3 D2
D1
D15
D14
D13
D12
D11
Ver.2004-03-05
D10
D0
-3-
NJU6855
LCD POWER SUPPLY BLOCK DIAGRAM
VREF (External VREF)
VREF TC
EVOL
+ -
+ -
VLCD
TC : Temperature Compensation
TC Register
EVOL Register
+ -
VCL1
+ Power Control Register
Boost step setting VOUT VREG C5P C5N C4P C4N C3P C3N C2P C2N C1P C1N
Gain Control Register
-
VCL2
+ Gain Control -
VCL3
+ 7x booster
VCL4
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Ver.2004-03-05
NJU6855
TERMINAL DESCRIPTION
Power Supply
No. 105-110 117-122 156-161 47-48 57-58 51-52 59-60 111-116 123-128 162-167 131-135 136-140 141-145 146-150 151-155 218-222 223-227 208-212 213-217 193-197 198-202 183-187 188-192 173-177 178-182 168-172 203-207 37-38 Terminal VDD1 VDD2 VDD3 VDD VSS VSS1 Vss2 VSS3 VLCD VCL1 ~VCL4 C1P, C1N C2P, C2N C3P, C3N C4P, C4N C5P, C5N VOUT VREG VREF Power/O I/O Power Power Power Power Power Power Power Power Description Power Supply for Logic Circuit Power Supply for Analog Circuit Power Supply for Voltage Booster Power Supply for Logic Circuit(Internally connected to VDD1) External power supply is not allowed GND for Logic Circuit (internally connected to VSS1) External power supply is not allowed. GND for Logic Circuit GND for Analog Circuit GND for Voltage Booster(or high voltage) LCD Bias Voltage When the internal LCD power supply is used, LCD bias voltages (VLCD and VCL1~VCL4) are generated by the built-in Voltage Booster, and capacitors must be connected between these pins and GND for stabilizing. When the external LCD power supply is used, LCD bias voltages must maintain the following shown relationship: VSS < VCL4 < VCL3 < VCL2 < VCL1 < VLCD Capacitor Connection for Voltage Booster Capacitor Connection for Voltage Booster Capacitor Connection for Voltage Booster Capacitor Connection for Voltage Booster Capacitor Connection for Voltage Booster High Voltage Power Supply(from external power) Internal Voltage Booster output (2x~7x boosting) High Voltage Power Supply(from external power) Internal Voltage Booster output(2x boosting) External Reference Voltage Input Pin When TSEL<2:0> is "101" or "110" or "111", external reference voltage is used. Set to "L" or "H" when not used.
O O O O O Power/O Power/O I
Ver.2004-03-05
-5-
NJU6855
MPU Interface
No. 79-80 81-82 67-78 83-98 49-50 45-46 Terminal D6/SRCK D7/SDI D0-D5 D8-D15 I/O I/O I/O I/O I/O Description Parallel Interface D7 to D0: 8-bit Bi-directional Bus(P/S="H") Serial Interface SDI: Serial Data Input SRCK: Shift Clock 8-bit Bidirectional Bus In the 16-bit data bus mode, D15~D8 assigned to upper 8-bit data. In the serial interface mode or 8-bit parallel interface mode, D15-D8 should be fixed to "H" or "L". Chip Select Active "L" Register Select Interprets transferred data as display data or instruction RS H L Data Instruction Display Data 80-series MPU Interface (P/S="H", SEL68="L") Data Read (RDb) Signal: Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Enable Signal: Active "H" 80-series MPU Interface (P/S="H", SEL68="L") Data Write (WRb) Signal: Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Data Read or Write (R/W) Signal R/W H L Status MPU Mode Select 61-62 SEL68 I SEL86 MPU H 68-series L 80-series Read Write
CSB, CS2
I
53-54
RS
I
65-66
RDB(E)
I
63-64
WRB(R/WB)
I
55-56
P/S
I
Parallel/Serial Interface Mode Select Chip Display / Read Serial P/S Data Select Instruction /Write Clock H CSB RS D0 ~ D7 RDB, WRB L CSB RS SDI (D7) Write Only SRCK (D6) In the serial interface mode (P/S="L"), RDB, WRB, D0-D5 and D8-D15 should be fixed to "H" or "L",. Reset Test(Only for maker use) Keep open Test(Only for maker use) Keep open Test(Only for maker use) Keep open Test(Only for maker use) Keep open Test(Only for maker use) Keep open
43-44 31 32 33-34 35-36 129-130
RESB TEST1 TEST2 TEST3 TEST4 VR
I I O I O I
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Ver.2004-03-05
NJU6855
LCD Output
No. Terminal I/O Segment Drivers Output REV Mode SEGA0~ SEGA127, SEGB0~ SEGB127, SEGC0~ SEGC127 Normal Reverse O Turn-off 0 1 Turn-on 1 0 Description
335-718
FRAME signal Display RAM data Normal mode Reverse mode VCL3 VSS VCL2 VLCD VSS VCL3 VLCD VCL2
99-100 101-102 103-104 4-15 243-254 260-299 305-332 721-748 754-793 41-42 39-40
CL FLM FR
O O O
Normally open. Normally open. Normally open. Common Divers Output Data H L H L
COM0~ COM159
O
FR H H L L
Output level VLCD VCL4 VSS VCL1
CLK OSC2
I O
External Reference Clock Input Fix to "L" or "H" when not used Display Timing Clock Output Internal oscillator wave will be output when MCKSEL is "H".
Ver.2004-03-05
-7-
NJU6855
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITION TERMINAL RATING UNIT Supply Voltage (1) VDD1 VDD1 -0.3 to +4.0 V Supply Voltage (2) VDD2 VDD2 -0.3 to +4.0 V VSS1= VSS2= Supply Voltage (3) VDD3 VDD3 -0.3 to +4.0 V VSS3=0V Supply Voltage (4) VOUT VOUT -0.3 to +20.0 V Ta = +25C Supply Voltage (5) VLCD VLCD -0.3 to +20.0 V Supply Voltage (6) VCL1~VCL4 VCL1~VCL4 -0.3 to VLCD + 0.3 V *1 -0.3 to VDD1 + 0.3 Input Voltage VI V Storage Temperature Tstg -45 to +125 C *1 D0 ~ D15, CSB, CS2, RS, WRB, RDB, CLK, RESB, TEST1~4 terminals *2 To stabilize the LSI operation, place decoupling capacitors between VDD1 and VSS1, VDD2 and VSS2, VDD3 and VSS3.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VDD3 VOUT VLCD VREG VREF Topr TERMINAL VDD1 VDD2 VDD3 VOUT VLCD VREG VREF MIN 1.7 2.4 2.4 5 5 4.8 1.0 -30 TYP MAX 3.3 3.3 3.3 18.0 18.0 6.6 1.3 85 UNIT V V V V V V V C NOTE
*1 *2 *3
Operating Voltage Operating Temperature
1.2
*1. When the Voltage booster is used, VDD3 should be used within the limit range, and VDD2 can be connected to VDD3. *2. Please keep the relationship as following shown, VOUTVLCD>VCL1>VCL2>VCL3>VCL4>VSS, VOUTVREGVCL2, when the internal boosting circuit is not used. *3. When the internal reference voltage circuit is used, reference voltage VREF should be used within the limit range.
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Ver.2004-03-05
NJU6855
DC CHARACTERISTICS
VSS = 0V, VDD1=+1.7 to +3.3V, VDD2=+2.4 to +3.3V, Ta=-30 to +85C PARAMETER High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Input leakage current Output leakage current Driver ON-resistance Stand-by current Internal oscillation Frequency Voltage converter output voltage Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) Supply current (7) Supply current (8) SYM BOL VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO RON1 ISTB fOSC1 fOSC2 fOSC3 fOSC4 VOUT IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 VCL2 VCL3 VD12 VD34 VD24 CONDITION MIN 0.8 VDD1 0 VDD1 - 0.4 VDD1 - 0.4 0.4 TBD TBD 1 2 TBD 1572 1045 850 671.5 (N x VDD3) x 0.95 1850 1230 1000 790 2127 1414 1150 908.5 TYP MAX VDD1 0.2VDD1 0.4 UNIT NOTE V V V V V V A A k A kHz V TBD TBD TBD TBD TBD TBD TBD TBD -100 -100 -100 -30 -30 0 0 0 0 0 +100 +100 +30 +30 +30 A *13 *1 *1 *2 *2 *3 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12
IOH = -0.4mA IOL = 0.4mA IOH = -0.1mA IOL = 0.1mA VI = VSS1 or VDD1 VI = VSS1 or VDD1 |VON| = 0.5V CSB=VDD1, Ta=25C VDD2 = 3V Ta = 25C N-time booster (N=2 to 7) VDD3 =2.5V, 7-time booster All ON pattern VDD3 =2.5V, 7-time booster Checker pattern VDD3 =3V, 6-time booster All ON pattern VDD3 =3V, 6-time booster Checker pattern VDD3 =3V, 5-time booster All ON pattern VDD3 =3V, 5-time booster Checker pattern VDD3 =3V, 4-time booster All ON pattern VDD3 =3V, 4-time booster Checker pattern VLCD = 10V VLCD = 6V VDD1 = 3V
2 4
Output Voltage
mV
*14
Ver.2004-03-05
-9-
NJU6855
Applied Terminals (* remark solves) *1. D0~D15, CSB, RS, RDB, WRB, P/S, SEL68, RESB terminals *2. D0~D15 terminals *3. OSC2 terminals *4. CSB, RS, SEL68, RDB, WRB, P/S, RES, CLK terminals *5. Applicable at D0~D15 = high impedance state *6. SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127, COM0~COM159 terminals Resistance when being supplied 0.5V between each output terminals and power terminal (VLCD, VCL1, VCL2, VCL3, and VCL4). Applicable under bias ratio = 1/9 *7. VDD1 terminal VDD1 current when source clock is stopped, chip selection (CSB=VDD1) is non- selection state and no load. *8. Oscillator frequency when internal oscillator circuit is used. Applicable under MCLK register of oscillator circuit, {MCLK<7:0>} = "00000000". *9. Oscillator frequency when internal oscillator circuit is used. Applicable under MCLK register of oscillator circuit, {MCLK<7:0>} = "01000000". *10. Oscillator frequency when internal oscillator circuit is used. Applicable under MCLK register of oscillator circuit, {MCLK<7:0>} = "10000000". *11. Oscillator frequency when internal oscillator circuit is used. Applicable under MCLK register of oscillator circuit, {MCLK<7:0>} = "11000000". *12. VOUT terminal N x boosting (N=2~7), applicable under internal oscillator circuit and internal power circuit are ON state. VDD3 = 2.4~3.3V, electric volume is MAX("11111111"). bias = 1/5~1/12, no load at LCD driver terminal. CA1= CA2=1.0F, DCON="1", AMPON="1" *13. Applicable under internal oscillator circuit and internal power circuit are ON state and no access from CPU. Electric volume is "11111111". Display data is all ON or cross check pattern, and no load at LCD driver terminal. Test condition: VDD2=VDD3, CA1=CA2=1.0F, DCON="1", AMPON="1",a=25. *14. VLCD, VCL1, VCL2, VCL3 and VCL4 terminals. VDD3 = 3.0V, VOUT=15.0V, bias = 1/5~1/12, electric volume is "11111111" Display OFF and no load at LCD drive terminal. Boosting coefficient N is 5 times. Test condition: CA1=CA2=1.0F, DCON="1", AMPON="1".

VLCD VCL1 VCL2 VCL3 VCL4 VSS
VD12 : - VD34 : - VD24 : -

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Ver.2004-03-05
NJU6855
AC CHARACTERISTICS
(1) Write operation (80-type MPU) Write Timing-1
tAS8 CSB RS WRB tWRLW8 tDS8 D0 D15 tCYC8
tAH8
tDH8
tWRHW8
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 90 35 35 30 5
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns ns ns WRB
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 160 70 70 40 5 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS WRB
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS WRB
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD1.
Ver.2004-03-05
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NJU6855
(2) Read operation (80-type MPU)
tAS8 CSB RS RDB tWRLR8
tAH8
tWRHR8 tRDH8 D0 D15 tRDD8 tCYC8
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 TRDD8 TRDH8
CONDITION
MIN. 0 0 180 80 80
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns 60 ns ns RDB
CL=15pF
10
D0 to D15
(VDD=2.2to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CL=15pF CONDITION MIN. 0 0 180 80 80 60 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS RDB
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CL=15pF CONDITION MIN. 0 0 250 120 120 110 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS RDB
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD1.
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Ver.2004-03-05
NJU6855
(3) Write operation (68-type MPU)
tAS6 CSB RS R/WB (WRB) tEHW6 E (RDB) D0 D15 tCYC6 tDS6
tAH6
tELW6 tDH8
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6
CONDITION
MIN. 0 0 90 35 35 40 5
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns ns ns E
D0 to D15
(VDD1=2.2 to 2.5V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 160 70 70 50 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS E
D0 to D15
(VDD1=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSB RS E
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD1.
Ver.2004-03-05
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NJU6855
(4) Read operation (68-type MPU)
tAS6 CSB RS R/WB (WRB) E (RDB) D0 D15 tELR6
tAH6
tEHR6 tRDH6
tRDD6 tCYC6
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
(VDD1=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns 70 ns ns E
CL=15pF
0
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
(VDD1=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns 70 ns ns E
CL=15pF
0
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 250 120 120
(VDD1=1.7 to 2.2V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSB ns RS ns ns ns 110 ns ns E
CL=15pF
10
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD1.
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Ver.2004-03-05
NJU6855
(5) Serial interface CSB tCSS tCSH
RS tASS SRCK tSHW tCYCS tSLW tAHS
tDSS
tDHS
SDI
(VDD1=2.5 to 3.3V, Ta=-30 to +85C) PARAMETER Serial clock cycle SRCK "H" level pulse width SRCK "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSB - SRCK time CSB hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SRCK RS SDI CSB
(VDD1=2.2 to 2.5V, Ta=-30 to +85C) PARAMETER Serial clock cycle SRCK "H" level pulse width SRCK "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSB - SRCK time CSB hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SRCK RS SDI CSB
(VDD1=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER SYMBOL CONDITION Serial clock cycle tCYCS SRCK "H" level pulse width tSHW tSLW SRCK "L" level pulse width Address setup time tASS Address hold time tAHS Data setup time tDSS Data hold time tDHS CSB - SRCK time tCSS tCSH CSB hold time Note) Each timing is specified based on 20% and 80% of VDD1. MIN. 80 35 35 35 35 5 35 35 35 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SRCK RS SDI CSB
Ver.2004-03-05
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NJU6855
(6) Source Clock timing
tCKLW OSC2 tCKHW
(VDD2=2.4 to 3.3V, Ta=-30 to +85C) PARAMETER OSC2 "H" level pulse width (1) OSC2 "L" level pulse width (1) OSC2 "H" level pulse width (2) OSC2 "L" level pulse width (2) OSC2 "H" level pulse width (3) OSC2 "L" level pulse width (3) OSC2 "H" level pulse width (4) OSC2 "L" level pulse width (4) SYMBOL tCKHW tCKLW tCKHW tCKLW tCKHW tCKLW tCKHW tCKLW CONDITION MCLK<7:0> ="00000000" MCLK<7:0> ="01000000" MCLK<7:0> ="10000000" MCLK<7:0> ="11000000" MIN. 0.235 0.235 0.353 0.353 0.434 0.434 0.55 0.55 MAX. 0.318 0.318 0.478 0.478 0.588 0.588 0.744 0.744 UNIT s s s s s s s s TERMINAL OSC2 OSC2 OSC2 OSC2
Note) Each timing is specified based on 20% and 80% of VDD1.
(7) Reset input timing
RESB
tRW
tR Internal circuit status During reset End of reset
PARAMETER Reset time RESB "L" level pulse width
SYMBOL tR tRW
CONDITION
MIN.
(VDD1=2.4 to 3.3V, Ta=-30 to +85C) UNIT MAX. Terminal 1.0 s s RESB
10.0
PARAMETER Reset time
SYMBOL tR
CONDITION
MIN.
MAX. 1.5
(VDD1=1.7 to 2.4V, Ta=-30 to +85C) UNIT Terminal s s RESB
RESB "L" level pulse width tRW Note) Each timing is specified based on 20% and 80% of VDD1.
10.0
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Ver.2004-03-05
NJU6855
MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
A0 A1~A7 IORQ 7
RS
VDD
Decoder
8
CSB D0~D7 RDB WRB RESB
D0~D7 RD (80-series MPU) WR RES GND
VSS
reset input
68-type MPU interface
1.7V to 3.3V
VCC
A0 A1~A15 VMA 15
RS
VDD
Decoder
8
CSB D0~D7 RDB(E) WRB(R/W) RESB VSS
D0~D7 E (68-series MPU) R/W RES GND
reset input
Serial interface
1.7V to 3.3V
VCC
A0 A1~A7 7
RS
VDD
Decoder
CSB
(CPU)
PORT1 PORT2 RES GND reset input
SDI SRCK RESB
VSS
Ver.2004-03-05
- 17 -
NJU6855
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
- 18 -
Ver.2004-03-05

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