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| MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 D D D D Interface to External ROM/EPROM (Up to 8 MBytes) 8-Bit Microprocessor with 61 instructions 32 Twelve-Bit Words and 992 Bytes of RAM 4K Internal ROM D D D 3.3V to 6.5V CMOS Technology for Low Power Dissipation 28 Software-Configurable I/O Lines 10-kHz or 8-kHz Speech Sample Rate description The MSP50C30 combines an 8-bit microprocessor, two speech synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling the microprocessor to do a multiply operation in 0.8 s. The MSP50C30 features two independent channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code modulation (PCM) can produce music or sound effects. For more information, see the MSP50C30 User's Guide (TI literature number SPSU012). PJM PACKAGE (TOP VIEW) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC OA16 OA15 OA14 OA13 OA12 OA11 OA10 OA9 OA8 OA7 OA6 OA5 OA4 OA3 OA2 OA1 NC NC NC NC NC NC NC NC OA17 OA18 OA19 OA20 OA21 OA22 VSS ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 INIT VDD PA0 NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC NC NC OA0 PD3 PD2 PD1 PD0 VDD DAC- DAC+ VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 OSC OUT NC NC NC NC NC NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. NC PA1 PA2 PA3 PA4 PA5 PA6 NC NC PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 OSC IN NC POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 absolute maximum ratings over operating free-air temperature range Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 8 V Supply current, IDD or ISS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30C to 125C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground. 2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the device. recommended operating conditions (MSP50C30) MIN VDD VIH Supply voltage High-level input voltage VDD = 3.3 V VDD = 5 V VDD = 6 V VDD = 3.3 V VIL TA Rspeaker Low-level input voltage Operating free-air temperature Minimum speaker impedance VDD = 5 V VDD = 6 V Device functionality Direct speaker drive using 2 pin push-pull DAC option 3.3 2.5 3.8 4.5 0 0 0 0 32 MAX 6.5 3.3 5 6 0.65 1 1.3 70 C V V UNIT V Unless otherwise noted, all voltages are with respect to VSS. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VT T+ VT T- Vh hys IIkg Istandby IDD Positive going threshold voltage (INIT) Positive-going Negative-going Negative going threshold voltage (INIT) Hysteresis ( VT - VT- ) (INIT) T+ T Input leakage current (except for OSC IN) Standby current (INIT low, SETOFF) Supply current VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VOH = 2.75 V VOH = 4.5 V VOH = 5.5 V VOH = 2.2 V VOH = 3.33 V VOH = 4 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.1 V VOL = 1.67 V VOL = 2 V VOH = 2.75 V VOH = 4.5 V VOH = 5.5 V VOH = 2.3 V VOH = 4 V VOH = 5 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1 V VOL = 1 V VOL = 1 V -4 -5 -6 -8 -14 - 20 5 5 5 10 20 25 - 30 -35 -40 - 50 -90 - 100 50 70 80 100 140 150 10 14.89 14 89 18.62 18 62 20 15.36 15 36 19.2 19 2 50 15.86 15 86 19.7 19 7 k MHz MHz 2.1 3.1 4.5 -12 -14 - 15 -20 - 40 - 51 9 9 9 19 29 35 -50 -60 - 65 -90 - 140 - 150 80 90 110 140 mA mA mA mA mA mA mA mA mA TEST CONDITIONS VDD = 3.5 V VDD = 6 V VDD = 3.5 V VDD = 6 V VDD = 3.5 V VDD = 6 V MIN TYP 2 3.4 1.6 2.3 0.4 1.1 2 10 MAX UNIT V V V A A IOH High-level High level output current (PA, PB) (PA IOL Low-level Low level output current (PA, PB) (PA IOH High-level High level output current (D/A) IOL Low level output current (D/A) Low-level Pullup resistance fosc(low) (l ) fosc(high) (hi h) Oscillator frequency freq enc Oscillator frequency freq enc VDD = 6 V, Resistors selected by software and connected between terminal and VDD VDD = 5 V, TA = 25C, Target frequency = 15.36 MHz VDD = 5 V, TA = 25C, Target frequency = 19.2 MHz Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. The frequency of the internal clock has a temperature coefficient of approximately - 0.2 % / C and a VDD coefficient of approximately 1%/V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 switching characteristics PARAMETER tr Rise time PA, PB, PC, PD, D/A OA tf Fall time PA, PB, PC, PD, D/A OA VDD = 3.3 V, VDD = 3.3 V, VDD = 3.3 V, VDD = 3.3 V, TEST CONDITIONS CL = 100 pF, CL = 50 pF, CL = 100 pF, CL = 50 pF, 10% to 90% 10% to 90% 10% to 90% 10% to 90% MIN NOM 50 ns 50 50 ns 50 MAX UNIT timing requirements MIN Initialization tINIT Wakeup tsu(wakeup) Setup time prior to wakeup terminal negative transition (see Figure 2) fclock = 15.36 MHz fclock = 19.2 MHz 1 s INIT pulsed low while the MSP50x3x has power applied (see Figure 1) 1 s MAX UNIT External Interrupt tsu(interrupt) (i t t) 1 1.5 20 100 20 30 100 50 50 Setup time prior to B1 terminal negative transition (see Figure 3) s Writing (Slave Mode) tsu1(B1) tsu(d) th1(B1) th(d) tw tr tf tsu2(B1) th2(B1) tdis tw tr tf td External ROM ta(ROM) ROM access time 400 ns Setup time, B1 low before B0 goes low (see Figure 4) Setup time, data valid before B0 goes high (see Figure 4) Hold time, B1 low after B0 goes high (see Figure 4) Hold time, data valid after B0 goes high (see Figure 4) Pulse duration, B0 low (see Figure 4) Rise time, B0 (see Figure 4) Fall time, B0 (see Figure 4) ns ns ns ns ns ns ns Reading (Slave Mode) Setup time, B1 before B0 goes low (see Figure 5) Hold time, B1 after B0 goes high (see Figure 5) Output disable time, data valid after B0 goes high (see Figure 5) Pulse duration, B0 low (see Figure 5) Rise time, B0 (see Figure 5) Fall time, B0 (see Figure 5) Delay time for B0 low to data valid (see Figure 5) 20 20 0 100 50 50 50 30 ns ns ns ns ns ns ns 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION INIT tINIT Figure 1. Initialization Timing Diagram Wakeup tsu(wakeup) Figure 2. Wakeup Terminal Setup Timing Diagram B1 tsu(interrupt) Figure 3. External Interrupt Terminal Setup Timing Diagram B1 tsu1(B1) tw B0 tf tr tsu(d) th(d) PA Data Valid th1(B1) Figure 4. Write Timing Diagram (Slave Mode) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION B1 tsu2(B1) tw B0 tf td PA Data Valid tr tdis th2(B1) Figure 5. Read Timing Diagram (Slave Mode) 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 MECHANICAL DATA PJM (R-PQFP-G100) 0,38 0,22 PLASTIC QUAD FLATPACK 0,65 80 0,13 M 51 81 50 12,35 TYP 14,20 13,80 17,45 16,95 100 31 1 18,85 TYP 20,20 19,80 23,45 22,95 30 0,16 NOM Gage Plane 0,25 0,25 MIN 1,03 0,73 Seating Plane 0- 7 2,90 2,50 3,40 MAX 0,10 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MSP50C30 MIXED-SIGNAL PROCESSOR SPSS021 NOVEMBER 1998 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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