View MSM98P05_992597.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2D0019-27-42 Semiconductor
Semiconductor MSM98P05
Built-in 2-Mbit OTP ROM Voice Synthesis IC
el im This version:MSM98P05 ina Jan. 1998 ry Previous version: May. 1997
Pr
GENERAL DESCRIPTION
The MSM98P05 is a PCM voice synthesis IC with built-in 2-Mbit OTP (One Time PROM). This IC employs OKI nonlinear PCM methods and contains a current mode 10-bit D/A converter and a low-pass filter. External control has been made easy by the built-in edit ROM that can form sentences by linking phrases. With the stand-alone mode/microcontroller interface mode switching pin, the MSM98P05 can support various applications. The products with build-in OTP are suited to applications to be produced in small quantities in a wide variery or those to be delivered with an early deadline. Demand like these, that is, production in small quantities in a wide variety and delivery with an early deadline is what the MSM9800 family of products with built-in mask ROM cannot meet.
FEATURES
* 8-bit OKI nonlinear PCM method * Built-in edit ROM * Random playback function * Sampling frequency : 4.0 kHz/5.3 kHz/6.4 kHz/8.0 kHz/10.6 kHz/12.8 kHz/ 16.0 kHz Note: If RC oscillation is selected, 10.6 kHz, 12.8 kHz, and 16.0 kHz cannot be selected. * Maximum number of phrases : 63 (Microcontroller interface mode) 56 (Stand-alone mode) * Built-in current mode 10-bit D/A converter * Built-in low-pass filter (LPF) * Standby function * RC oscillation (256 kHz)/ceramic oscillation (4.096 MHz) selectable * Package options: 20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name : MSM98P05RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM98P05GS-K)
1/10
VPP
PGM
Semiconductor
BLOCK DIAGRAM
STAND-ALONE MODE (CPU/STD: "L" level)
Program Circuit A2 A1 A0 SW2 SW1 SW0
Address & Switching Controller
6
18-Bit Multiplexer
2-Mbit OTP ROM (Including 11 Kbits of Edit ROM & Address ROM) 8
CPU/STD RND
Random Circuit
18-Bit Address Counter
DATA Controller PCM Synthesizer
BUSY
I/O Interface 10
OSC1 OSC2 OSC3/TEST
OSC XT/RC
Timing Controller
10-Bit DAC & LPF
MSM98P05
2/10
XT/CR
RESET
VDD
GND
VREF
AOUT
Semiconductor
MSM98P05
PIN CONFIGURATION (TOP VIEW)
VPP A0 A1 A2 RESET XT/CR BUSY GND VREF
1 2 3 4 5 6 7 8 9
20 PGM 19 SW2 18 SW1 17 SW0 16 RND 15 CPU/STD 14 OSC3/TEST 13 OSC2 12 OSC1 11 VDD
AOUT 10
20-Pin Plastic DIP Note: Applies to MSM98P05RS
VDD 1 2 3 4 5 6 7 8 9 OSC1 OSC2 NC 21 NC OSC3/TEST NC 19 NC CPU/STD RND PGM 16 VPP SW0 10 SW1 11 SW2 12 15 A2 14 A1 13 A0
24 AOUT 23 VREF 22 GND
20 BUSY
18 XT/CR 17 RESET
NC: No connection
24-Pin Plastic SOP
Note: Applies to MSM98P05GS-K
3/10
Semiconductor
MSM98P05
PIN DESCRIPTIONS
Pin DIP SOP Symbol Type Description The IC enters the standby state if this pin is set to "L" level. At this time, oscillation stops and AOUT drives a current of 0mA and becomes GND level, 5 17 RESET I then the IC returns to the initial state. This IC has a built-in power-on reset circuit. To operate power-on reset correctly, apply the power within 1 ms up to VDD. If the power cannot be applied within 1 ms, apply a RESET pulse during power-on. This pin has an internal pull-up resistor. 7 6 15 20 18 7 BUSY XT/CR CPU/STD O I I Outputs "L" level while voice is being played back. In "H" level when power is turned ON. XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L" level if RC oscillation is used. Microcontroller interface/stand-alone mode switching pin. Set to "L" level if the IC is used in stand-alone mode. Volume setting pin. If this pin is set to GND level, the maximum amplitude is 9 23 VREF I delivered. If this pin is set to VDD level, the minimum amplitude is delivered. This pin is internally connected to a pull-down resistor of approx. 10 kW during IC operation. Voice output pin. 10 8 11 24 22 1 AOUT GND VDD O -- -- The voice signals are output as current changes. A logic "L" is output from this pin in standby state. Ground pin. Power supply pin. Insert a bypass capacitor of 0.1 mF or more between VDD and GND pins. Ceramic oscillator connection pin when ceramic oscillation is selected. 12 2 OSC1 I RC connection pin when RC oscillation is selected. Input from this pin if external clock is used. Ceramic oscillator connection pin when ceramic oscillation is selected. 13 3 OSC2 O RC connection pin when RC oscillation is selected. Leave this pin open if external clock is used. Outputs "L" level in standby state. Leave this pin open when ceramic oscillation is used. 14 5 OSC3/TEST O RC connection pin when RC oscillation is selected. Outputs "H" level in standby state when RC oscillation is selected. Random playback starts if RND pin is set to "L" level. 16 8 RND I Fetches addresses from random address generation circuit in the IC at fall of RND. Set to "H" level when the random playback function is not used. This pin has internal pull-up resistor.
4/10
Semiconductor
MSM98P05
Pin DIP SOP
Symbol
Type
Description Phrase input pins corresponding to playback sound.
17-19 10-12 SW0 - SW2
I
If input changes, SW0 to SW2 pins fetch addresses after 16 ms and start voice synthesis. Each of these pins has internal pull-down resistor. Phrase input pins corresponding to playback sound. A0 input becomes invalid if the random playback function is used. Power supply pin for writing to the built-in OTP. Interface pin for writing to the built-in OTP.
2-4 1 20
13-15 16 9
A0 - A2 VPP PGM
I -- I
5/10
VPP
PGM
Semiconductor
BLOCK DIAGRAM
MICROCONTROLLER INTERFACE MODE (CPU/STD: "H" level)
Program Circuit I5 I4 I3 I2 I1 I0
Address Controller
6
18-Bit Multiplexer
2-Mbit OTP ROM (Including 11 Kbits of Edit ROM & Address ROM) 8
CPU/STD ST NAR
18-Bit Address Counter I/O Interface
DATA Controller PCM Synthesizer
10
OSC1 OSC2 OSC3/TEST
OSC XT/RC
Timing Controller
10-Bit DAC & LPF
MSM98P05
6/10
XT/CR
RESET
VDD
GND
VREF
AOUT
Semiconductor
MSM98P05
PIN CONFIGURATION (TOP VIEW)
VPP I3 I4 I5 RESET XT/CR NAR GND VREF
1 2 3 4 5 6 7 8 9
20 PGM 19 I2 18 I1 17 I0 16 ST 15 CPU/STD 14 OSC3/TEST 13 OSC2 12 OSC1 11 VDD
AOUT 10
20-Pin Plastic DIP Note: Applies to MSM98P05RS
VDD 1 2 3 4 5 6 7 8 9 OSC1 OSC2 NC 21 NC OSC3/TEST NC 19 NC CPU/STD ST PGM 16 VPP I0 10 I1 11 I2 12 15 I5 14 I4 13 I3
24 AOUT 23 VREF 22 GND
20 NAR
18 XT/CR 17 RESET
NC: No connection
24-Pin Plastic SOP
Note: Applies to MSM98P05GS-K
7/10
Semiconductor
MSM98P05
PIN DESCRIPTIONS
Pin DIP SOP
Symbol
Type
Description The IC enters the standby state if this pin is set to "L" level. At this time, oscillation stops and AOUT drives a current of 0mA and becomes GND level, then the IC returns to the initial state. This IC has a built-in power-on reset circuit. To operate power-on reset correctly, apply the power within 1 ms up to VDD. If the power cannot be applied within 1ms, apply a RESET pulse during power-on. This pin has an internal pull-up resistor. Signal output pin that indicates whether the register in the address controller
5
17
RESET
I
7
20
NAR
O
to latch the 10-15 addresses (see Block Diagram) is idle. NAR at "H" level indicates that the LATCH is empty and ST input is enabled. XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L" level if RC oscillation is used. Microcontroller interface/stand-alone mode switching pin. Set to "H" level if the IC is used in microcontroller interface mode. Volume setting pin. If this pin is set to GND level, the maximum amplitude is delivered. If this pin is set to VDD level, the minimum amplitude is delivered. This pin is internally connected to a pull-down resistor of approx. 10 kW during IC operation. Voice output pin.
6 15
18 7
XT/CR CPU/STD
I I
9
23
VREF
I
10 8 11
24 22 1
AOUT GND VDD
O -- --
The voice signals are output as current changes. A logic "L" is output from this pin in standby state. Ground pin. Power supply pin. Insert a bypass capacitor of 0.1 mF or more between this pin and the GND pin. Ceramic oscillator connection pin when ceramic oscillation is selected. RC connection pin when RC oscillation is selected. Input from this pin if external clock is used. Ceramic oscillator connection pin when ceramic oscillation is selected. RC connection pin when RC oscillation is selected. Leave this pin open if external clock is used. Outputs "L" level in standby state. Leave this pin open when ceramic oscillation is used.
12
2
OSC1
I
13
3
OSC2
O
14
5
OSC3/TEST
O
RC connection pin when RC oscillation is selected. Outputs "H" level in standby state when RC oscillation is selected. Voice synthesis starts at fall of ST, and addresses I0 to I5 are fetched at rise
16 17-19 2-4 1 20
8
ST
I
of ST. Input ST when NAR, the status signal, is at "H" level. This pin has internal pull-up resistor. Phrase input pins corresponding to vocalized sound. Power supply pin for writing to the built-in OTP. Interface pin for writing to the built-in OTP.
10-15 16 9
I0 - I5 VPP RGM
I -- I
8/10
Semiconductor
MSM98P05
PACKAGE DIMENSIONS
(Unit : mm)
DIP20-P-300-2.54-W1
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
9/10
Semiconductor
MSM98P05
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
10/10

▲Up To Search▲

Price & Availability of MSM98P05

	To Download MSM98P05 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .