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MSC1211
MS C12 11
(R)
SBAS267 - MARCH 2003
Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory
FEATURES
ANALOG FEATURES q 24-BITS NO MISSING CODES q 22-BITS EFFECTIVE RESOLUTION AT 10Hz Low Noise: 75nV q PGA FROM 1 TO 128 q PRECISION ON-CHIP VOLTAGE REFERENCE: Accuracy: 0.2% Drift: 5ppm/C q 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS q ON-CHIP OFFSET/GAIN CALIBRATION q OFFSET DRIFT: 0.02PPM/C q GAIN DRIFT: 0.5PPM/C q ON-CHIP TEMPERATURE SENSOR q SELECTABLE BUFFER INPUT q BURNOUT DETECT q QUAD 16-BIT MONOTONIC VOLTAGE DACs: 2 VDACs Can Be Programmed as IDACs 8s Settling Time DIGITAL FEATURES Microcontroller Core q 8051 COMPATIBLE q HIGH SPEED CORE: 4 Clocks per Instruction Cycle q DC TO 30MHz q SINGLE INSTRUCTION 133ns q DUAL DATA POINTER Memory q UP TO 32kB FLASH DATA MEMORY q FLASH MEMORY PARTITIONING q ENDURANCE 1M ERASE/WRITE CYCLES, 100 YEAR DATA RETENTION q IN-SYSTEM SERIALLY PROGRAMMABLE q EXTERNAL PROGRAM/DATA MEMORY (64kB) q 1280 BYTES DATA SRAM q FLASH MEMORY SECURITY q 2kB BOOT ROM q PROGRAMMABLE WAIT STATE CONTROL Peripheral Features q 34 I/O PINS q ADDITIONAL 32-BIT ACCUMULATOR q THREE 16-BIT TIMER/COUNTERS q SYSTEM TIMERS q PROGRAMMABLE WATCHDOG TIMER q FULL DUPLEX DUAL UART q MASTER/SLAVE SPITM WITH DMA q MULTI-MASTER I2CTM q 16-BIT PWM q POWER MANAGEMENT CONTROL q INTERNAL CLOCK DIVIDER q IDLE MODE CURRENT < 200A q STOP MODE CURRENT < 100nA q PROGRAMMABLE BROWNOUT RESET q PROGRAMMABLE LOW VOLTAGE DETECT q 21 INTERRUPT SOURCES q TWO HARDWARE BREAKPOINTS GENERAL FEATURES q q q q PIN COMPATIBLE WITH MSC1210 FAMILY PACKAGE: TQFP-64 LOW POWER: 4mW INDUSTRIAL TEMPERATURE RANGE: -40C to +85C q POWER SUPPLY: 2.7V to 5.25V
APPLICATIONS
q q q q q q q q q q q INDUSTRIAL PROCESS CONTROL INSTRUMENTATION LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS INTELLIGENT SENSORS PORTABLE APPLICATIONS DAS SYSTEMS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2003, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION
FLASH MEMORY PACKAGE-LEAD 4k 4k 8k 8k 16k 16k 32k 32k TQFP-64 PACKAGE DESIGNATOR(1) PAG SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING MSC1211Y2 ORDERING NUMBER MSC1211Y2PAGT MSC1211Y2PAGR MSC1211Y3PAGT MSC1211Y3PAGR MSC1211Y4PAGT MSC1211Y4PAGR MSC1211Y5PAGT MSC1211Y5PAGR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000
PRODUCT MSC1211Y2 MSC1211Y2 MSC1211Y3 MSC1211Y3 MSC1211Y4 MSC1211Y4 MSC1211Y5 MSC1211Y5
"
TQFP-64
"
PAG
"
-40C to +85C
"
MSC1211Y3
"
TQFP-64
"
PAG
"
-40C to +85C
"
MSC1211Y4
"
TQFP-64
"
PAG
"
-40C to +85C
"
MSC1211Y5
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com/msc.
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs Input Current ............................................................ 100mA, Momentary Input Current .............................................................. 10mA, Continuous Input Voltage ............................................. AGND - 0.5V to AVDD + 0.5V Power Supply DVDD to DGND ...................................................................... -0.3V to 6V AVDD to AGND ...................................................................... -0.3V to 6V AGND to DGND .............................................................. -0.3V to +0.3V VREF to AGND ....................................................... -0.3V to AVDD + 0.3V Digital Input Voltage to DGND .............................. -0.3V to DVDD + 0.3V Digital Output Voltage to DGND ........................... -0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................ +150C Operating Temperature Range ...................................... -40C to +85C Storage Temperature Range ....................................... -65C to +150C Lead Temperature (soldering, 10s) ............................................ +300C Package Power Dissipation ........................................................ 900mW Output Current All Pins ................................................................ 200mA Output Pin Short Circuit ..................................................................... 10s Thermal Resistance, Junction-to-Ambient (JA) ....................... 66.6C/W Thermal Resistance, Junction-to-Case (JC) ............................. 4.3C/W Digital Outputs Output Current ......................................................... 100mA, Continuous I/O Source/Sink Current ............................................................... 100mA Power Pin Maximum .................................................................... 300mA NOTE: (1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
MSC1211YX FAMILY FEATURES
FEATURES(1) Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad RAM (Bytes) Internal MOVX SRAM (Bytes) Externally Accessible Memory (Bytes) MSC1211Y2(2) Up to 4k Up to 4k 256 1024 64k Program, 64k Data MSC1211Y3(2) Up to 8k Up to 8k 256 1024 64k Program, 64k Data MSC1211Y4(2) Up to 16k Up to 16k 256 1024 64k Program, 64k Data MSC1211Y5(2) Up to 32k Up to 32k 256 1024 64k Program, 64k Data
NOTES: (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2N)kBytes.
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ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted. MSC1211Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources ADC OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection CONDITION Buffer OFF Buffer ON (In+) - (In-) See Figure 4 Buffer OFF Buffer ON -3dB -3dB -3dB User-Selectable Gain Ranges Buffer ON Multiplexer Channel Off, T = +25C Sensor Input Open Circuit MIN AGND - 0.1 AGND + 50mV 5/PGA 0.5 0.469 * fDATA 0.318 * fDATA 0.262 * fDATA 1 4 0.5 2 VREF/(2 * PGA) 8 1.5 1 24 22 See Typical Characteristics Sinc3 Filter End Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration 24 0.0015 7.5 0.02 0.005 0.5 80 -50 100 120 50 115 130 120 120 100 100 88 AVDD(2) AVDD 128 pF pA A V Bits % of Range ppm/C Bits Bits Bits %FSR ppm of FS ppm of FS/C % ppm/C % of FS % of FS dB dB dB dB dB dB dB V V dB A A V V dB mA A ppm/C ms mV V/C Bits % LSB mV % of FSR % of FSR V/C ppm of FSR/C TYP MAX AVDD + 0.1 AVDD - 1.5 VREF/PGA UNITS V V V M nA
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range ADC VREF Common-Mode Rejection Input Current(4) DAC Reference Current ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power ON Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient VOLTAGE DAC STATIC PERFORMANCE (5) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient
At DC fCM = 60Hz, fDATA = 10Hz fCM = 50Hz, fDATA = 50Hz fCM = 60Hz, fDATA = 60Hz fSIG = 50Hz, fDATA = 50Hz fSIG = 60Hz, fDATA = 60Hz At DC, dB = -20log(VOUT/VDD)(3) REF IN+, REF IN- VREF (REF IN+) - (REF IN-) At DC VREF = 2.5V, ADC Only For Each DAC, 5V Reference VREFH = 1 at +25C, PGA = 1, 2, 4, 8 VREFH = 0
0.0 0.3
2.5 110 10 25 2.5 1.25 65 8 50 Indefinite 5 3 8 115 375
2.495
2.505
Sink or Source Sourcing 100A CREFOUT = 0.1F T = +25C
16 0.05 All 0s Loaded to DAC Register All 1s Loaded to DAC Register +13 0 0 20 5 0.146 1 +35 +1.25
-1.25 -1.25
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ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted. MSC1211Yx PARAMETER VOLTAGE DAC OUTPUT Output Voltage Range Output Voltage Settling Time Slew Rate DC Output Impedance Short-Circuit Current CHARACTERISTICS(6) AGND To 0.003% FSR, 0200H to FD00H 8 1 7 20 25 Indefinite AVDD - 1.5 0.185 0.5 -0.4 -0.6 4.75 <1 200 500 240 850 250 250 5.25 AVDD V s V/s mA mA V of FSR of FSR of FSR of FSR V nA A A A A A A CONDITION MIN TYP MAX UNITS
All 1s Loaded to DAC Register Maximum VREF = 2.5V
IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage Relative Accuracy Zero Code Error Full-Scale Error Gain Error ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current IADC + IVREF ADC Current IADC
Over Full Range
% % % %
VDAC Current VREF Supply Current
IVDAC IVREF
AVDD Analog OFF, PDAD = 1 PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Excluding Load Current External Reference ADC ON, VDAC OFF
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD - 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result. (4) 12pF switched capacitor at fSAMP clock frequency (see Figure 6). (5) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (6) Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF (REF IN+) - (REF IN-) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted. MSC1211Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources ADC OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range CONDITION Buffer OFF Buffer ON (In+) - (In-) See Figure 4 Buffer OFF Buffer ON -3dB -3dB -3dB User-Selectable Gain Ranges Buffer On Multiplexer Channel Off, T = +25C Sensor Input Open Circuit MIN AGND - 0.1 AGND + 50mV 5/PGA 0.5 0.469 * fDATA 0.318 * fDATA 0.262 * fDATA 1 4 0.5 2 VREF/(2 * PGA) 8 1.5 1 24 22 See Typical Characteristics Sinc3 Filter End Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration 24 0.0015 7.5 0.02 0.005 1.0 80 -50 120 50 128 pF pA A V Bits % of Range ppm/C Bits Bits Bits %FSR ppm of FS ppm of FS/C % ppm/C % of FS % of FS TYP MAX AVDD + 0.1 AVDD - 1.5 VREF/PGA UNITS V V V M nA
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ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, and Bipolar, VREF (REF IN+) - (REF IN-) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted. MSC1211Yx PARAMETER SYSTEM PERFORMANCE (Cont.) Common-Mode Rejection fCM = fCM = fCM = fSIG = fSIG = At DC, dB CONDITION MIN TYP MAX UNITS
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range ADC VREF Common-Mode Rejection Input Current(4) DAC Reference Current ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power ON Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient VOLTAGE DAC STATIC PERFORMANCE (5) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient VOLTAGE DAC OUTPUT CHARACTERISTICS(6) Output Voltage Range Output Voltage Settling Time Slew Rate DC Output Impedance Short-Circuit Current IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage Relative Accuracy Zero Code Error Full-Scale Error Gain Error POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current IADC + IVREF ADC Current IADC
At DC 60Hz, fDATA = 10Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz = -20log(DVOUT/DVDD)(3)
100
115 130 120 120 100 100 85 AVDD(2) AVDD
dB dB dB dB dB dB dB V V dB A A V dB mA A ppm/C ms mV V/C Bits % of FSR LSB mV % of FSR % of FSR V/C ppm of FSR/C V s V/s mA mA
REF IN+, REF IN- VREF (REF IN+) - (REF IN-) At DC VREF = 1.25V, ADC Only For each DAC, 3V Reference VREFH = 0 at +25C, PGA = 1, 2, 4, 8
0.0 0.3
1.25 110 10 25 1.25 65 2.6 50 Indefinite 5 3 8 115 375
1.245
1.255
Sink or Source Sourcing 100A CREFOUT = 0.1F T = +25C
16 0.05 Ensured Monotonic by Design All 0s Loaded to DAC Register All 1s Loaded to DAC Register +13 0 0 20 5 0.146 1 +35 1.25
-1.25 -1.25
AGND To 0.003% FSR, 0200H to FD00H 8 1 7 16 25 Indefinite AVDD - 1.5 0.185 0.5 -0.4 -0.6 2.7 <1 200 500 240 850 250 250
AVDD
All 1s Loaded to DAC Register Maximum VREF = 2.5V
Over Full Range
% % % % 3.6
of of of of
FSR FSR FSR FSR
VDAC Current VREF Current
IVDAC IVREF
AVDD Analog OFF, PDAD = 1 PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Excluding Load Current External Reference
V nA A A A A A A
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD - 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result. (4) 12pF switched capacitor at fSAMP clock frequency (see Figure 6). (5) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (6) Ensured by design and characterization, not production tested.
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DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V
All specifications from TMIN to TMAX, unless otherwise specified. MSC1211Yx PARAMETER POWER-SUPPLY REQUIREMENTS DVDD Normal Mode, fOSC = 1MHz Normal Mode, fOSC = 8MHz Stop Mode DVDD Normal Mode, fOSC = 1MHz Normal Mode, fOSC = 8MHz Stop Mode DIGITAL INPUT/OUTPUT (CMOS) Logic Level: VIH (except XIN pin) VIL (except XIN pin) Ports 0-3, Input Leakage Current, Input Mode Pins EA, XIN Input Leakage Current VOL, ALE, PSEN, Ports 0-3, All Output Modes VOL, ALE, PSEN, Ports 0-3, All Output Modes VOH, ALE, PSEN, Ports 0-3, Strong Drive Output VOH, ALE, PSEN, Ports 0-3, Strong Drive Output Ports 0-3 Pull-Up Resistors Pins ALE, PSEN, Pull-Up Resistors Pin RST, Pull-Down Resistor 2.7 1.3 6 100 4.75 2.2 14 100 0.6 * DVDD DGND -10 DGND DVDD - 0.4 1.5 DVDD - 0.1 DVDD - 1.5 9 9 200 DVDD 0.2 * DVDD +10 0.4 DVDD 5.25 3.6 V mA mA nA V mA mA nA V V A A V V V V k k k CONDITION MIN TYP MAX UNITS
VIH = DVDD or VIH = 0V IOL = 1mA IOL = 30mA, 3V (20mA) IOH = 1mA IOH = 30mA, 3V (20mA) Flash Programming Mode Only
0 0
FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V
tUSEC = 1s, tMSEC = 1ms MSC1211Yx PARAMETER Flash Flash Mass Flash Memory Endurance Memory Data Retention and Page Erase Time Memory Data Retention CONDITION MIN 100,000 100 10 30 TYP 1,000,000 MAX UNITS cycles Years ms s
Set with FER Value in FTCON Set with FWR Value in FTCON
40
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AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V
2.7V to 3.6V SYMBOL System Clock fOSC(3) 1/tOSC(3) fOSC(3) Program Memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tHIGH tLOW tR tF FIGURE D D D A A A A A A A A A A A PARAMETER External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) ALE Pulse Width Address Valid to ALE LOW Address Hold After ALE LOW ALE LOW to Valid Instruction In ALE LOW to PSEN LOW PSEN Pulse Width PSEN LOW to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN LOW to Address Float 5 tCLK - 5 3tCLK - 40 0 0.5tCLK 2tCLK - 5 2tCLK - 40 -5 tCLK 3tCLK - 25 0 MIN 1 0 1 1.5tCLK - 5 0.5tCLK - 10 0.5tCLK 2.5tCLK - 35 0.5tCLK 2tCLK - 5 2tCLK - 30 MAX 16 16 12 4.75V to 5.25V MIN 1 1 1 1.5tCLK - 5 0.5tCLK - 7 0.5tCLK 2.5tCLK - 25 MAX 30 30 12 UNITS MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns
B B C C B B B B B B B B B B, C B, C B, C B, C C C B B, C B, C
RD Pulse Width (tMCS = 0)(4) RD Pulse Width (tMCS > 0)(4) WR Pulse Width (tMCS = 0)(4) Pulse Width (tMCS > 0)(4) RD LOW to Valid Data In (tMCS = 0)(4) RD LOW to Valid Data In (tMCS > 0)(4) Data Hold After Read Data Float After Read (tMCS = 0)(4) Data Float After Read (tMCS > 0)(4) ALE LOW to Valid Data In (tMCS = 0)(4) ALE LOW to Valid Data In (tMCS > 0)(4) Address to Valid Data In (tMCS = 0)(4) Address to Valid Data In (tMCS > 0)(4) ALE LOW to RD or WR LOW (tMCS = 0)(4) ALE LOW to RD or WR LOW (tMCS > 0)(4) Address to RD or WR LOW (tMCS = 0)(4) Address to RD or WR LOW (tMCS > 0)(4) Data Valid to WR Transition Data Hold After WR RD LOW to Address Float RD or WR HIGH to ALE HIGH (tMCS = 0)(4) RD or WR HIGH to ALE HIGH (tMCS > 0)(4) HIGH Time(5) LOW Time(5) Rise Time(5) Fall Time(5)
2tCLK - 5 tMCS - 5 2tCLK - 5 tMCS - 5 2tCLK - 40 tMCS - 40 -5 tCLK 2tCLK 2.5tCLK - 40 tCLK + tMCS - 40 3tCLK - 40 1.5tCLK + tMCS - 40 0.5tCLK - 5 tCLK - 5 tCLK - 5 2tCLK - 5 -8 tCLK - 8 -0.5tCLK - 5 -5 tCLK - 5 15 15 5 5 5 tCLK + 5 0.5tCLK + 5 tCLK + 5
2tCLK - 5 tMCS - 5 2tCLK - 5 tMCS - 5 2tCLK - 30 tMCS - 30 -5 tCLK 2tCLK 2.5tCLK - 25 tCLK + tMCS - 25 3tCLK - 25 1.5tCLK + tMCS - 25 0.5tCLK - 5 tCLK - 5 tCLK - 5 2tCLK - 5 -5 tCLK - 5 -0.5tCLK - 5 -5 tCLK - 5 10 10 5 5 5 tCLK + 5 0.5tCLK + 5 tCLK + 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D D D D
ns ns ns ns
NOTES: (1) Parameters are valid over operating temperature range, unless otherwise specified. (2) Load capacitance for Port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. (3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (4) tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection. (5) These values are characterized but not 100% production tested.
MD2 0 0 0 0 1 1 1 1
MD1 0 0 1 1 0 0 1 1
MD0 0 1 0 1 0 1 0 1
MOVX DURATION 2 Machine Cycles 3 Machine Cycles (default) 4 Machine Cycles 5 Machine Cycles 6 Machine Cycles 7 Machine Cycles 8 Machine Cycles 9 Machine Cycles
tMCS 0 4tCLK 8tCLK 12tCLK 16tCLK 20tCLK 24tCLK 28tCLK
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EXPLANATION OF THE AC SYMBOLS
Each Timing Symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designators are: A--Address C--Clock D--Input Data H--Logic Level HIGH I--Instruction (program memory contents) L--Logic Level LOW, or ALE P--PSEN Q--Output Data R--RD Signal t--Time V--Valid W--WR Signal X--No Longer a Valid Logic Level Z--Float Examples: (1) tAVLL = Time for address valid to ALE LOW. (2) tLLPL = Time for ALE LOW to PSEN LOW.
tLHLL ALE tAVLL tLLPL tLLIV PSEN tLLAX PORT 0 A0-A7 tPLAZ tPLIV tPXIZ tPXIX INSTR IN A0-A7 tPLPH
tAVIV PORT 2 A8-A15 A8-A15
FIGURE A. External Program Memory Read Cycle.
ALE tWHLH PSEN
tLLDV tLLWL tRLRH
RD tAVLL tLLAX tRLAZ PORT 0 A0-A7 from RI or DPL tAVWL tAVDV PORT 2 P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH tRLDV tRHDX DATA IN A0-A7 from PCL INSTR IN tRHDZ
FIGURE B. External Data Memory Read Cycle.
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ALE tWHLH PSEN tLLWL tWLWH
WR tAVLL tLLAX tQVWX tDW PORT 0 A0-A7 from RI or DPL tAVWL DATA OUT A0-A7 from PCL INSTR IN tWHQX
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
FIGURE C. External Data Memory Write Cycle.
tHIGH VIH1 0.8V VIH1 0.8V tLOW VIH1 0.8V tOSC
tr VIH1 0.8V
tf
FIGURE D. External Clock Drive CLK.
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RESET AND POWER-ON TIMING
FIGURE E. Reset Timing.
FIGURE F. Parallel Flash Programming Power-On Timing (EA is ignored).
FIGURE G. Serial Flash Programming Power-On Timing (EA is ignored).
SYMBOL tRW tRRD tRFD tRS tRH
PARAMETER RST width RST rise to PSEN ALE internal pull high RST falling to PSEN and ALE start Input signal to RST falling setup time RST falling to input signal hold time
MIN 2 tOSC -- -- tOSC (217 + 512) tOSC
MAX -- 5 (217 + 512) tOSC -- --
UNIT ns s ns ns ns
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PIN CONFIGURATION
P1.7/INT5/SCLK/SCK P1.6/INT4/MISO/SDA
Top View
TQFP
P1.5/INT3/MOSI
P1.4/INT2/SS
P1.1/T2EX
P1.2/RxD1
P1.3/TxD1
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
50
64 XOUT XIN P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1/TONE/PWM P3.4/T0 P3.5/T1 P3.6/WR 1 2 3 4 5 6 7 8 9
63
62
61
60
59
58
57
56
55
54
53
52
51
49 48 EA 47 P0.6/AD6 46 P0.7/AD7 45 ALE 44 PSEN/OSCCLK/MODCLK 43 P2.7/A15 42 DVDD
P0.5/AD5
41 DGND 40 P2.6/A14 39 P2.5/A13 38 P2.4/A12 37 P2.3/A11 36 P2.2/A10 35 P2.1/A09 34 P2.0/A08 33 NC 32
MSC1211
P3.7/RD 10 DVDD 11 DGND 12 RST 13 DVDD 14 DVDD 15 RDAC0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
P1.0/T2
DGND
DVDD
REFOUT/REF IN+
IDAC0/AIN0
IDAC1/AIN1
VDAC2/AIN2
VDAC3/AIN3
AIN6/EXTD
AIN7/EXTA
AINCOM
REF IN-
VDAC0
VDAC1
PIN DESCRIPTIONS
PIN # 1 2 3-10 NAME XOUT XIN P3.0-P3.7 DESCRIPTION The crystal oscillator pin XOUT supports parallel resonant AT cut crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. The crystal oscillator pin XIN supports parallel resonant AT cut crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. Port 3--Alternate Functions: PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 11, 14, 15, 42, 58 DVDD 12, 41, 57 DGND 13 RST 16 RDAC0 17 VDAC0 27 AGND 18 IDAC0/AIN0 19 IDAC1/AIN1 ALTERNATE RxD0 TxD0 INT0 INT1/TONE/PWM T0 T1 WR RD MODE Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1/TONE/PWM Output Timer 0 External Input Timer 1 External Input External Data Memory Write Strobe External Data Memory Read Strobe
Digital Power Supply Digital Ground A HIGH on the reset input for two tOSC periods will reset the device. RDAC0 Output VDAC0 Output Analog Ground IDAC0 Output/Analog Input Channel 0 IDAC1 Output/Analog Input Channel 1
MSC1211
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RDAC1
AIN4
AIN5
AGND
AVDD
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PIN DESCRIPTIONS (Cont.)
PIN # 20 21 22 23 24 25 26 28 29 30 31 32 33 34-40, 43 NAME VDAC2/AIN2 VDAC3/AIN3 AIN4 AIN5 AIN6, EXTD AIN7, EXTA AINCOM AVDD REF IN- REFOUT/REF IN+ VDAC1 RDAC1 NC P2.0-P2.7 DESCRIPTION VDAC2 Output/Analog Input Channel 2 VDAC3 Output/Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6, Low Voltage Detect Input Generates DLVD Interrupt Analog Input Channel 7, Low Voltage Detect Input Generates ALVD Interrupt Analog Common for Single-Ended Inputs Analog Power Supply Voltage Reference Negative Input Voltage Reference Output/ Voltage Reference Positive Input VDAC1 Output RDAC1 Output No Connection Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Port 2--Alternate Functions: PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 44 PSEN OSCCLK MODCLK ALTERNATE MODE A8 A9 A10 A11 A12 A13 A14 A15 Address Address Address Address Address Address Address Address Bit Bit Bit Bit Bit Bit Bit Bit 8 9 10 11 12 13 14 15
Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held HIGH for parallel programming and tied LOW for serial programming. This pin can also be selected (when not using external memory) to output the Oscillator clock, Modulator clock, HIGH, or LOW for light loads. ALE NC 0 NC 0 PSEN NC NC 0 0 PROGRAM MODE SELECTION DURING RESET Normal Operation (user application mode) Parallel Programming Serial Programming Reserved
45
ALE
Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at a constant rate of 1/2 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define serial or parallel programming mode. ALE is held HIGH for serial programming and tied LOW for parallel programming. This pin can also be selected (when not using external memory) to output HIGH or LOW for light loads. External Access Enable: EA must be externally held LOW to enable the device to fetch code from external program memory locations starting with 0000H. Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Port 0--Alternate Functions: PORT ALTERNATE MODE P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
48 46, 47, 49-54
EA P0.0-P0.7
55, 56, 59-64
P1.0-P1.7
Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Port 1--Alternate Functions: PORT ALTERNATE MODE P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 T2 T2EX RxD1 TxD1 INT2/SS INT3/MOSI INT4/MISO INT5/SCK T2 Input T2 External Input Serial Port Input Serial Port Output External Interrupt/Slave Select External Interrupt/Master Out-Slave In External Interrupt/Master In-Slave Out/SDA External Interrupt/Serial Clock/SCK
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TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
EFFECTIVE NUMBER OF BITS vs DATA RATE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA1 PGA2 PGA4 PGA8
PGA1 PGA8 PGA32 PGA64
21 20 19
ENOB (rms)
ENOB (rms)
PGA128
18 17 16 15 14
PGA16
PGA32
PGA64
PGA128
Sinc3 Filter, Buffer OFF 10 100 Data Rate (SPS) 1000
Sinc3 Filter, Buffer OFF
13 12 0 500 1000 Decimation Ratio = fMOD fDATA 1500 2000
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA1 PGA2 PGA4 PGA8
21 20 19
ENOB (rms)
PGA1
21 20 19
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = fMOD fDATA 1500 2000 Sinc3 Filter, Buffer ON
PGA32 PGA16 PGA64 PGA128
ENOB (rms)
18 17
PGA16 PGA32 PGA64 PGA128
16 15 14 13 12 0 500 1000 Decimation Ratio = fMOD fDATA 1500 2000 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
21 20 19
ENOB (rms)
PGA1
21 20 19
ENOB (rms)
PGA1
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = fMOD fDATA 1500 2000 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON
PGA16 PGA32 PGA64 PGA128
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 Sinc2 Filter
PGA32 PGA16 PGA64 PGA128
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 21 20
ENOB (rms)
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) 25 fMOD = 203kHz fMOD = 15.6kHz 15 fMOD = 31.25kHz 10 fMOD = 110kHz
20
19
ENOB (rms)
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000
5
Fast Settling Filter
fMOD = 62.5kHz 0 1 10 100 1k Data Rate (SPS) 10k 100k
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION 25 DEC = 2020 DEC = 500
NOISE vs INPUT SIGNAL 0.8 0.7
Noise (rms, ppm of FS)
20
0.6 0.5 0.4 0.3 0.2 0.1 0 -2.5
ENOB (rms)
15
DEC = 255
DEC = 50 DEC = 20
10
5
DEC = 10
0 10 100 1k Data Rate (SPS) 10k 100k
-1.5
-0.5 VIN (V)
0.5
1.5
2.5
INTEGRAL NON-LINEARITY vs INPUT SIGNAL 10 8 6
INL (ppm of FS)
INTEGRAL NON-LINEARITY vs INPUT SIGNAL 30 VREF = AVDD, Buffer OFF 20
VREF = 2.5V
-40C
INL (ppm of FS)
4 2 0 -2 -4 -6 -8 -10 -2.5 -2 -1.5 -1 -0.5 0 VIN (V) 0.5 1 1.5 2 2.5 +25C +85C
10 0 -10 -20 -30 VIN = -VREF 0 VIN (V) VIN = +VREF
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
ADC INTEGRAL NONLINEARITY vs VREF 35 30
ADC INL (ppm of FS)
INL ERROR vs PGA 100 90 80
INL (ppm of FS)
AVDD = 3V 25 20
VIN = VREF Buffer OFF
70 60 50 40 30 20
AVDD = 5V 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VREF (V)
10 0 1 2 4 8 16 32 64 128 PGA Setting
MAXIMUM ANALOG SUPPLY CURRENT 2.6 2.5
Analog Supply Current (mA)
ADC CURRENT vs PGA 900 +85C 800 +25C
IADC (A)
2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
PGA = 128, ADC ON, Brownout Detect ON, All VDACs ON = FFFFH, VDACs REF = AVDD
AVDD = 5V, Buffer = ON Buffer = OFF
700 600
-40C
500 400 300 200 100 0
AVDD = 3V, Buffer = ON Buffer = OFF
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
2
4
8
16
32
64
128
Analog Supply Voltage (V)
PGA Setting
HISTOGRAM OF OUTPUT DATA 4500 4000 2.510 2.508 2.506 2.504
VREFOUT vs LOAD CURRENT
Number of Occurrences
3500
VREFOUT (V)
3000 2500 2000 1500 1000 500 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 ppm of FS
2.502 2.500 2.498 2.496 2.494 2.492 2.490 0 0.4 0.8 1.2 1.6 2.0 2.4 VREFOUT Current Load (mA)
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
OFFSET DAC: OFFSET vs TEMPERATURE 10 8 6
1.00004 1.00006
OFFSET DAC: GAIN vs TEMPERATURE
Offset (ppm of FSR)
Normalized Gain
4 2 0 -2 -4 -6 -8 -10 -12 -40 +25 Temperature (C) +85
1.00002 1 0.99998 0.99996 0.99994 -40 +25 Temperature (C) +85
DIGITAL SUPPLY CURRENT vs FREQUENCY 100
DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER 100 Divider Values 2
Digital Supply Current (mA)
Digital Supply Current (mA)
4 10 8 16 32 1024 1 4096 2048
RUN 10 IDLE
1
0.1 0.1 1 10 100 Clock Frequency (MHz)
0.1 0.1 1 10 100 Clock Frequency (MHz)
DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE 20
Digital Supply Current (mA)
NORMALIZED GAIN vs PGA 101
+85C
Normalized Gain (%)
15 +25C 10 -40C
100
99
98
5
97
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V)
96 1 2 4 8 16 32 64 128 PGA Setting
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
CMOS DIGITAL OUTPUT 5.0 4.5 4.0
Output Voltage (V)
1.0
VDAC DIFFERENTIAL NONLINEARITY vs CODE 0.8 0.6 0.4
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10
DNL (LSB)
5V 3V 30 40 50 60 70 Output Current (mA)
3V Low Output
5V Low Output
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DAC Code
20
VDAC INTEGRAL NONLINEARITY vs CODE 40
5.0
VDAC SOURCE CURRENT CAPABILITY DAC = All 1s
20
INL (LSB)
+85C
VDAC Output (V)
4.9
4.8
0
4.7
+25C -20
4.6
-40C -40 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DAC Code
4.5 0 2 4 6 8 10 12 14 16 ISOURCE (mA)
VDAC SINK CURRENT CAPABILITY 0.6 DAC = All 0s 0.5 0
Error (% of FS)
VDAC FULL-SCALE ERROR vs LOAD RESISTOR 1
VDAC Output (V)
0.4 0.3 0.2 0.1 0 0 2 4 6 8 ISINK (mA) 10 12 14 16
-1 -2 -3 -4 -5 0.5 1 10 100 Load Resistor (k) 1k 10k
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. For VDAC, VREF = AVDD, RLOAD = 10k, and CLOAD = 200pF, unless otherwise noted.
FULL-SCALE SETTLING TIME
FULL-SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Full-Scale Code Change 0200H to FFFFH Output Loaded with 10k and 200pF to GND
Scope Trigger (5.0V/div)
Large-Signal Output (1.0V/div) Full-Scale Code Change FFFFH to 0200H Output Loaded with 10k and 200pF to GND
Large-Signal Output (1.0V/div)
Time (1s/div)
Time (1s/div)
HALF-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Half-Scale Code Change 4000H to C000H Output Loaded with 10k and 200pF to GND
Scope Trigger (5.0V/div) Half-Scale Code Change C000H to 4000H Output Loaded with 10k and 200pF to GND
Large-Signal Output (1.0V/div)
Large-Signal Output (1.0V/div)
Time (1s/div)
Time (1s/div)
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DESCRIPTION
The MSC1211Yx is a completely integrated family of mixedsignal devices incorporating a high-resolution delta-sigma ADC, quad 16-bit DACs, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC (Digital-to-Analog Converter), Programmable Gain Amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 1. On-chip peripherals include an additional 32-bit accumulator, an SPI compatible serial port with FIFO, I2C, dual UARTs, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, breakpoints, brownout reset, three timer/counters, and a system clock divider. The device accepts low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a sinc3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core which executes up to three times faster than the standard 8051 core, given the same clock source. That makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core.
The MSC1211Yx allows the user to uniquely configure the Flash and SRAM memory maps to meet the needs of their application. The Flash is programmable down to 2.7V using both serial and parallel programming methods. The Flash endurance is 100k Erase/Write cycles. In addition, 1280 bytes of RAM are incorporated on-chip. The part has separate analog and digital supplies, which can be independently powered from 2.7V to +5.5V. At +3V operation, the power dissipation for the part is typically less than 4mW. The MSC1211Yx is packaged in a TQFP-64 package. The MSC1211Yx is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation.
ENHANCED 8051 CORE
All instructions in the MSC1211 family perform exactly the same functions as they would in a standard 8051. The effect on bits, flags, and registers is the same. However, the timing is different. The MSC1211 family utilizes an efficient 8051 core which results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 2). This translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. Therefore, a device frequency of 30MHz for the MSC1211Yx actually performs at an
AVDD
AGND
REFOUT/REF IN+ REF IN-
DVDD
DGND
+AVDD VREF LVD Timers/ Counters EA ALE BOR IDAC0/AIN0 IDAC1/AIN1 VDAC2/AIN2 VDAC3/AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM V/I Converter V/I Converter IDAC1/ AIN1 AGND RDAC0 RDAC1 VDAC0 VDAC1 AIN2 AIN3 VDAC0 VDAC1 VDAC2 VDAC3 POR 1.2K SRAM 8051 PORT3 SFR SPI FIFO SYS Clock Divider Clock Generator 8 Up to 32K FLASH ACC PORT2 8 ADDR UART1 EXT T0 T1 PWM RW MUX BUF PGA Modulator Digital Filter PORT0 Temperature Sensor 8-Bit Offset DAC WDT Alternate Functions 8 ADDR DATA T2 SPI/EXT/I2C UART2 PSEN
PORT1
8
IDAC0/ AIN0
RST
XIN XOUT
FIGURE 1. Block Diagram.
CLK
instr_cycle
n+1
n+2
cpu_cycle
C1
C2
C3
C4
C1
C2
C3
C4
C1
FIGURE 2. Instruction Cycle Timing.
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equivalent execution speed of 75MHz compared to the standard 8051 core. This allows the user to run the device at slower external clock speeds which reduces system noise and power consumption, but provides greater throughput. This performance difference can be seen in Figure 3. The timing of software loops will be faster with the MSC1211. However, the timer/counter operation of the MSC1211 may be maintained at 12 clocks per increment or optionally run at 4 clocks per increment.
Single-Byte, Single-Cycle Instruction
Furthermore, improvements were made to peripheral features that offload processing from the core, and the user, to further improve efficiency. For instance, the SPI interface uses a FIFO, which allows the SPI interface to transmit and receive data with minimum overhead needed from the core. Also, a 32-bit accumulator was added to significantly reduce the processing overhead for the multiple byte data from the ADC or other sources. This allows for 24-bit addition and shifting to be accomplished in a few instruction cycles, compared to hundreds of instruction cycles through software implementation.
Family Device Compatibility
The hardware functionality and pin configuration across the MSC1211 family is fully compatible. To the user the only difference between family members is the memory configuration. This makes migration between family members simple. Code written for the MSC1211Y2 can be executed directly on an MSC1211Y3, MSC1211Y4, or MSC1211Y5. This gives the user the ability to add or subtract software functions and to freely migrate between family members. Thus, the MSC1211 can become a standard device used across several application platforms.
MSC1210 Timing
ALE PSEN AD0-AD7 PORT 2 4 Cycles CLK 12 Cycles
Standard 8051 Timing
Family Development Tools
The MSC1211 is fully compatible with the standard 8051 instruction set. This means that the user can develop software for the MSC1211 with their existing 8051 development tools. Additionally, a complete, integrated development environment is provided with each demo board, and third-party developers also provide support.
ALE PSEN AD0-AD7 PORT 2 Single-Byte, Single-Cycle Instruction
Power Down Modes
The MSC1211 can power several of the peripherals and put the CPU into IDLE. This is accomplished by shutting off the clocks to those sections, as shown in Figure 4.
FIGURE 3. Comparison of MSC1211 Timing to Standard 8051 Timing. The MSC1211 also provides dual data pointers (DPTRs) to speed block Data Memory moves. Additionally, it can stretch the number of memory cycles to access external Data Memory from between two and nine instruction cycles in order to accommodate different speeds of memory or devices, as shown in Table I. The MSC1211 provides an external memory interface with a 16-bit address bus (P0 and P2). The 16-bit address bus makes it necessary to multiplex the low address byte through the P0 port. To enhance P0 and P2 for high-speed memory access, hardware configuration control is provided to configure the ports for external memory/peripheral interface or general-purpose I/O.
CKCON (8EH) MD2:MD0 000 001 010 011 100 101 110 111 INSTRUCTION CYCLES (for MOVX) 2 3 (default) 4 5 6 7 8 9 RD or WR STROBE WIDTH (SYS CLKs) 2 4 8 12 16 20 24 28 RD or WR STROBE WIDTH (s) AT 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
SYS Clock Oscillator tOSC SYS Clock Divider tCLK
STOP
SPICON/ I2CCON 9A PDCON.0 PWMHI A3 PDCON.4 s FB
SCLK/SCK
PWMLOW A2
PWM Clock
USEC
FTCON Flash Write (30s to 40s) [3:0] EF Timing
MSECH MSECL FD FC
ms
FTCON [7:4] EF
Flash Erase (5ms to 11ms) Timing milliseconds interrupt FA seconds interrupt F9
MSINT PDCON.1
SECINT
HMSEC FE
100ms WDTCON FF PDCON.2
watchdog
ACLK
F6
divide by 64
ADC Power Down PDCON.3
ADCON3 ADCON2 DF DE Decimation Ratio
ADC Output Rate
Modulator Clock
Timers 0/1/2 IDLE
UART0/1
CPU Clock
TABLE I. Memory Cycle Stretching. Stretching of MOVX timing as defined by MD2, MD1, and MD0 bits in CKCON register (address 8EH).
FIGURE 4. MSC1211 Timing Chain and Clock Control.
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OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 5. If AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels. It is also possible to switch the polarity of the differential input pair to negate any offset voltages.
BURNOUT DETECT
When the Burnout Detect (BOD) bit is set in the ADC control configuration register (ADCON0 DCH), two current sources are enabled. The current source on the positive input channel sources approximately 2A of current. The current source on the negative input channel sinks approximately 2A. This allows for the detection of an open circuit (full-scale reading) or short circuit (small differential reading) on the selected input differential pair.
INPUT BUFFER
The analog input impedance is always high, regardless of PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always preferred. The input impedance of the MSC1211 without the buffer is 5M/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0 DCH).
AIN0
AIN1
AVDD Burnout Detect Current Source
AIN2
ANALOG INPUT
When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6H) and gain (PGA). The relationship is:
AIN3 In+ AIN4 In-
5M 1MHz AIN Im pedance () = * ACLK Frequency PGA where ACLK frequency = fCLK/(ACLK +1).
Burnout Detect Current Sink
AIN5
AIN6 AGND AIN7
Temperature Sensor
Figure 6 shows the basic input structure of the MSC1211. The sampling frequency varies according to the PGA settings, as shown in Table II.
I
80 * I
RSW (8k typical)
AINCOM
AIN
High Impedance > 1G CINT 12pF Typical VCM
Sampling Frequency = fSAMP
FIGURE 5. Input Multiplexer Configuration. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins.
FIGURE 6. Analog Input Structure.
PGA 1 2 4 8 16 32 64 128 FULL-SCALE RANGE VREF VREF/2 VREF/4 VREF/8 VREF/16 VREF/32 VREF/64 VREF/128 SAMPLING FREQUENCY fSAMP fSAMP fSAMP fSAMP * 2 fSAMP * 4 fSAMP * 8 fSAMP * 16 fSAMP * 16
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diodes are connected to the input of the ADC. All other channels are open.
NOTE: fSAMP = ACLK frequency/64.
TABLE II. Sampling Frequency Versus PGA Setting.
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PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a 2.5V fullscale range, the ADC can resolve to 1.5V. With a PGA of 128 on a 19mV full-scale range, the ADC can resolve to 75nV. With a PGA of 1 on a 2.5V full-scale range, it would require a 26-bit ADC to resolve 75nV, as shown in Table III.
RMS FULL-SCALE MEASUREMENT EQUIVALENT PGA RANGE ENOB RESOLUTION ENOB AT PGA = 1 SETTING (V) AT 10Hz (nV) (5V RANGE) 1 2 4 8 16 32 64 128 2.5V 1.25 0.625 0.313 0.156 0.0781 0.039 0.019 21.7 21.5 21.4 21.2 20.8 20.4 20 19 1468 843 452 259 171 113 74.5 74.5 21.7 22.5 23.4 24.2 24.8 25.4 26 26
requires a positive "full-scale" differential input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. Calibration should be performed after power on, a change in temperature, decimation ratio, buffer, or a change of the PGA. Calibration will remove the effects of the Offset DAC, therefore, changes to the Offset DAC register must be done after calibration. At the completion of calibration, the ADC Interrupt bit goes HIGH which indicates the calibration is finished and valid data is available.
DIGITAL FILTER
The Digital Filter can use either the Fast Settling, sinc2, or sinc3 filter, as shown in Figure 7. In addition, the Auto mode changes the sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter, for the next two conversions the first of which should be discarded. It will then use the sinc2 followed by the sinc3 filter to improve noise performance. This combines the low-noise advantage of the sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 8.
TABLE III. ENOB Versus PGA.
OFFSET DAC
The analog input to the PGA can be offset by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6H). The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, using the ODAC does not reduce the performance of the ADC.
Adjustable Digital Filter Sinc3
MODULATOR
The modulator is a single-loop 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from the CLK using the value in the Analog Clock register (ACLK). The data output rate is: Data Rate = fMOD/Decimation Ratio where fMOD = fCLK/(ACLK +1)/64
Modulator
Sinc2
Data Out
Fast Settling
FILTER SETTLING TIME FILTER Sinc3 Sinc2 Fast SETTLING TIME (Conversion Cycles) 3(1) 2(1) 1(1)
CALIBRATION
The offset and gain errors in the MSC1211, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDH), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. For system calibration, the appropriate signal must be applied to the inputs. The system offset command requires a "zero" differential input signal. It then computes an offset that will nullify offset in the system. The system gain command
NOTE: (1) With Synchronized Channel Changes.
AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 Discard 2 Fast 3 Sinc2 4+ Sinc3
FIGURE 7. Filter Step Responses.
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SINC3 FILTER RESPONSE (-3dB = 0.262 * fDATA) 0 -20 -40
Gain (dB)
VOLTAGE REFERENCE
The voltage reference used for the MSC1211 can either be internal or external. The power-up configuration for the voltage reference is 2.5V internal. The selection for the voltage reference is made through the ADCON0 register (SFR DCH). The internal voltage reference is selectable as either 1.25V (AVDD = 2.7V to 5.25V) or 2.5V (AVDD = 4.5V to 5.25V). If the internal VREF is not used, it should be turned off to reduce noise and power consumption. The VREFOUT pin should have a 0.1F capacitor to AGND. The external voltage reference is differential and is represented by the voltage difference between the pins: REF IN+ and REF IN-. The absolute voltage on either pin (REF IN+ and REF IN- ) can range from AGND to AVDD, however, the differential voltage must not exceed 2.6V. The differential voltage reference provides easy means of performing ratiometric measurement.
-60 -80 -100 -120 0 fD 2fD 3fD 4fD 5fD Frequency (Hz) SINC2 FILTER RESPONSE (-3dB = 0.318 * fDATA) 0 -20 -40
DAC
The architecture consists of a string DAC followed by an output buffer amplifier. Figure 9 shows a block diagram of the DAC architecture.
Gain (dB)
-60 -80
DAC3 21 AIN3/VDAC3
-100
DAC2 20 AIN2/VDAC2
-120 0 fD 2fD 3fD 4fD 5fD
DAC1 V/I Converter 19 AIN1/IDAC1 31 VDAC1
Frequency (Hz)
FAST SETTLING FILTER RESPONSE (-3dB = 0.469 * fDATA) 0
AVDD DAC0 V/I Converter
Current Mirror 32 RDAC1
17
VDAC0
-20 -40
Gain (dB)
VREF
18 Current Mirror 16
AIN0/IDAC0
RDAC0
-60 -80
FIGURE 9. DAC Architecture.
-100 -120 0 fD 2fD 3fD 4fD 5fD Frequency (Hz)
The input coding to the DAC is straight binary, so the ideal output voltage is given by:
VDAC = VREF * D 65536
NOTE: fD = Data Output Rate = 1/tDATA
FIGURE 8. Filter Frequency Responses.
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535.
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RESISTOR STRING
The DAC selects the voltage from a string of resistors from the reference to AGND. It is essentially a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because it is a string of resistors.
The output voltage for any input code can be calculated as follows: R2 D R1 + R2 VO = DACREF * * - DACREF * 65536 R1 R1 where D represents the input code in decimal (0-65535). With DACREF = 5V, R1 = R2 = 10k:
10 * D VO = - 5V 65536
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of AGND to AVDD. It is capable of driving a load of 2k in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1V/s with a full-scale settling time of 8s with the output unloaded.
This is an output voltage range of 5V with 0000H corresponding to a -5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a 2.5V output voltage can be achieved. IDAC
DAC REFERENCE
Each DAC can be selected to use the internal REFOUT/REF IN+ voltage or the supply voltage AVDD as the reference for the DAC. The full range of the voltage DAC is limited according to Table IV. The full range of the current DAC is limited according to Table V.
DAC REFERENCE DACREF = AVDD DACREF = 2.5V DACREF = 1.25V AVDD = 5V AVDD = 3V AVDD < 3.0V Not Recommended Not Recommended Not Recommended
The compliance specification of the IDAC output defines the maximum output voltage to achieve the expected current. Refer to Figure 9 for the IDAC structure and to Table V for the DAC reference selection and code range.
POWER-UP--SUPPLY VOLTAGE RAMP RATE
The built-in (on-chip) power-on reset circuitry was designed to accommodate analog or digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically at the specified rate. If BOR is enabled, the ramp rate can be slower.
Full Range Full Range Full Range Not Recommended Full Range Full Range
TABLE IV. Voltage DAC Code Range.
DAC REFERENCE DACREF = AVDD DACREF = 2.5V DACREF = 1.25V AVDD = 5V AVDD = 3V AVDD < 3.0V Not Recommended Not Recommended Not Recommended
MEMORY MAP
The MSC1211 contains on-chip SFR, Flash Memory, Scratchpad RAM Memory, Boot ROM, and SRAM. The SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1211 are controlled through the SFR. Reading from undefined SFR will return zero and writing to undefined SFR registers is not recommended and will have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memories. The partition size is set through hardware configuration bits, which are programmed through either the parallel or serial programming methods. Both Program and Data Flash Memories are erasable and writable (programmable) in user application mode. However, only program execution can occur from Program Memory. As an added precaution, a lock feature can be activated through the hardware configuration bits, which disables erase and writes to 4kB of Program Flash Memory or the entire Program Flash Memory in user application mode. The MSC1211 includes 1kB of SRAM on-chip. SRAM starts at address 0 and is accessed through the MOVX instruction. This SRAM can also be located to start at 8400H and can be accessed as both Program and Data Memory.
0000-7FFFH 0000-3FFFH Full Range Not Recommended Full Range Full Range
TABLE V. Current DAC Code Range.
DAC LOADING
The DAC can be selected to be turned off with a 1k, 100k, or open circuit on the DAC outputs.
BIPOLAR OPERATION USING THE DAC
The DAC can be used for a bipolar output range, as shown in Figure 10. The circuit shown will give an output voltage range of VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
R2 100k +5V R1 100k DACREF OPA703 VREF VDAC 5V
-5V
FIGURE 10. Bipolar Operation with the DAC.
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FLASH MEMORY
The MSC1211 uses a memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area is 64kB beginning at address 0000H and ending at FFFFH, as shown in Figure 11. The program and data segments can overlap since they are accessed in different ways. Program Memory is fetched by the microcontroller automatically. There is one instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read lookup tables. The Data Memory area is accessed explicitly using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is used to access the 64kB of Data Memory. The address and data range of devices with on-chip Program and Data Memory overlap the 64kB memory space. When on-chip memory is enabled, accessing memory in the on-chip range will cause the device to access internal memory. Memory accesses beyond the internal range will be addressed externally via Ports 0 and 2.
HCR0 DFSEL 000 001 010 011 100 101 110 111 (default)
MSC1211Y2 MSC1211Y3 MSC1211Y4 MSC1211Y5 PM DM PM DM PM DM PM DM
0000 040013FF 0000 040013FF 0000 0400 13FF 0000 040013FF
0000 040023FF 0000 040023FF 0000 0400 23FF 0000 040023FF
0000 040043FF 0000 040043FF
0000 040083FF 0000 040083FF
0000 0400 0000- 040043FF 3FFF 43FF 0000- 0400- 0000- 04001FFF 23FF 5FFF 23FF 0000- 0400- 0000- 04002FFF 13FF 6FFF 13FF 0000- 0400- 0000- 040037FF 0BFF 77FF 0BFF 0000- 0400- 0000- 04003BFF 07FF 7BFF 07FF 0000- 0000 3FFF 0000- 0000 7FFF
0000 0400- 0000- 040013FF 0FFF 13FF 0000- 0400- 0000- 040007FF 0BFF 17FF 0BFF 0000- 0400- 0000- 04000BFF 07FF 1BFF 07FF 0000- 0000 0FFF 0000- 0000 1FFF
NOTE: Program memory accesses above the highest listed address will access external program memory.
TABLE VII. Flash Memory Partitioning. It is important to note that the Flash Memory is readable and writable (depending on the MXWS bit in the MWS SFR) by the user through the MOVX instruction when configured as either Program or Data Memory. This means that the user may partition the device for maximum Flash Program Memory size (no Flash Data Memory) and use Flash Program Memory as Flash Data Memory. This may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning prohibits execution of code from Data Flash Memory. Additionally, the Program Memory erase/ write can be disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) to Data Flash Memory. The effect of memory mapping on Program and Data Memory is straightforward. The Program Memory is decreased in size from the top of internal Program Memory. Therefore, if the MSC1211Y5 is partitioned with 31kB of Flash Program Memory and 1kB of Flash Data Memory, external Program Memory execution will begin at 7C00H (versus 8000H for 32kB). The Flash Data Memory is added on top of the SRAM memory. Therefore, access to Data Memory (through MOVX) will access SRAM for addresses 0000H-03FFH and access Flash Memory for addresses 0400H-07FFH.
Program Memory
Select in HCR0
2k Internal Boot ROM FFFFH F800H
Data Memory
FFFFH
External Program Memory
Select in MCON
1k RAM or External External Memory
Mapped to Both Memory Spaces (von Neumann) 8800H 8400H 8000H, 32k (Y5)
External Data Memory
1k RAM or External 8800H 8400H, 33k (Y5) 4400H, 17k (Y4)
O
Ch
Select in MCON
n-
O
4000H, 16k (Y4)
n-
ip
Ch
Fl
as
2000H, 8k (Y3)
ip
h
1000H, 4k (Y2) 0000H, 0k
Fl
as
2400H, 9k (Y3)
h
1400H, 5k (Y2) 0400H, 1k
1k RAM or External
FIGURE 11. Memory Map. The MSC1211 has two Hardware Configuration registers (HCR0 and HCR1) that are programmable only during Flash Memory Programming mode. The MSC1211 allows the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1211Y5 contains 32kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Tables VI and VII. The MSC1211 family offers four memory configurations.
HCR0 DFSEL 000 001 010 011 100 101 110 111 (default) MSC1211Y2 MSC1211Y3 MSC1211Y4 MSC1211Y5 PM 0kB 0kB 0kB 0kB 0kB 2kB 3kB 4kB DM 4kB 4kB 4kB 4kB 4kB 2kB 1kB 0kB PM 0kB 0kB 0kB 0kB 4kB 6kB 7kB 8kB DM 8kB 8kB 8kB 8kB 4kB 2kB 1kB 0kB PM 0kB 0kB 0kB 8kB 12kB 14kB 15kB 16kB DM 16kB 16kB 16kB 8kB 4kB 2kB 1kB 0kB PM DM
Data Memory
The MSC1211 can address 64kB of Data Memory. Scratchpad Memory provides 256 bytes in addition to the 64kB of Data Memory. The MOVX instruction is used to access the Data SRAM Memory. This includes 1024 bytes of on-chip Data SRAM Memory. The data bus values do not appear on Port 0 (during data bus timing) for internal memory access. The MSC1211 also has on-chip Flash Data Memory which is readable and writable (depending on Memory Write Select register) during normal operation (full VDD range). This memory is mapped into the external Data Memory space directly above the SRAM.
0kB 32kB 0kB 32kB 16kB 16kB 24kB 8kB 28kB 4kB 30kB 2kB 31kB 1kB 32kB 0kB
NOTE: When a 0kB program memory configuration is selected program execution is external.
TABLE VI. MSC1211Y Flash Partitioning.
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REGISTER MAP
The Register Map is illustrated in Figure 12. It is entirely separate from the Program and Data Memory areas mentioned before. A separate class of instructions is used to access the registers. There are 256 potential register locations. In practice, the MSC1211 has 256 bytes of Scratchpad RAM and up to 128 SFRs. This is possible, since the upper 128 Scratchpad RAM locations can only be accessed indirectly. That is, the contents of a Working Register (described below) will designate the RAM location. Thus, a direct reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7FH (0 to 127).
FFH Indirect RAM 7FH Direct RAM 2FH 2EH 2DH 2CH 2BH 2AH FFH Indirect RAM 80H 7FH Direct RAM 0000H Scratchpad RAM 128 255 Direct Special Function Registers 80H SFR Registers 26H 25H 24H 23H 22H 37 2F 27 1F 17 0F 07 36 2E 26 1E 16 0E 06 35 2D 25 1D 15 0D 05 34 2C 24 1C 14 0C 04 33 2B 23 1B 13 0B 03 32 2A 22 1A 12 0A 02 31 29 21 19 11 09 01 30 28 20 18 10 08 00 FFH 29H 28H 27H 7F 77 6F 67 5F 57 4F 47 3F 7E 76 6E 66 5E 56 4E 46 3E 7D 75 6D 65 5D 55 4D 45 3D 7C 74 6C 64 5C 54 4C 44 3C 7B 73 6B 63 5B 53 4B 43 3B 7A 72 6A 62 5A 52 4A 42 3A 79 71 69 61 59 51 49 41 39 78 70 68 60 58 50
Bit Addressable
48 40 38
FIGURE 12. Register Map. SFRs are accessed directly between 80H and FFH (128 to 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data contents are small. When off-chip RAM is needed, the Scratchpad area will still provide the fastest generalpurpose access. Within the 256 bytes of RAM, there are several special-purpose areas.
21H 20H 1FH
Bank 3 18H 17H 10H 0FH Bank 1 08H 07H Bank 0 0000H MSB LSB Bank 2
Bit Addressable Locations
In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20H to 2FH are bit addressable. This provides 128 (16 * 8) individual bits available to software. A bit access is distinguished from a full-register access by the type of instruction. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 13 shows details of the onchip RAM addressing including the locations of individual RAM bits.
FIGURE 13. Scratchpad Register Addressing. stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the these registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions.
Stack
Another use of the Scratchpad area is for the programmer's stack. This area is selected using the Stack Pointer (SP; 81H) SFR. Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack. The Stack Pointer will default to 07H on reset. The user can then move it as needed. A convenient location would be the upper RAM area (> 7FH) since this is only available indirectly. The SP will point to the last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment the SP by the appropriate value. Each POP or RET will decrement as well.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 13. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0-R7. This allows software to change context by simply switching banks. This is controlled via the Program Status Word register (PSW; 0D0H) in the SFR area described below. Registers R0 and R1 also allow their contents to be used for indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value
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Program Memory
After reset, the CPU begins execution from Program Memory location 0000H. The selection of where Program Memory execution begins is made by tying the EA pin to VDD for internal access, or DGND for external access. When EA is tied to VDD, any PC fetches outside the internal Program Memory address occur from external memory. If EA is tied to DGND, then all PC fetches address external memory. The standard internal Program Memory size for MSC1211 family members is shown in Table VIII. Refer to the Accessing External Memory section for details on using external Program Memory. If enabled the Boot ROM will appear from address F800H to FFFFH.
STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES) 32k 16k 8k 4k
If an 8-bit address is being used (MOVX @RI), the contents of the MPAGE (92H) SFR remain at the Port 2 pins throughout the external memory cycle. This will facilitate paging. In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The ADDR/DATA signals use CMOS drivers in the Port 0, Port 2, WR, and RD output buffers. Thus, in this application the Port 0 pins are not opendrain outputs, and do not require external pull-ups for highspeed access. Signal ALE (Address Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated. The function of Port 0 and Port 2 is selected in Hardware Configuration Register 1. This can only be changed during the Flash Program mode. There is no conflict in the use of these registers; they will either be used as general-purpose I/O or for external memory access. The default state is for Port 0 and Port 2 to be used as general-purpose I/O. If an external memory access is attempted when they are configured as generalpurpose I/O, the values of Port 0 and Port 2 will not be affected. External Program Memory is accessed under two conditions: 1) Whenever signal EA is LOW during reset, then all future accesses are external, or 2) Whenever the Program Counter (PC) contains a number that is outside of the internal Program Memory address range, if the ports are enabled. If Port 0 and Port 2 is selected for external memory, all 8 bits of Port 0 and Port 2, as well as P3.6 and P3.7, are dedicated to an output function and may not be used for generalpurpose I/O. During external program fetches, Port 2 outputs the high byte of the PC.
MODEL NUMBER MSC1211Y5 MSC1211Y4 MSC1211Y3 MSC1211Y2
TABLE VIII. MSC1211 Maximum Internal Program Memory Sizes.
ACCESSING EXTERNAL MEMORY
If external memory is used, P0 and P2 can be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the Hardware Configuration Register. To enable access to external memory bits 0 and 1 of the HCR1 register must be set to 0. When these bits are enabled all memory accesses for both internal and external memory will appear on ports 0 and 2. During the data portion of the cycle for internal memory, Port 0 will be zero for security purposes. Accesses to external memory are of two types: accesses to external Program Memory and accesses to external Data Memory. Accesses to external Program Memory use signal PSEN (program store enable) as the read strobe. Accesses to external Data Memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data Memory. A program fetch from external Program Memory uses a 16bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @RI). If Port 2 is selected for external memory use (HCR1, bit 0), it can not be used as a general-purpose I/O. This bit (or Bit 1 of HCR1) also forces bits P3.6 and P3.7 to be used for WR and RD instead of I/O. Port 2, P3.6, and P3.7 should all be written to `1'.
Programming Flash Memory
There are four sections of Flash Memory for programming. 1. 128 configuration bytes. 2. Reset sector (4kB) (not to be confused with the 2kB Boot ROM). 3. Program Memory. 4. Data Memory.
Boot Rom
There is a 2kB Boot ROM that controls operation during serial or parallel programming. Additionally, the Boot ROM routines can be accessed during the user mode if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800H-FFFFH during user mode. In program mode the Boot ROM is located in the first 2kB of Program Memory.
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Flash Programming Mode
There are two programming modes: parallel and serial. The programming mode is selected by the state of the ALE and PSEN signals during power-on reset. Serial programming mode is selected with PSEN = 0 and ALE = 1. Parallel programming mode is selected with PSEN = 1 and ALE = 0 (see Figure 14). If they are both HIGH, the MSC1211 will
operate in normal user mode. Both signals LOW is a reserved mode and is not defined. Programming mode is exited with a power-on reset signal and the normal mode selected. The MSC1211 is shipped with Flash Memory erased (all 1's). Parallel programming methods typically involve a third-party programmer. Serial programming methods typically involve insystem programming. User Application mode allows Flash Program and Data Memory programming. The actual code for Flash programming can not execute from Flash. That code must execute from the Boot ROM or internal (von Neumann) RAM.
MSC1211 PSEL P2[7] AddrHi[6:0] NC P2[6:0] PSEN P1[7:0] Data[7:0] ALE P0[7:0] Cmd[2:0] P3[7:5] Req P3[4] P3[3] P3[2] RST XIN Ack Pass RST CLK AddrLo[7:0]
HOST Flash Programmer
INTERRUPTS
The MSC1211 uses a three-priority interrupt system. As shown in Table IX, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxilliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family. All of the standard interrupts are available.
HARDWARE CONFIGURATION MEMORY
The 128 configuration bytes can only be written during the program mode. The bytes are accessed through SFR registers CADDR (SFR 93H) and CDATA (SFR 94H). Two of the configuration bytes control Flash partitioning and system control. If the security bit is set, these bits can not be changed except with a Mass Erase command that erases all of the Flash Memory including the 128 configuration bytes.
FIGURE 14. Parallel Programming Configuration.
INTERRUPT INTERRUPT/EVENT DVDD Low Voltage/HW Breakpoint AVDD Low Voltage SPI Receive / I2C SPI Transmit Milliseconds Timer ADC Summation Register Seconds Timer External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port 0 Timer 2 Overflow Serial Port 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 Watchdog ADDR 33H 33H 33H 33H 33H 33H 33H 33H 03H 0BH 13H 1BH 23H 2BH 3BH 43H 4BH 53H 5BH 63H NUM 6 6 6 6 6 6 6 6 0 1 2 3 4 5 7 8 9 10 11 12 PRIORITY HIGH 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 LOW
FLAG EDLVB (AIE.0)(1) EBP (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) ESPIT (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE.5)(1) ESUM (AIE.6)(1) ESEC (AIE.7)(1) IE0 (TCON.1)(2) TF0 (TCON.5)(3) IE1 (TCON.3)(2) TF1 (TCON.7)(3) RI_0 (SCON0.0) TI_0 (SCON0.1) TF2 (T2CON.7) RI_1 (SCON1.0) TI_1 (SCON1.1) IE2 (EXIF.4) IE3 (EXIF.5) IE4 (EXIF.6) IE5 (EXIF.7) WDTI (EICON.3)
PRIORITY ENABLE EDLVV (AIE.0)(1) EBP (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) ESPIT (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE .5)(1) ESUM (AIE.6)(1) ESEC (AIE.7)(1) EX0 (IE.0)(4) ET0 (IE.1)(4) EX1 (IE.2)(4) ET1 (IE.3)(4) ES0 (IE.4)(4) ET2 (IE.5)(4) ES1 (IE.6)(4) EX2 (EIE.0)(4) EX3 (EIE.1)(4) EX4 (EIE.2)(4) EX5 (EIE.3)(4) EWDI (EIE.4)(4)
CONTROL N/A N/A N/A N/A N/A N/A N/A N/A PX0 (IP.0) PT0 (IP.1) PX1 (IP.2) PT1 (IP.3) PS0 (IP.4) PT2 (IP.5) PS1 (IP.6) PX2 (IP.0) PX3 (IP.1) PX4 (IP.2) PX5 (IP.3) PWDI (IP.4)
NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs. (4) Globally enabled by EA (IE.7).
TABLE IX. Interrupt Summary.
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Hardware Configuration Register 0 (HCR0)--Accessed Using SFR Registers CADDR and CDATA.
bit 7 CADDR 7FH EPMA bit 6 PML bit 5 RSL bit 4 EBR bit 3 EWDR bit 2 DFSEL2 bit 1 DFSEL1 bit 0 DFSEL0
For access to this register during normal operation, refer to the register descriptions for CADDR and CDATA. EPMA bit 7 Enable Programming Memory Access (Security Bit). 0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done. 1: Fully Accessible (default) PML bit 6 Program Memory Lock. (PML has Priority Over RSL) 0: Enable all Flash Programming Modes in program mode, can be written in UAM. 1: Enable read only for program mode, can't be written in UAM (default). RSL bit 5 Reset Sector Lock. 0: Enable Reset Sector Writing 1: Enable Read Only Mode for Reset Sector (4kB) (default) EBR bit 4 Enable Boot Rom. Boot Rom is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located in Flash Memory. 0: Disable Internal Boot Rom 1: Enable Internal Boot Rom (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL Data Flash Memory Size. (see Table III) bits 2-0 000: Reserved 001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory 010: 16kB, 8kB, or 4kB Data Flash Memory 011: 8kB or 4kB Data Flash Memory 100: 4kB Data Flash Memory 101: 2kB Data Flash Memory 110: 1kB Data Flash Memory 111: No Data Flash Memory (default) The reset sector can be used to provide another method of Flash Memory programming. This will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished.
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Hardware Configuration Register 1 (HCR1)
7 CADDR 7EH DBLSEL1 6 DBLSEL0 5 ABLSEL1 4 ABLSEL0 3 DAB 2 DDB 1 EGP0 0 EGP23
For access to this register during normal operation, refer to the register descriptions for CADDR and CDATA. DBLSEL Digital Brownout Level Select bits 7-6 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) ABLSEL Analog Brownout Level Select bits 5-4 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) DAB bit 3 DDB bit 2 EGP0 bit 1 EGP23 bit 0 Disable Analog Power-Supply Brownout Detection 0: Enable Analog Brownout Detection 1: Disable Analog Brownout Detection (default). Disable Digital Power-Supply Brownout Detection 0: Enable Digital Brownout Detection 1: Disable Digital Brownout Detection (default) Enable General-Purpose I/O for Port 0 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 0 is Used as General-Purpose I/O (default) Enable General-Purpose I/O for Ports 2 and 3 0: Port 2 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 2 and Port3 are Used as General-Purpose I/O (default)
Configuration Memory Programming
Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These bits are nonvolatile and can only be changed through serial and parallel programming. Other peripheral control and status functions, such as ADC configuration timer setup, and Flash control are controlled through the SFRs.
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SFR Definitions (Boldface is unique to the MSC1211)
ADDRESS 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH REGISTER P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON MWS P1 EXIF MPAGE CADDR CDATA MCON BIT 7 P0.7 BIT 6 P0.6 BIT 5 P0.5 BIT 4 P0.4 BIT 3 P0.3 BIT 2 P0.2 BIT 1 P0.1 BIT 0 P0.0 RESET VALUES FFH 07H 00H 00H 00H 00H 00H 30H 00H 00H 00H 00H 00H 00H 01H 00H FFH 08H 00H 00H 00H 00H
0 0 0 0 SMOD 0 1 1 TF1 TR1 TF0 TR0 |---------------------------Timer 1 --------------------------| GATE M1 M0 C/T
0 0 GF1 GF0 IE1 IT1 |--------------------------Timer GATE C/T
0 SEL STOP IDLE IE0 IT0 0 ---------------------------| M1 M0
T2M 0 P1.5 INT5/SCLK/SCK INT4/MISO/SDA INT3/MOSI IE5 IE4 IE3
0 0 P1.7
0 0 P1.6
T1M 0 P1.4 INT2/SS IE2
T0M 0 P1.3 TXD1 1
MD2 0 P1.2 RXD1 0
MD1 0 P1.1 T2EX 0
MD0 MXWS P1.0 T2 0
BPSEL
0
0
RAMMAP
SCON0 SBUF0 SPICON I2CCON SPIDATA I2CDATA SPIRCON I2CSTAT SPITCON I2CGM
SM0_0 SCLK2 START
SM1_0 SCLK1 STOP
SM2_0 SCLK0 ACK
REN_0 FIFO 0
TB8_0 ORDER FAST
RB8_0 MSTR MSTR
TI_0 CPHA SCLS
RI_0 CPOL FILEN
00H 00H 00H 00H
9DH
9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H
SPISTART SPIEND P2 PWMCON PWMLOW TONELOW PWMHI TONEHI PAI AIE AISTAT IE BPCON BPL BPH P0DDRL P0DDRH P1DDRL P1DDRH P3 P2DDRL P2DDRH P3DDRL P3DDRH DACL DACH DACCON IP
RXCNT7 RXFLUSH GCMEN TXCNT7 TXFLUSH STAT7 SCKD7/SAE 1 1 P2.7 PWM7 TDIV7 PWM15 TDIV15 0 ESEC SEC EA BP
RXCNT6
RXCNT5
RXCNT4
RXCNT3
RXCNT2 RXIRQ2 TXCNT2 TXIRQ2 0 SCKD2/SA2
RXCNT1 RXIRQ1 TXCNT1 TXIRQ1 0 SCKD1/SA1
RXCNT0 RXIRQ0 TXCNT0 TXIRQ0 0 SCKD0/SA0
00H
TXCNT6 STAT6 SCKD6/SA6
TXCNT5 CLK_EN STAT5 SCKD5/SA5
TXCNT4 DRV_DLY STAT4 SCKD4/SA4
TXCNT3 DRV_EN STAT3 SCKD3/SA3
00H
P2.6 PWM6 TDIV6 PWM14 TDIV14 0 ESUM SUM ES1 0
P2.5 PPOL PWM5 TDIV5 PWM13 TDIV13 0 EADC ADC ET2 0
P2.4 PWMSEL PWM4 TDIV4 PWM12 TDIV12 0 EMSEC MSEC ES0 0
P2.3 SPDSEL PWM3 TDIV3 PWM11 TDIV11 PAI3 ESPIT SPIT ET1 0
P2.2 TPCNTL2 PWM2 TDIV2 PWM10 TDIV10 PAI2 ESPIR/EI2C SPIR/I2CSI EX1 0
P2.1 TPCNTL1 PWM1 TDIV1 PWM9 TDIV9 PAI1 EALV ALVD ET0 PMSEL
P2.0 TPCNTL0 PWM0 TDIV0 PWM8 TDIV8 PAI0 EDLVB DLVD EX0 EBP
80H 80H FFH 00H 00H 00H
00H 00H 00H 00H 00H
P03H P07H P13H P17H P3.7 RD P23H P27H P33H P37H
P03L P07L P13L P17L P3.6 WR P23L P27L P33L P37L
P02H P06H P12H P16H P3.5 T1 P22H P26H P32H P36H
P02L P06L P12L P16L P3.4 T0 P22L P26L P32L P36L
P01H P05H P11H P15H P3.3 INT1 P21H P25H P31H P35H
P01L P05L P11L P15L P3.2 INT0 P21L P25L P31L P35L
P00H P04H P10H P14H P3.1 TXD0 P20H P24H P30H P34H
P00L P04L P10L P14L P3.0 RXD0 P20L P24L P30L P34L
00H 00H 00H 00H FFH 00H 00H 00H 00H
DSEL7 1
DSEL6 PS1
DSEL5 PT2
DSEL4 PS0
DSEL3 PT1
DSEL2 PX1
DSEL1 PT0
DSEL0 PX0
00H 80H
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ADDRESS B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUES
SCON1 SBUF1
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00H 00H
EWU SYSCLK T2CON RCAP2L RCAP2H TL2 TH2
0 TF2
0 EXF2
DIVMOD1 RCLK
DIVMOD0 TCLK
0 EXEN2
EWUWDT DIV2 TR2
EWUEX1 DIV1 C/T2
EWUEX0 DIV0 CP/RL2
00H 00H 00H 00H 00H 00H 00H
PSW OCL OCM OCH GCL GCM GCH ADMUX EICON ADRESL ADRESM ADRESH ADCON0 ADCON1 ADCON2 ADCON3 ACC SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON EIE HWPC0 HWPC1 HWVER Reserved Reserved FMCON FTCON B PDCON PASEL
CY
AC
F0
RS1
RS0
OV
F1
P LSB
MSB LSB MSB INP3 SMOD1
INP2 1
INP1 EAI
INP0 AI
INN3 WDTI
INN2 0
INN1 0
INN0 0 LSB
MSB -- -- DR7 0 SSCON1
BOD POL DR6 0 SSCON0
EVREF SM1 DR5 0 SCNT2
VREFH SM0 DR4 0 SCNT1
EBUF -- DR3 0 SCNT0
PGA2 CAL2 DR2 DR10 SHF2
PGA1 CAL1 DR1 DR9 SHF1
PGA0 CAL0 DR0 DR8 SHF0
ALVDIS 1
ALVD2 1
ALVD1 1
ALVD0 EWDI
DLVDIS EX5 1
DLVD2 EX4 1
DLVD1 DLVD0 EX3 EX2 MEMORY SIZE
00H 00H 00H 00H 24H 90H 67H 01H 40H 00H 00H 00H 38H x000_0000B 1BH 06H 00H 00H 00H 00H 00H 00H 00H 00H E0H 0000_01xxB 08H 00H 00H 02H A5H 00H 7FH 00H
0 FER3 0 0
PGERA FER2 PDDAC 0
0 FER1 PDI2C PSEN2
FRCM FER0 PDPWM PSEN1
0 FWR3 PDAD PSEN0
BUSY FWR2 PDWDT 0
1 FWR1 PDST ALE1
0 FWR0 PDSPI ALE0
ACLK SRST EIP SECINT MSINT USEC MSECL MSECH HMSEC WDTCON
0 0 1 WRT WRT 0
FREQ6 0 1 SECINT6 MSINT6 0
FREQ5 0 1 SECINT5 MSINT5 FREQ5
FREQ4 0 PWDI SECINT4 MSINT4 FREQ4
FREQ3 0 PX5 SECINT3 MSINT3 FREQ3
FREQ2 0 PX4 SECINT2 MSINT2 FREQ2
FREQ1 0 PX3 SECINT1 MSINT1 FREQ1
FREQ0 RSTREQ PX2 SECINT0 MSINT0 FREQ0
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
03H 00H E0H 7FH 7FH 03H 9FH 0FH 63H 00H
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Port 0 (P0)
7 SFR 80H P0.7 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0 Reset Value FFH
P0.7-0 bits 7-0
Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a generalpurpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is HIGH, and Data when ALE is LOW. When used as a general-purpose I/O, this port drive is selected by P0DDRL and P0DDRH (ACH, ADH). Whether Port 0 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.1) (see SFR CADDR 93H).
Stack Pointer (SP)
7 SFR 81H SP.7 6 SP.6 5 SP.5 4 SP.4 3 SP.3 2 SP.2 1 SP.1 0 SP.0 Reset Value 07H
SP.7-0 bits 7-0
Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset.
Data Pointer Low 0 (DPL0)
7 SFR 82H DPL0.7 6 DPL0.6 5 DPL0.5 4 DPL0.4 3 DPL0.3 2 DPL0.2 1 DPL0.1 0 DPL0.0 Reset Value 00H
DPL0.7-0 bits 7-0
Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer High 0 (DPH0)
7 SFR 83H DPH0.7 6 DPH0.6 5 DPH0.5 4 DPH0.4 3 DPH0.3 2 DPH0.2 1 DPH0.1 0 DPH0.0 Reset Value 00H
DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer Low 1 (DPL1)
7 SFR 84H DPL1.7 6 DPL1.6 5 DPL1.5 4 DPL1.4 3 DPL1.3 2 DPL1.2 1 DPL1.1 0 DPL1.0 Reset Value 00H
DPL1.7-0 bits 7-0
Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer High 1 (DPH1)
7 SFR 85H DPH1.7 6 DPH1.6 5 DPH1.5 4 DPH1.4 3 DPH1.3 2 DPH1.2 1 DPH1.1 0 DPH1.0 Reset Value 00H
DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer Select (DPS)
7 SFR 86H 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SEL Reset Value 00H
SEL bit 0
Data Pointer Select. This bit selects the active data pointer. 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1.
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Power Control (PCON)
7 SFR 87H SMOD 6 0 5 1 4 1 3 GF1 2 GF0 1 STOP 0 IDLE Reset Value 30H
SMOD bit 7 GF1 bit 3 GF0 bit 2 STOP bit 1 IDLE bit 0
Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. General-Purpose User Flag 1. This is a general-purpose flag for software control. General-Purpose User Flag 0. This is a general-purpose flag for software control. Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0. Exit with RESET. Idle Mode Select. Setting this bit will freeze the CPU, Timer 0, 1, and 2, and the UARTs; other peripherals remain active. This bit will always be read as a 0. Exit with AI (A6H) and EWU (C6H) interrupts.
Timer/Counter Control (TCON)
7 SFR 88H TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Reset Value 00H
TF1 bit 7
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current bit 6 count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. 0: INT1 is level triggered. 1: INT1 is edge triggered. Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. 0: INT0 is level triggered. 1: INT0 is edge triggered.
TR1
TF0 bit 5
TR0 bit 4
IE1 bit 3 IT1 bit 2 IE0 bit 3 IT0 bit 2
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Timer Mode Control (TMOD)
7 6 TIMER 1 5 4 3 2 TIMER 0 1 0 Reset Value
SFR 89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
GATE bit 7 C/T bit 6 M1, M0 bits 5-4
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H) is 1. Timer 1 Mode Select. These bits select the operating mode of Timer 1.
M1 0 0 1 1 M0 0 1 0 1 MODE Mode Mode Mode Mode 0: 1: 2: 3: 8-bit counter with 5-bit prescale. 16 bits. 8-bit counter with auto reload. Timer 1 is halted, but holds its count.
GATE bit 3 C/T bit 2 M1, M0 bits 1-0
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). Timer 0 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H) is 1. Timer 0 Mode Select. These bits select the operating mode of Timer 0.
M1 0 0 1 1 M0 0 1 0 1 MODE Mode Mode Mode Mode 0: 1: 2: 3: 8-bit counter with 5-bit prescale. 16 bits. 8-bit counter with auto reload. Timer 1 is halted, but holds its count.
Timer 0 LSB (TL0)
7 SFR 8AH TL0.7 6 TL0.6 5 TL0.5 4 TL0.4 3 TL0.3 2 TL0.2 1 TL0.1 0 TL0.0 Reset Value 00H
TL0.7-0 bits 7-0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
7 SFR 8BH TL1.7 6 TL1.6 5 TL1.5 4 TL1.4 3 TL1.3 2 TL1.2 1 TL1.1 0 TL1.0 Reset Value 00H
TL1.7-0 bits 7-0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
Timer 0 MSB (TH0)
7 SFR 8CH TH0.7 6 TH0.6 5 TH0.5 4 TH0.4 3 TH0.3 2 TH0.2 1 TH0.1 0 TH0.0 Reset Value 00H
TH0.7-0 bits 7-0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
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Timer 1 MSB (TH1)
7 SFR 8DH TH1.7 6 TH1.6 5 TH1.5 4 TH1.4 3 TH1.3 2 TH1.2 1 TH1.1 0 TH1.0 Reset Value 00H
TH1.7-0 bits 7-0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
Clock Control (CKCON)
7 SFR 8EH 0 6 0 5 T2M 4 T1M 3 T0M 2 MD2 1 MD1 0 MD0 Reset Value 01H
T2M bit 5
Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 2 uses a divide by 12 of the crystal frequency. 1: Timer 2 uses a divide by 4 of the crystal frequency. Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be stretched. This allows slower memory or peripherals to be accessed without using ports or manual software intervention. The for RD or WR strobe will be stretched by the specified interval, which will be transparent to the software except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate.
RD or WR STROBE WIDTH (SYS CLKs) 2 4 8 12 16 20 24 28 RD or WR STROBE WIDTH (s) AT 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
T1M bit 4
T0M bit 3
MD2, MD1, MD0 bits 2-0
MD2 0 0 0 0 1 1 1 1
MD1 0 0 1 1 0 0 1 1
MD0 0 1 0 1 0 1 0 1
STRETCH VALUE 0 1 2 3 4 5 6 7
MOVX DURATION 2 3 4 5 6 7 8 9 Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Cycles Cycles (default) Cycles Cycles Cycles Cycles Cycles Cycles
Memory Write Select (MWS)
7 SFR 8FH 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MXWS Reset Value 00H
MXWS bit 0
MOVX Write Select. This allows writing to the internal Flash program memory. 0: No writes are allowed to the internal Flash program memory. 1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on.
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Port 1 (P1)
7 SFR 90H P1.7 INT5/SCLK/SCK 6 P1.6 INT4/MISO/SDA 5 P1.5 INT3/MOSI 4 P1.4 INT2/SS 3 P1.3 TXD1 2 P1.2 RXD1 1 P1.1 T2EX 0 P1.0 T2 Reset Value FFH
P1.7-0 bits 7-0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic `1' before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEH), P1DDRH (SFR AFH). External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. SPI Clock. The master clock for SPI data transfers. Serial Clock. The serial clock for I2C data transfers. External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave. ISDA. For I2C data transfers, this pin is the data line.
INT5/SCLK/SCK bit 7 INT4/MISO/SDA bit 6 INT3/MOSI bit 5 INT2/SS bit 4 TXD1 bit 3 RXD1 bit 2 T2EX bit 1
External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data. External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. Slave Select. During SPI operation, this pin provides the select signal for the slave device. Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0. Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be transferred into the capture registers if enabled by EXEN2 (T2CON.3, SFR C8H). When in auto-reload mode, a 1 to 0 transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2 (T2CON.3, SFR C8H). Time 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment or decrement depending on the timer configuration.
T2 bit 0
External Interrupt Flag (EXIF)
7 SFR 91H IE5 6 IE4 5 IE3 4 IE2 3 1 2 0 1 0 0 0 Reset Value 08H
IE5 bit 7 IE4 bit 6 IE3 bit 5 IE2 bit 4
External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled.
Memory Page (MPAGE)
7 SFR 92H 6 5 4 3 2 1 0 Reset Value 00H
MPAGE bits 7-0
The 8051 uses Port 2 for the upper 8 bits of the external data memory access by MOVX A@RI and MOVX @RI, A instructions. The MSC1211 uses register MPAGE instead of Port 2. To access external data memory using the MOVX A@RI and MOVX @RI, A instructions, the user should preload the upper byte of the address into MPAGE (versus preloading into P2 for the standard 8051).
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Configuration Address Register (CADDR) (write only)
7 SFR 93H 6 5 4 3 2 1 0 Reset Value 00H
CADDR bits 7-0
Configuration Address Register. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration Memory. WARNING: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data Register (CDATA)
7 SFR 94H 6 5 4 3 2 1 0 Reset Value 00H
CDATA bits 7-0
Configuration Data Register. This register will contain the data in the 128 bytes of Flash Configuration Memory that is located at the last written address in the CADDR register. This is a read-only register.
Memory Control (MCON)
7 SFR 95H BPSEL 6 0 5 0 4 -- 3 -- 2 -- 1 -- 0 RAMMAP Reset Value 00H
BPSEL bit 7
Breakpoint Address Selection Write: Select one of two Breakpoint registers: 0 or 1. 0: Select breakpoint register 0. 1: Select breakpoint register 1. Read: Provides the Breakpoint register that created the last interrupt: 0 or 1. Memory Map 1kB extended SRAM. 0: Address is: 0000H-03FFH (default) (Data Memory) 1: Address is 8400H-87FFH (Data and Program Memory)
RAMMAP bit 0
Serial Port 0 Control (SCON0)
7 SFR 98H SM0_0 6 SM1_0 5 SM2_0 4 REN_0 3 TB8_0 2 RB8_0 1 TI_0 0 RI_0 Reset Value 00H
SM0-2 bits 7-5
Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits.
MODE 0 0 1(2) 2 2 3(2) 3(2) SM0 0 0 0 1 1 1 1 SM1 0 0 1 0 0 1 1 SM2 0 1 x 0 1 0 1 FUNCTION Synchronous Synchronous Asynchronous Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication LENGTH 8 bits 8 bits 10 bits 11 bits 11 bits 11 bits 11 bits PERIOD 12 pCLK(1) 4 pCLK(1) Timer 1 or 2 Baud Rate Equation 64 32 64 32 pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD = = = = 0) 1) 0) 1)
Timer 1 or 2 Baud Rate Equation Timer 1 or 2 Baud Rate Equation
NOTE: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the T2CON (C8H) register.
REN_0 bit 4 TB8_0 bit 3 RB8_0 bit 2 TI_0 bit 1
Receive Enable. This bit enables/disables the serial Port 0 received shift register. 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software.
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RI_0 bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
7 SFR 99H 6 5 4 3 2 1 0 Reset Value 00H
SBUF0 bits 7-0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls which is enabled.
7 SFR 9AH SCLK2 6 SCLK1 5 SCLK0 4 FIFO 3 ORDER 2 MSTR 1 CPHA 0 CPOL Reset Value 00H
SCLK bits 7-5
SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
SCLK2 0 0 0 0 1 1 1 1 SCLK1 0 0 1 1 0 0 1 1 SCLK0 0 1 0 1 0 1 0 1 SCK PERIOD tCLK/2 tCLK/4 tCLK/8 tCLK/16 tCLK/32 tCLK/64 tCLK/128 tCLK/256
FIFO bit 4 ORDER bit 3 MSTR bit 2 CPHA bit 1 CPOL bit 0
Enable FIFO in on-chip indirect memory. 0: Both transmit and receive are double buffers 1: Circular FIFO used for transmit and receive bytes Set Bit Order for Transmit and Receive. 0: Most Significant Bits First 1: Least Significant Bits First SPI Master Mode. 0: Slave Mode 1: Master Mode Serial Clock Phase Control. 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK Serial Clock Polarity. 0: SCK idle at logic LOW 1: SCK idle at logic HIGH
I2C Control Register (I2CCON)
7 SFR 9AH START 6 STOP 5 ACK 4 0 3 FAST 2 MSTR 1 SCLS 0 FILEN Reset Value 00H
START bit 7
Start Condition (Master mode). Read: Current status of start condition or repeated start condition. Write: When operating as a master, a start condition is transmitted when the START bit is set to 1. During a data transfer, if the START bit is set, a repeated start is transmitted after the current data transfer is complete. If no transfer is in progress when the START and STOP bits are set simultaneously, a START will be followed by a STOP.
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STOP bit 6
Stop Condition (Master mode). Read: Current status of stop condition. Write: Setting STOP to logic 1 causes a stop condition to be transmitted. When a stop condition is received, hardware clears STOP to logic 0. If both START and STOP are set during a transfer, a stop condition is transmitted followed by a start condition. Acknowledge. Defines the ACK/NACK generation from the master/slave receiver during the acknowledge cycle. 0: A NACK (high level on SDA) is returned during the acknowledge cycle. 1: An ACK (low level on SDA) is returned during the ackowledge cycle. Always set this value to zero. Fast Mode Enable. 0: Standard Mode (100kHz) 1: Fast Mode (400kHz) SPI Master Mode. 0: Slave Mode 1: Master Mode Clock Stretch. 0: No effect 1: Release the clock line. For the slave mode, the clock is stretched for each data transfer. This bit releases the clock. This bit can be set during a transfer to eliminate any clock stretching. Filter Enable. 50ns glitch filter. 0: Filter disabled 1: Filter enabled
ACK bit 5 0 bit 4 FAST bit 3 MSTR bit 2 SCLS bit 1
FILEN bit 0
SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA)
7 SFR 9BH 6 5 4 3 2 1 0 Reset Value 00H
SPIDATA bits 7-0 I2CDATA bits 7-0
SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are separate registers, but both are addressed at this location. I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers are separate registers, but both are addressed at this location.
SPI Receive Control Register (SPIRCON)
7 SFR 9CH RXCNT7 RXFLUSH 6 RXCNT6 5 RXCNT5 4 RXCNT4 3 RXCNT3 2 RXCNT2 RXIRQ2 1 RXCNT1 RXIRQ1 0 RXCNT0 RXIRQ0 Reset Value 00H
RXCNT bits 7-0 RXFLUSH bit 7 RXIRQ bits 2-0
Receive Counter. Read only bits which read the number of bytes in the receive buffer (0 to 128). Flush Receive FIFO. Write only. 0: No Action 1: SPI Receive Buffer Set to Empty Read IRQ Level. Write only.
000 001 010 011 100 101 110 111 Generate Generate Generate Generate Generate Generate Generate Generate IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ when when when when when when when when Receive Receive Receive Receive Receive Receive Receive Receive Count Count Count Count Count Count Count Count = = = = = = = = 1 or more. 2 or more. 4 or more. 8 or more. 16 or more. 32 or more. 64 or more. 128 or more.
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I2C GM Register (I2CGM)
7 SFR 9CH GCMEN 6 5 4 3 2 1 0 Reset Value 00H
GCMEN bit 7
General Call/Multiple Master Enable. Write only. Slave mode: 0 = General call ignored, 1 = General call will be detected Master mode: 0 = Single master, 1 = Multiple master mode
SPI Transmit Control Register (SPITCON)
7 SFR 9DH TXCNT7 TXFLUSH 6 TXCNT6 5 TXCNT5 CLK_EN 4 TXCNT4 DRV_DLY 3 TXCNT3 DRV_EN 2 TXCNT2 TXIRQ2 1 TXCNT1 TXIRQ1 0 TXCNT0 TXIRQ0 Reset Value 00H
TXCNT bits 7-0 TXFLUSH bit 7 CLK_EN bit 5 DRV_DLY bit 4 DRV_EN bit 3
Transmit Counter. Read only bits which read the number of bytes in the transmit buffer (0 to 128). Flush Transmit FIFO. This bit is write only. When set, the SPI transmit pointer is set equal to the FIFO Output pointer. This bit is 0 for a read operation. SCLK Driver Enable. 0: Disable SCLK Driver (Master Mode) 1: Enable SCLK Driver (Master Mode) Drive Delay (refer to DRV_EN bit). 0: Drive Output Immediately 1: Drive Output After Current Byte Transfer Drive Enable.
DRV_DLY 0 0 1 1 DRV_EN 0 1 0 1 MOSI or MISO OUTPUT CONTROL Tristate Immediately Drive Immediately Tristate After the Current Byte Transfer Drive After the Current Byte Transfer
TXIRQ bits 2-0
Transmit IRQ Level. Write only bits.
000 001 010 011 100 101 110 111 Generate Generate Generate Generate Generate Generate Generate Generate IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ when when when when when when when when Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit count count count count count count count count = = = = = = = = 1 or less. 2 or less. 4 or less. 8 or less. 16 or less. 32 or less. 64 or less. 128 or less.
I2C Status Register (I2CSTAT)
7 SFR 9DH 6 5 STAT5 SCKD5/SA5 4 STAT4 SCKD4/SA4 3 STAT3 SCKD3/SA3 2 0 SCKD2/SA2 1 0 SCKD1/SA1 0 0 SCKD0/SA0 Reset Value 00H STAT7 STAT6 SCKD7/SAE SCKD6/SA6
STAT7-3 bit 7-3 SCKD7-0 bit 7-0 SAE bit 7 SA6-0 bit 6-0
Status Code. Read only. Serial Clock Divisor. Write only, master mode. The frequency of the SCL line is set equal to Sysclk/[2 * (SCKD + 1)]. The minimum value for SCKD is 3. Slave Address Enable. Write only, slave mode. In slave mode, if this is set, address recognition is enabled. Slave Address. Write only, slave mode. The address of this device is used in slave mode for address recognition.
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SPI Buffer Start Address (SPISTART)
7 SFR 9EH 1 6 5 4 3 2 1 0 Reset Value 80H
SPISTART bits 6-0 SPITP bits 6-0
SPI FIFO Start Address. Write only. This specifies the start address of the SPI data buffer. This is a circular FIFO that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters. SPI Transmit Pointer. Read Only. This is the FIFO address for SPI transmissions. This is where the next byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data register unless that would make it equal to the SPI Receive pointer.
SPI Buffer End Address (SPIEND)
7 SFR 9FH 1 6 5 4 3 2 1 0 Reset Value 80H
SPIEND bits 6-0 SPIRP bits 6-0
SPI FIFO End Address. Write only. This specifies the end address of the SPI data FIFO. This is a circular buffer that is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address. SPI Receive Pointer. Read Only. This is the FIFO address for SPI received bytes. This is the location of the next byte to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero.
Port 2 (P2)
7 SFR A0H 6 5 4 3 2 1 0 Reset Value FFH
P2 bits 7-0
Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port. During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as generalpurpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).
PWM Control (PWMCON)
7 SFR A1H -- 6 -- 5 PPOL 4 PWMSEL 3 SPDSEL 2 TPCNTL.2 1 TPCNTL.1 0 TPCNTL.0 Reset Value 00H
PPOL bit 5 PWMSEL bit 4 SPDSEL bit 3 TPCNTL bits 2-0
Period Polarity. Specifies the starting level of the PWM pulse. 0: ON Period. PWM Duty register programs the ON period. 1: OFF Period. PWM Duty register programs the OFF period. PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHIGH. 0: Period (must be 0 for TONE mode) 1: Duty Speed Select. 0: 1MHz (the USEC Clock) 1: SYSCLK Tone Generator/Pulse Width Modulation Control.
TPCNTL.2 0 0 0 1 TPCNTL.1 0 0 1 1 TPCNTL.0 0 1 1 1 MODE Disable (default) PWM TONE--Square TONE--Staircase
Tone Low (TONELOW) /PWM Low (PWMLOW)
7 SFR A2H PWM7 TDIV7 6 PWM6 TDIV6 5 PWM5 TDIV5 4 PWM4 TDIV4 3 PWM3 TDIV3 2 PWM2 TDIV2 1 PWM1 TDIV1 0 PWM0 TDIV0 Reset Value 00H
PWMLOW bits 7-0 TDIV7-0 bits 7-0
Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register. Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance for the last 1/4 of this period.
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Tone High (TONEHI)/PWM High (PWMHI)
7 SFR A3H PWM15 TDIV15 6 PWM14 TDIV14 5 PWM13 TDIV13 4 PWM12 TDIV12 3 PWM11 TDIV11 2 PWM10 TDIV10 1 PWM9 TDIV9 0 PWM8 TDIV8 Reset Value 00H
PWMHI bits 7-0 TDIV15-8 bits 7-0
Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register. Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance for the last 1/4 of this period.
Pending Auxiliary Interrupt (PAI)
7 SFR A5H 0 6 0 5 0 4 0 3 PAI3 2 PAI2 1 PAI1 0 PAI0 Reset Value 00H
PAI bits 3-0
Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate interrupt routine. All of these interrupts vector through address 0033H.
PAI3 0 0 0 0 0 0 0 0 1 PAI2 0 0 0 0 1 1 1 1 0 PAI1 0 0 1 1 0 0 1 1 0 PAI0 0 1 0 1 0 1 0 1 0 AUXILIARY INTERRUPT STATUS No Pending Auxiliary IRQ Digital Low Voltage IRQ Pending Analog Low Voltage IRQ Pending SPI Receive IRQ Pending. I2C Status Pending. SPI Transmit IRQ Pending One Millisecond System Timer IRQ Pending Analog to Digital Conversion IRQ Pending Accumulator IRQ Pending One Second System Timer IRQ Pending
Auxiliary Interrupt Enable (AIE)
7 SFR A6H ESEC 6 ESUM 5 EADC 4 EMSEC 3 ESPIT 2 ESPIR/EI2C 1 EALV 0 EDLVB Reset Value 00H
Interrupts are enabled by EICON.4 (SFR D8H). The other interrupts are controlled by the IE and EIE registers. ESEC bit 7 ESUM bit 6 EADC bit 5 EMSEC bit 4 ESPIT bit 3 Enable Seconds Timer Interrupt (lowest priority auxialiary interrupt). Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Seconds Timer Interrupt before masking. Enable Summation Interrupt. Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Summation Interrupt before masking. Enable ADC Interrupt. Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of ADC Interrupt before masking. Enable Millisecond System Timer Interrupt. Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Millisecond System Timer Interrupt before masking. Enable SPI Transmit Interrupt. Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of SPI Transmit Interrupt before masking.
ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt. bit 2 Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of SPI Receive Interrupt or I2C Status Interrupt before masking. EALV bit 1 EDLVB bit 0 Enable Analog Low Voltage Interrupt. Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Analog Low Voltage Interrupt before masking. Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). Write: Set mask bit for this interrupt 0 = masked, 1 = enabled. Read: Current value of Digital Low Voltage or Breakpoint Interrupt before masking.
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Auxiliary Interrupt Status Register (AISTAT)
7 SFR A7H SEC 6 SUM 5 ADC 4 MSEC 3 SPIT 2 SPIR/I2CSI 1 ALVD 0 DLVD Reset Value 00H
SEC bit 7 SUM bit 6 ADC bit 5 MSEC bit 4 SPIT bit 3
Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. Summation Register Interrupt Status Flag. 0: SUM interrupt inactive or masked (if active, it is set inactive by reading the lowest byte of the Summation register). 1: SUM interrupt active. ADC Interrupt Status Flag. 0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register). 1: ADC interrupt active (If active no new data will be written to the Data Output Register). Millisecond System Timer Interrupt Status Flag. 0: MSEC interrupt inactive or masked. 1: MSEC interrupt active. SPI Transmit Interrupt Status Flag. 0: SPI transmit interrupt inactive or masked. 1: SPI transmit interrupt active.
SPIR/I2CSI SPI Receive Interrupt Status Flag. I2C Status Interrupt. bit 2 0: SPI receive or I2CSI interrupt inactive or masked. 1: SPI receive or I2CSI interrupt active. ALVD bit 1 DLVD bit 0 Analog Low Voltage Detect Interrupt Status Flag. 0: ALVD interrupt inactive or masked. 1: ALVD interrupt active. Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI). 0: DLVD interrupt inactive or masked. 1: DLVD interrupt active.
Interrupt Enable (IE)
7 SFR A8H EA 6 ES1 5 ET2 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value 00H
EA bit 7 ES1 bit 6 ET2 bit 5 ES0 bit 4
Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt. 0: Disable all serial Port 1 interrupts. 1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0H) or TI_1 (SCON1.1, SFR C0H) flags. Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt. 0: Disable all Timer 2 interrupts. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8H). Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H) or TI_0 (SCON0.1, SFR 98H) flags.
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ET1 bit 3 EX1 bit 2 ET0 bit 1 EX0 bit 0
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H). Enable External Interrupt 1. This bit controls the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H). Enable External Interrupt 0. This bit controls the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin.
Breakpoint Control (BPCON)
7 SFR A9H BP 6 0 5 0 4 0 3 0 2 0 1 PMSEL 0 EBP Reset Value 00H
Writing to register sets the breakpoint condition specified by MCON, BPL, and BPH. BP bit 7 Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers. Write: 0: No effect. 1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95H). Program Memory Select. Write this bit to select memory for address breakpoints of register selected in MCON (SFR 95H). 0: Break on address in data memory. 1: Break on address in program memory. Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by MCON (SFR 95H). 0: Breakpoint disabled. 1: Breakpoint enabled.
PMSEL bit 1
EBP bit 0
Breakpoint Low (BPL) Address for BP Register Selected in MCON (95H)
7 SFR AAH BPL.7 6 BPL.6 5 BPL.5 4 BPL.4 3 BPL.3 2 BPL.2 1 BPL.1 0 BPL.0 Reset Value 00H
BPL.7-0 bits 7-0
Breakpoint Low Address. The low 8 bits of the 16 bit breakpoint address.
Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95H)
7 SFR ABH BPH.7 6 BPH.6 5 BPH.5 4 BPH.4 3 BPH.3 2 BPH.2 1 BPH.1 0 BPH.0 Reset Value 00H
BPH.7-0 bits 7-0
Breakpoint High Address. The high 8 bits of the 16 bit breakpoint address.
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Port 0 Data Direction Low Register (P0DDRL)
7 SFR ACH P03H 6 P03L 5 P02H 4 P02L 3 P01H 2 P01L 1 P00H 0 P00L Reset Value 00H
P0.3 bits 7-6
Port 0 bit 3 control.
P03H 0 0 1 1 P03L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.2 bits 5-4
Port 0 bit 2 control.
P02H 0 0 1 1 P02L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.1 bits 3-2
Port 0 bit 1 control.
P01H 0 0 1 1 P01L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.0 bits 1-0
Port 0 bit 0 control.
P00H 0 0 1 1 P00L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.1.
Port 0 Data Direction High Register (P0DDRH)
7 SFR ADH P07H 6 P07L 5 P06H 4 P06L 3 P05H 2 P05L 1 P04H 0 P04L Reset Value 00H
P0.7 bits 7-6
Port 0 bit 7 control.
P07H 0 0 1 1 P07L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.6 bits 5-4
Port 0 bit 6 control.
P06H 0 0 1 1 P06L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.5 bits 3-2
Port 0 bit 5 control.
P05H 0 0 1 1 P05L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.4 bits 1-0
Port 0 bit 4 control.
P04H 0 0 1 1 P04L 0 1 0 1 Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
T
O
N
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Port 1 Data Direction Low Register (P1DDRL)
7 SFR AEH P13H 6 P13L 5 P12H 4 P12L 3 P11H 2 P11L 1 P10H 0 P10L Reset Value 00H
P1.3 bits 7-6
Port 1 bit 3 control.
P13H 0 0 1 1 P13L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.2 bits 5-4
Port 1 bit 2 control.
P12H 0 0 1 1 P12L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.1 bits 3-2
Port 1 bit 1 control.
P11H 0 0 1 1 P11L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.0 bits 1-0
Port 1 bit 0 control.
P10H 0 0 1 1 P10L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
Port 1 Data Direction High Register (P1DDRH)
7 SFR AFH P17H 6 P17L 5 P16H 4 P16L 3 P15H 2 P15L 1 P14H 0 P14L Reset Value 00H
P1.7 bits 7-6
Port 1 bit 7 control.
P17H 0 0 1 1 P17L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.6 bits 5-4
Port 1 bit 6 control.
P16H 0 0 1 1 P16L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.5 bits 3-2
Port 1 bit 5 control.
P15H 0 0 1 1 P15L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P1.4 bits 1-0
Port 1 bit 4 control.
P14H 0 0 1 1 P14L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
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Port 3 (P3)
7 SFR B0H P3.7 RD 6 P3.6 WR 5 P3.5 T1 4 P3.4 T0 3 P3.3 INT1 2 P3.2 INT0 1 P3.1 TXD0 0 P3.0 RXD0 Reset Value FFH
P3.7-0 bits 7-0 RD bit 7 WR bit 6 T1 bit 5 T0 bit 4 INT1 bit 3 INT0 bit 2 TXD0 bit 1 RXD0 bit 0
General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic `1' before the pin can be used in its alternate function capacity. External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device. If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a 1 is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory device. If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a 1 is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0.
Port 2 Data Direction Low Register (P2DDRL)
7 SFR B1H P23H 6 P23L 5 P22H 4 P22L 3 P21H 2 P21L 1 P20H 0 P20L Reset Value 00H
P2.3 bits 7-6
Port 2 bit 3 control.
P23H 0 0 1 1 P23L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.2 bits 5-4
Port 2 bit 2 control.
P22H 0 0 1 1 P22L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.1 bits 3-2
Port 2 bit 1 control.
P21H 0 0 1 1 P21L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.0 bits 1-0
Port 2 bit 0 control.
P20H 0 0 1 1 P20L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.1.
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Port 2 Data Direction High Register (P2DDRH)
7 SFR B2H P27H 6 P27L 5 P26H 4 P26L 3 P25H 2 P25L 1 P24H 0 P24L Reset Value 00H
P2.7 bits 7-6
Port 2 bit 7 control.
P27H 0 0 1 1 P27L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.6 bits 5-4
Port 2 bit 6 control.
P26H 0 0 1 1 P26L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.5 bits 3-2
Port 2 bit 5 control.
P25H 0 0 1 1 P25L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P2.4 bits 1-0
Port 2 bit 4 control.
P24H 0 0 1 1 P24L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.1.
Port 3 Data Direction Low Register (P3DDRL)
7 SFR B3H P33H 6 P33L 5 P32H 4 P32L 3 P31H 2 P31L 1 P30H 0 P30L Reset Value 00H
P3.3 bits 7-6
Port 3 bit 3 control.
P33H 0 0 1 1 P33L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P3.2 bits 5-4
Port 3 bit 2 control.
P32H 0 0 1 1 P32L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P3.1 bits 3-2
Port 3 bit 1 control.
P31H 0 0 1 1 P31L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P3.0 bits 1-0
Port 3 bit 0 control.
P30H 0 0 1 1 P30L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
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Port 3 Data Direction High Register (P3DDRH)
7 SFR B4H P37H 6 P37L 5 P36H 4 P36L 3 P35H 2 P35L 1 P34H 0 P34L Reset Value 00H
P3.7 bits 7-6
Port 3 bit 7 control.
P37H 0 0 1 1 P37L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1.
P3.6 bits 5-4
Port 3 bit 6 control.
P36H 0 0 1 1 P36L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1.
P3.5 bits 3-2
Port 3 bit 5 control.
P35H 0 0 1 1 P35L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
P3.4 bits 1-0
Port 3 bit 4 control.
P34H 0 0 1 1 P34L 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input
DAC Low Byte (DACL)
7 SFR B5H 6 5 4 3 2 1 0 Reset Value 00H
DACL7-0 bits 7-0
Least Significant Bit Register for DAC0-3 and DAC Control (0 and 2).
DAC High Byte (DACH)
7 SFR B6H 6 5 4 3 2 1 0 Reset Value 00H
DACH7-0 bits 7-0
Most Significant Byte Register for DAC0-3 and DAC Control (1 and 3).
DAC Select Register (DACSEL)
7 SFR B7H DSEL7 6 DSEL6 5 DSEL5 4 DSEL4 3 DSEL3 2 DSEL2 1 DSEL1 0 DSEL0 Reset Value 00H
DSEL7-0 bits 7-0
DAC and DAC Control Select. The DACSEL register selects which DAC output register or which DAC control register is accessed by the DACL and DACH registers.
DACSEL (B7H) 00H 01H 02H 03H 04H 05H 06H 07H DACH (B6H) DAC0 (high) DAC1 (high) DAC2 (high) DAC3 (high) DACCON1 DACCON3 -- -- DACL (B5H) DAC0 (low) DAC1 (low) DAC2 (low) DAC3 (low) DACCON0 DACCON2 LOADCON -- RESET VALUE 0000H 0000H 0000H 0000H 6363H 0303H --00H --
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DAC0 Control Register (DACCON0)
DACSEL = 04H SFR B5H 7 COR0 6 EOD0 5 IDAC0DIS 4 0 3 0 2 SELREF0 1 DOM0_1 0 DOM0_0 Reset Value 63H
COR0 bit 7
Current Over Range on DAC0 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range exists. 1 = NOP Read: 0 = No current over range for DAC0. 1 = COR0 signal after 3ms filter (EOD0 = 1) or raw signal (EOD0 = 0).
EOD0 bit 6 IDAC0DIS bit 5 Not Used bits 4-3 SELREF0 bit 2 DOM0_1-0 bits 1-0
Enable Over-Current Detection 0 = Disable over-current detection. 1 = Enable over-current detection (default). IDAC0 Disable (for DOM0 = 00) 0 = IDAC on mode for DAC0. 1 = IDAC off mode for DAC0 (default).
Select the Reference Voltage for DAC0 Voltage Reference. 0 = DAC0 VREF = AVDD (default). 1 = DAC0 VREF = internal VREF. DAC Output Mode DAC0.
DOM0 00 01 10 11 OUTPUT MODE FOR DAC0 Normal VDAC output, IDAC controlled by IDAC0DIS bit. Power-Down mode--VDAC output off 1k to AGND, IDAC off. Power-Down mode--VDAC output off 100k to AGND, IDAC off. Power-Down mode--VDAC output off high impedance, IDAC off (default).
DAC1 Control Register (DACCON1)
DACSEL = 04H SFR B6H 7 COR1 6 EOD1 5 IDAC1DIS 4 0 3 0 2 SELREF1 1 DOM1_1 0 DOM1_0 Reset Value 63H
COR1 bit 7
Current Over Range on DAC1 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range exists. 1 = NOP Read: 0 = No current over range for DAC1. 1 = COR1 signal after 3ms filter (EOD1 = 1) or raw signal (EOD1 = 0).
EOD1 bit 6 IDAC1DIS bit 5 Not Used bits 4-3 SELREF1 bit 2 DOM1_1-0 bits 1-0
Enable Over-Current Detection 0 = Disable over-current detection. 1 = Enable over-current detection (default). IDAC1 Disable (for DOM1 = 00) 0 = IDAC on mode for DAC1. 1 = IDAC off mode for DAC1 (default).
Select the Reference Voltage for DAC1 Voltage Reference. 0 = DAC1 VREF = AVDD (default). 1 = DAC1 VREF = internal VREF. DAC Output Mode DAC0.
DOM1 00 01 10 11 OUTPUT MODE FOR DAC1 Normal VDAC output, IDAC controlled by IDAC1DIS bit. Power-Down mode--VDAC output off 1k to AGND, IDAC off. Power-Down mode--VDAC output off 100k to AGND, IDAC off. Power-Down mode--VDAC output off high impedance, IDAC off (default).
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DAC2 Control Register (DACCON2)
DACSEL = 05H SFR B5H 7 0 6 0 5 0 4 0 3 0 2 SELREF2 1 DOM2_1 0 DOM2_0 Reset Value 03H
SELREF2 bit 2 DOM2_1-0 bits 1-0
Select the Reference Voltage for DAC2 Voltage Reference. 0 = DAC2 VREF = AVDD (default). 1 = DAC2 VREF = internal VREF. DAC Output Mode DAC2.
DOM2 00 01 10 11 OUTPUT MODE FOR DAC2 Normal VDAC output. Power-Down mode--VDAC output off 1k to AGND, IDAC off. Power-Down mode--VDAC output off 100k to AGND, IDAC off. Power-Down mode--VDAC output off high impedance, IDAC off (default).
DAC3 Control Register (DACCON3)
DACSEL = 05H SFR B6H 7 0 6 0 5 0 4 0 3 0 2 SELREF3 1 DOM3_1 0 DOM3_0 Reset Value 03H
SELREF3 bit 2 DOM3_1-0 bits 1-0
Select the Reference Voltage for DAC3 Voltage Reference. 0 = DAC2 VREF = AVDD (default). 1 = DAC2 VREF = internal VREF. DAC Output Mode DAC3.
DOM2 00 01 10 11 OUTPUT MODE FOR DAC2 Normal VDAC output. Power-Down mode--VDAC output off 1k to AGND, IDAC off. Power-Down mode--VDAC output off 100k to AGND, IDAC off. Power-Down mode--VDAC output off high impedance, IDAC off (default).
DAC Load Control Register (LOADCON)
DACSEL = 06H SFR B5H 7 D3LOAD1 6 D3LOAD0 5 D2LOAD1 4 D2LOAD0 3 D1LOAD1 2 D1LOAD0 1 D0LOAD1 0 D0LOAD0 Reset Value 00H
D3LOAD1-0 DAC Load Options. bit 7-6 DxLOAD OUTPUT MODE FOR DACx D2LOAD1-0 bit 5-4 D1LOAD1-0 bit 3-2 D0LOAD1-0 bit 1-0
00 01 10 11 Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output). Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next MSEC timer tick. Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next HMSEC timer tick. Sync load: the values contained in the DACxL/DACxH registers will be transferred to the DAC output immediately after 11B is written to this register.
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Interrupt Priority (IP)
7 SFR B8H 1 6 PS1 5 PT2 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value 80H
PS1 bit 6 PT2 bit 5 PS0 bit 4 PT1 bit 3 PX1 bit 2 PT0 bit 1 PX0 bit 0
Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt. 0 = Serial Port 1 priority is determined by the natural priority order. 1 = Serial Port 1 is a high priority interrupt. Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt. 0 = Timer 2 priority is determined by the natural priority order. 1 = Timer 2 priority is a high priority interrupt. Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. External Interrupt 1. This bit controls the priority of external interrupt 1. 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. External Interrupt 0. This bit controls the priority of external interrupt 0. 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt.
Serial Port 1 Control (SCON1)
7 SFR C0H SM0_1 6 SM1_1 5 SM2_1 4 REN_1 3 TB8_1 2 RB8_1 1 TI_1 0 RI_1 Reset Value 00H
SM0-2 bits 7-5
Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits.
MODE 0 0 1(2) 2 2 3(2) 3(2) SM0 0 0 0 1 1 1 1 SM1 0 0 1 0 0 1 1 SM2 0 1 x 0 1 0 1 FUNCTION Synchronous Synchronous Asynchronous Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication LENGTH 8 bits 8 bits 10 bits 11 bits 11 bits 11 bits 11 bits PERIOD 12 pCLK(1) 4 pCLK(1) Timer 1 or 2 Baud Rate Equation 64 32 64 32 pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD = = = = 0) 1) 0) 1)
Timer 1 or 2 Baud Rate Equation Timer 1 or 2 Baud Rate Equation
NOTE: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the SCON register.
REN_1 bit 4 TB8_1 bit 3 RB8_1 bit 2 TI_1 bit 1
Receive Enable. This bit enables/disables the serial Port 1 received shift register. 0 = Serial Port 1 reception disabled. 1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3. 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0. Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be cleared by software to transmit the next byte.
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RI_1 bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must be cleared by software to receive the next byte.
Serial Data Buffer 1 (SBUF1)
7 SFR C1H 6 5 4 3 2 1 0 Reset Value 00H
SBUF1.7-0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive bits 7-0 buffers are separate registers, but both are addressed at this location.
Enable Wake Up (EWU) Waking Up from IDLE Mode
7 SFR C6H -- 6 -- 5 -- 4 -- 3 -- 2 EWUWDT 1 EWUEX1 0 EWUEX0 Reset Value 00H
Auxialiary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT bit 2 EWUEX1 bit 1 EWUEX0 bit 0 Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. 0 = Don't wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. Enable Wake Up External 1. Wake using external interrupt source 1. 0 = Don't wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. Enable Wake Up External 0. Wake using external interrupt source 0. 0 = Don't wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0.
System Clock Divider Register (SYSCLK)
7 SFR C7H 0 6 0 5 DIVMOD1 40 DIVMOD0 3 0 2 DIV2 1 DIV1 0 DIV0 Reset Value 00H
DIVMOD1-0 Clock Divide Mode bits 5-4 Write:
DIVMOD 00 01 10 DIVIDE MODE Normal mode (default, no divide) Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition.. Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Reserved
11
Read:
DIVMOD 00 01 10 11 DIVISION MODE STATUS No divide Divider is in Immediate mode Divider is in Delay mode Reserved
NOTE: Do not clear the DIVMOD register to exit Immediate or Delay modes. Exit these modes only through the appropriate interrupt (the interrupt can be either normally generated or software generated).
DIV2-0 bit 2-0
Divide Mode
DIV 000 001 010 011 100 101 110 111 DIVISOR Divide Divide Divide Divide Divide Divide Divide Divide by by by by by by by by 2 (default) 4 8 16 32 1024 2048 4096
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Timer 2 Control (T2CON)
7 SFR C8H TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 Reset Value 00H
TF2 bit 7 EXF2 bit 6 RCLK bit 5
Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFH. It must be cleared by software. TF2 will only be set if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on the EXEN2 (T2CON.3) bit. If set by a negative transition, this flag must be cleared to 0 by software. Setting this bit in software will force a timer interrupt if enabled. Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3. 0 = Timer 1 overflow is used to determine receiver baud rate for UART0. 1 = Timer 2 overflow is used to determine receiver baud rate for UART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. Transmit Clock Flag. This bit determines the serial Port 0 timerbase when transmitting data in serial modes 1 or 3. 0 = Timer 1 overflow is used to determine transmitter baud rate for UART0. 1 = Timer 2 overflow is used to determine transmitter baud rate for UART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating baud rates for the serial port. 0 = Timer 2 will ignore all external events at T2EX. 1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin. Timer 1 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode. 0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5). 1 = Timer 2 will count negative transitions on the T2 pin (P1.0). Capture/Reload Select. This bit determines whether the capture or reload function will be used for Timer 2. If either RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each overflow. 0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1. 1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1.
TCLK bit 4
EXEN2 bit 3
TR2 bit 2
C/T2 bit 1
CP/RL2 bit 0
Timer 2 Capture LSB (RCAP2L)
7 SFR CAH 6 5 4 3 2 1 0 Reset Value 00H
RCAP2L bits 7-0
Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
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Timer 2 Capture MSB (RCAP2H)
7 SFR CBH 6 5 4 3 2 1 0 Reset Value 00H
RCAP2H bits 7-0
Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
Timer 2 LSB (TL2)
7 SFR CCH 6 5 4 3 2 1 0 Reset Value 00H
TL2 bits 7-0
Timer 2 LSB. This register contains the least significant byte of Timer 2.
Timer 2 MSB (TH2)
7 SFR CDH 6 5 4 3 2 1 0 Reset Value 00H
TH2 bits 7-0
Timer 2 MSB. This register contains the most significant byte of Timer 2.
Program Status Word (PSW)
7 SFR D0H CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0 P Reset Value 00H
CY bit 7 AC bit 6 F0 bit 5 RS1, RS0 bits 4-3
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations. Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), or a borrow (during substraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic operations. User Flag 0. This is a bit-adressable, general-purpose flag for software control. Register Bank Select 1-0. These bits select which register bank is addressed during register accesses.
RS1 0 0 1 1 RS0 0 1 0 1 REGISTER BANK 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH
OV bit 2 F1 bit 1 P bit 0
Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. User Flag 1. This is a bit-addressable, general-purpose flag for software control. Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and cleared to 0 on even parity.
ADC Offset Calibration Register Low Byte (OCL)
7 SFR D1H 6 5 4 3 2 1 0 Reset Value 00H
OCL bits 7-0
ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
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ADC Offset Calibration Register Middle Byte (OCM)
7 SFR D2H 6 5 4 3 2 1 0 Reset Value 00H
OCM bits 7-0
ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Offset Calibration Register High Byte (OCH)
7 SFR D3H 6 5 4 3 2 1 0 Reset Value 00H
OCH bits 7-0
ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Gain Calibration Register Low Byte (GCL)
7 SFR D4H 6 5 4 3 2 1 0 Reset Value 5AH
GCL bits 7-0
ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Register Middle Byte (GCM)
7 SFR D5H 6 5 4 3 2 1 0 Reset Value ECH
GCM bits 7-0
ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Register High Byte (GCH)
7 SFR D6H 6 5 4 3 2 1 0 Reset Value 5FH
GCH bits 7-0
ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Multiplexer Register (ADMUX)
7 SFR D7H INP3 6 INP2 5 INP1 4 INP0 3 INN3 2 INN2 1 INN1 0 INN0 Reset Value 01H
INP3-0 bits 7-4
Input Multiplexer Positive Channel. This selects the positive signal input.
INP3 0 0 0 0 0 0 0 0 1 1 INP2 0 0 0 0 1 1 1 1 0 1 INP1 0 0 1 1 0 0 1 1 0 1 INP0 0 1 0 1 0 1 0 1 0 1 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX = FFH)
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INN3-0 bits 3-0
Input Multiplexer Negative Channel. This selects the negative signal input.
INN3 0 0 0 0 0 0 0 0 1 1 INN2 0 0 0 0 1 1 1 1 0 1 INN1 0 0 1 1 0 0 1 1 0 1 INN0 0 1 0 1 0 1 0 1 0 1 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX = FFH)
Enable Interrupt Control (EICON)
7 SFR D8H SMOD1 6 1 5 EAI 4 AI 3 WDTI 2 0 1 0 0 0 Reset Value 40H
SMOD1 bit 7 EAI bit 5
Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and identified by SFR registers PAI (SFR A5H), AIE (SFR A6H), and AISTAT (SFR A7H). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected.
AI bit 4
WDTI bit 3
ADC Results Register Low Byte (ADRESL)
7 SFR D9H 6 5 4 3 2 1 0 Reset Value 00H
ADRESL bits 7-0
The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC Converter Results. Reading from this register clears the ADC interrupt.
ADC Results Register Middle Byte (ADRESM)
7 SFR DAH 6 5 4 3 2 1 0 Reset Value 00H
ADRESM bits 7-0
The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC Converter Results.
ADC Results Register High Byte (ADRESH)
7 SFR DBH 6 5 4 3 2 1 0 Reset Value 00H
ADRESH bits 7-0
The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC Converter Results.
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ADC Control Register 0 (ADCON0)
7 SFR DCH -- 6 BOD 5 EVREF 4 VREFH 3 EBUF 2 PGA2 1 PGA1 0 PGA0 Reset Value 30H
BOD bit 6
Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to save power and reduce noise. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. 0 = REFOUT/REF IN+ is 1.25V. 1 = REFOUT/REF IN+ is 2.5V (default). Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128.
PGA2 0 0 0 0 1 1 1 1 PGA1 0 0 1 1 0 0 1 1 PGA0 0 1 0 1 0 1 0 1 GAIN 1 (default) 2 4 8 16 32 64 128
EVREF bit 5
VREFH bit 4 EBUF bit 3
PGA2-0 bits 2-0
ADC Control Register 1 (ADCON1)
7 SFR DDH -- 6 POL 5 SM1 4 SM0 3 -- 2 CAL2 1 CAL1 0 CAL0 Reset Value x000 0000B
POL bit 6
Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar.
POL 0 ANALOG INPUT +FSR ZERO -FSR +FSR ZERO -FSR DIGITAL OUTPUT 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
1
SM1-0 bits 5-4
Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics.
SM1 0 0 1 1 SM0 0 1 0 1 SETTLING MODE Auto Fast Settling Filter Sinc2 Filter Sinc3 Filter
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CAL2-0 bits 2-0
Calibration Mode Control Bits.
CAL2 0 0 0 0 1 1 1 1 CAL1 0 0 1 1 0 0 1 1 CAL0 0 1 0 1 0 1 0 1 CALIBRATION MODE No Calibration (default) Self Calibration, Offset and Gain Self Calibration, Offset Only Self Calibration, Gain Only System Calibration, Offset Only System Calibration, Gain Only Reserved Reserved
Read Value--000B.
ADC Control Register 2 (ADCON2)
7 SFR DEH DR7 6 DR6 5 DR5 4 DR4 3 DR3 2 DR2 1 DR1 0 DR0 Reset Value 1BH
DR7-0 bits 7-0
Decimation Ratio LSB.
ADC Control Register 3 (ADCON3)
7 SFR DFH -- 6 -- 5 -- 4 -- 3 -- 2 DR10 1 DR9 0 DR8 Reset Value 06H
DR10-8 bits 2-0
Decimation Ratio Most Significant 3 Bits. The output data rate = (ACLK + 1)/ 64/Decimation Ratio.
Accumulator (A or ACC)
7 SFR E0H ACC.7 6 ACC.6 5 ACC.5 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1 0 ACC.0 Reset Value 00H
ACC.7-0 bits 7-0
Accumulator. This register serves as the accumulator for arithmetic and logic operations.
Summation/Shifter Control (SSCON)
7 SFR E1H SSCON1 6 SSCON0 5 SCNT2 4 SCNT1 3 SCNT0 2 SHF2 1 SHF1 0 SHF0 Reset Value 00H
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1. SSCON1-0 Summation/Shift Control. bits 7-6 SSCON1 SSCON0 SCNT2
0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 x Note (1) Note (1)
SCNT1 0 1 0 x Note (1) Note (1)
SCNT0 0 0 0 x Note (1) Note (1)
SHF2 0 0 0 Note (1) x Note (1)
SHF1 0 0 0 Note (1) x Note (1)
SHF0 0 0 0 Note (1) x Note (1)
DESCRIPTION Clear Summation Register CPU Summation on Write to SUMR0 CPU Subtraction on Write to SUMR0 CPU Shift Only ADC Summation Only ADC Summation Completes then Shift Completes
NOTES: (1) Refer to register bit definition.
SCNT2-0 bits 5-3
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the SUMR0 register clears the interrupt.
SCNT2 0 0 0 0 1 1 1 1 SCNT1 SCNT0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SUMMATION COUNT 2 4 8 16 32 64 128 256
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SHF2-0 bits 2-0
Shift Count.
SHF2 0 0 0 0 1 1 1 1 SHF1 0 0 1 1 0 0 1 1 SHF0 0 1 0 1 0 1 0 1 SHIFT 1 2 3 4 5 6 7 8 DIVIDE 2 4 8 16 32 64 128 256
Summation Register 0 (SUMR0)
7 SFR E2H 6 5 4 3 2 1 0 Reset Value 00H
SUMR0 bits 7-0
Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. Write: will cause values in SUMR3-0 to be added to the summation register. Read: will clear the Summation Count Interrupt.
Summation Register 1 (SUMR1)
7 SFR E3H 6 5 4 3 2 1 0 Reset Value 00H
SUMR1 bits 7-0
Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15.
Summation Register 2 (SUMR2)
7 SFR E4H 6 5 4 3 2 1 0 Reset Value 00H
SUMR2 bits 7-0
Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23.
Summation Register 3 (SUMR3)
7 SFR E5H 6 5 4 3 2 1 0 Reset Value 00H
SUMR3 bits 7-0
Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31.
Offset DAC Register (ODAC)
7 SFR E6H 6 5 4 3 2 1 0 Reset Value 00H
ODAC bits 7-0
Offset DAC Register. This register will shift the input by up to half of the ADC input range. The least significant bit is equal to the input voltage range divided by 256. The input range will depend on the setting of the PGA. The ODAC is a signed magnitude register with bit 7 providing the sign of the offset and bits 6-0 providing the magnitude. Offset DAC Sign bit. 0 = Positive 1 = Negative Offset =
VREF ODAC[6 : 0] bit 7 * * (-1) 2 * PGA 127
bit 7
bit 6-0
NOTE: The offset must be used after calibration or the calibration will nullify the effects.
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Low Voltage Detect Control (LVDCON)
7 SFR E7H ALVDIS 6 ALVD2 5 ALVD1 4 ALVD0 3 DLVDIS 2 DLVD2 1 DLVD1 0 DLVD0 Reset Value 00H
ALVDIS bit 7 ALVD2-0 bits 6-4
Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage. 1 = Disable Detection of Low Analog Supply Voltage. Analog Voltage Detection Level.
ALVD2 0 0 0 0 1 1 1 1 ALVD1 0 0 1 1 0 0 1 1 ALVD0 0 1 0 1 0 1 0 1 VOLTAGE LEVEL AVDD 2.7V (default) AVDD 3.0V AVDD 3.3V AVDD 4.0V AVDD 4.2V AVDD 4.5V AVDD 4.7V External Voltage AIN7 Compared to 1.2V
DLVDIS bit 3
Digital Low Voltage Detect Disable. 0 = Enable Detection of Low Digital Supply Voltage. 1 = Disable Detection of Low Digital Supply Voltage. Digital Voltage Detection Level.
DLVD2 0 0 0 0 1 1 1 1 DLVD1 0 0 1 1 0 0 1 1 DLVD0 0 1 0 1 0 1 0 1 VOLTAGE LEVEL DVDD 2.7V (default) DVDD 3.0V DVDD 3.3V DVDD 4.0V DVDD 4.2V DVDD 4.5V DVDD 4.7V External Voltage AIN6 Compared to 1.2V
DLVD2-0 bits 2-0
Extended Interrupt Enable (EIE)
7 SFR E8H 1 6 1 5 1 4 EWDI 3 EX5 2 EX4 1 EX3 0 EX2 Reset Value E0H
EWDI bit 4 EX5 bit 3 EX4 bit 2 EX3 bit 1 EX2 bit 0
Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by the WDTCON (SFR FFH) and PDCON (SFR F1H) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer External Interrupt 5 Enable. This bit enables/disables external interrupt 5. 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2
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Hardware Product Code Register 0 (HWPC0)
7 SFR E9H HWPC0.7 6 HWPC0.6 5 HWPC0.5 4 HWPC0.4 3 HWPC0.3 2 1 1 0 Reset Value 0000_001xxB MEMORY SIZE
HWPC0.7-0 bits 7-0
Hardware Product Code LSB. Read only.
MEMORY SIZE 0 0 1 1 0 1 0 1
MODEL MSC1211Y2 MSC1211Y3 MSC1211Y4 MSC1211Y5
FLASH MEMORY 4kB 8kB 16kB 32kB
Hardware Product Code Register 1 (HWPC1)
7 SFR EAH 6 5 4 3 1 2 1 0 Reset Value 08H
HWPC1.7-0 bits 7-0
Hardware Product Code MSB. Read only.
Hardware Version Register (HDWVER)
7 SFR EBH 6 5 4 3 2 1 0 Reset Value
Flash Memory Control (FMCON)
7 SFR EEH 0 6 PGERA 5 0 4 FRCM 3 0 2 BUSY 1 1 0 0 Reset Value 02H
PGERA bit 6 FRCM bit 4 BUSY bit 2
Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode Frequency Control Mode. The bypass is only used for slow clocks to save power. 0 = Bypass (default) 1 = Use Delay Line. Saves power (Recommended). Write/Erase BUSY Signal. 0 = Idle or Available 1 = Busy
Flash Memory Timing Control Register (FTCON)
7 SFR EFH FER3 6 FER2 5 FER1 4 FER0 3 FWR3 2 FWR2 1 FWR1 0 FWR0 Reset Value A5H
Refer to Flash Timing Characteristics FER3-0 bits 7-4 FWR3-0 bits 3-0 Set Erase. Flash Erase Time = (1 + FER) * (MSEC + 1) * tCLK. 11ms industrial temperature range. 5ms commercial temperature range. Set Write. Flash Write Time = (1 + FWR) * (USEC + 1) * 5 * tCLK. 30s to 40s.
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B Register (B)
7 SFR F0H B.7 6 B.6 5 B.5 4 B.4 3 B.3 2 B.2 1 B.1 0 B.0 Reset Value 00H
B.7-0 bits 7-0
B Register. This register serves as a second accumulator for certain arithmetic operations.
Power-Down Control Register (PDCON)
7 SFR F1H 0 6 PDDAC 5 PDI2C 4 PDPWM 3 PDAD 2 PDWDT 1 PDST 0 PDSPI Reset Value 7FH
Turning peripheral modules off puts the MSC1211 in the lowest power mode. PDDAC bit 6 PDI2C bit 5 PDPWM bit 4 PDAD bit 3 PDWDT bit 2 PDST bit 1 PDSPI bit 0 Pulse Width Module Control. 0 = DACs On 1 = DACs Power Down I2C Control. 0 = I2C On (the state is undefined if PDSPI is also = 0) 1 = I2C Power Down Pulse Width Module Control. 0 = PWM On 1 = PWM Power Down ADC Control. 0 = ADC On 1 = ADC, VREF, Summation registers, and Analog Brownout are powered down. Analog current = 0. Watchdog Timer Control. 0 = Watchdog Timer On 1 = Watchdog Timer Power Down System Timer Control. 0 = System Timer On 1 = System Timer Power Down SPI System Control. 0 = SPI System On (the state is undefined if PDI2C is also = 0) 1 = SPI System Power Down
PSEN/ALE Select (PASEL)
7 SFR F2H 0 6 0 5 PSEN2 4 PSEN1 3 PSEN0 2 0 1 ALE1 0 ALE0 Reset Value 00H
PSEN2-0 bits 5-3
PSEN Mode Select.
PSEN2 0 0 1 1 1 PSEN1 0 1 0 1 1 PSEN0 X X X 0 1 PSEN CLK ADC MODCLK LOW HIGH
ALE1-0 bits 1-0
ALE Mode Select.
ALE1 0 1 1 ALE0 X 0 1 ALE LOW HIGH
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Analog Clock (ACLK)
7 SFR F6H 0 6 FREQ6 5 FREQ5 4 FREQ4 3 FREQ3 2 FREQ2 1 FREQ1 0 FREQ0 Reset Value 03H
FREQ6-0 bits 6-0
Clock Frequency - 1. This value + 1 divides the system clock to create the ADC clock. ACLK frequency = fCLK/(FREQ + 1) fMOD = fCLK/(FREQ + 1)/64 Data Rate = fMOD/Decimation
System Reset Register (SRST)
7 SFR F7H 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSTREQ Reset Value 00H
RSTREQ bit 0
Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset.
Extended Interrupt Priority (EIP)
7 SFR F8H 1 6 1 5 1 4 PWDI 3 PX5 2 PX4 1 PX3 0 PX2 Reset Value E0H
PWDI bit 4 PX5 bit 3 PX4 bit 2 PX3 bit 1 PX2 bit 0
Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority.
Seconds Timer Interrupt (SECINT)
7 SFR F9H WRT 6 SECINT6 5 SECINT5 4 SECINT4 3 SECINT3 2 SECINT2 1 SECINT1 0 SECINT0 Reset Value 7FH
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6-0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6-0 Seconds Interrupt = (1 + SEC) * (HMSEC + 1) * (MSEC + 1) * tCLK.
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Milliseconds Interrupt (MSINT)
7 SFR FAH WRT 6 MSINT6 5 MSINT5 4 MSINT4 3 MSINT3 2 MSINT2 1 MSINT1 0 MSINT0 Reset Value 7FH
The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register will clear the interrupt. WRT bit 7 MSINT6-0 bits 6-0 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. Seconds Count. Normal operation would use 1ms as the clock interval. MS Interrupt Interval = (1 + MSINT) * (MSEC + 1) * tCLK
One Microsecond Register (USEC)
7 SFR FBH 0 6 0 5 0 4 FREQ4 3 FREQ3 2 FREQ2 1 FREQ1 0 FREQ0 Reset Value 03H
FREQ4-0 bits 4-0
Clock Frequency - 1. This value + 1 divides the system clock to create a 1s Clock. USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH).
One Millisecond Low Register (MSECL)
7 SFR FCH MSECL7 6 MSECL6 5 MSECL5 4 MSECL4 3 MSECL3 2 MSECL2 1 MSECL1 0 MSECL0 Reset Value 9FH
MSECL7-0 bits 7-0
One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock. 1ms Clock = (MSECH * 256 + MSECL + 1) * tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFH).
One Millisecond High Register (MSECH)
7 SFR FDH MSECH7 6 MSECH6 5 MSECH5 4 MSECH4 3 MSECH3 2 MSECH2 1 MSECH1 0 MSECH0 Reset Value 0FH
MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7-0 1ms = (MSECH * 256 + MSECL + 1) * tCLK.
One Hundred Millisecond Register (HMSEC)
7 SFR FEH HMSEC7 6 HMSEC6 5 HMSEC5 4 HMSEC4 3 HMSEC3 2 HMSEC2 1 HMSEC1 0 HMSEC0 Reset Value 63H
HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7-0 100ms = (MSECH * 256 + MSECL + 1) * (HMSEC + 1) * tCLK.
Watchdog Timer Register (WDTCON)
7 SFR FFH EWDT 6 DWDT 5 RWDT 4 WDCNT4 3 WDCNT3 2 WDCNT2 1 WDCNT1 0 WDCNT0 Reset Value 00H
EWDT bit 7 DWDT bit 6 RWDT bit 5 WDCNT4-0 bits 4-0
Enable Watchdog (R/W). Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. Disable Watchdog (R/W). Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. Reset Watchdog (R/W). Write 1/Write 0 sequence restarts the Watchdog Counter. Watchdog Count (R/W). Watchdog expires in (WDCNT + 1) * HMSEC to (WDCNT + 2) * HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count.
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PACKAGE DRAWING PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17
MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
0,08 M
49
32
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 16
1,20 MAX
0,08 4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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