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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Low Voltage 1:18 Clock Distribution Chip
The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 150ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point the reader is referred to the MPC9109.
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
* * * * * *
LVPECL or LVCMOS Clock Input 2.5V LVCMOS Outputs for Pentium II Microprocessor Support 150ps Maximum Output-to-Output Skew Maximum Output Frequency of 250MHz 32-Lead LQFP Packaging Dual or Single Supply Device: * Dual VCC Supply Voltage, 3.3V Core and 2.5V Output * Single 3.3V VCC Supply Voltage for 3.3V Outputs * Single 2.5V VCC Supply Voltage for 2.5V I/O
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-02
With a low output impedance (20), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20 output impedance the 940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet. The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistor so they can be left open if unused. The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
01/01
(c) Motorola, Inc. 2001
1
REV 3
MPC940L
LOGIC DIAGRAM
PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel (Internal Pulldown) 0 1 16 Q1-Q16 Q17
Q0
Pinout: 32-Lead TQFP (Top View)
VCCI GND 17 16 15 14 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 Q10 19 Q11 18
Q6
Q7
Q8
24 GNDO Q5 Q4 Q3 VCCO Q2 Q1 Q0 25 26 27 28 29 30 31 32 1
23
22
21
Q9 20
FUNCTION TABLE
LVCMOS_CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK
MPC940L
13 12 11 10 9
POWER SUPPLY VOLTAGES
Supply Pin VCCI VCCO
Voltage Level
2.5V or 3.3V 5% 2.5V or 3.3V 5%
2
3
4
5
6
7
8
LVCMOS_CLK_Sel
LVCMOS_CLK
PECL_CLK
PECL_CLK
VCCI
GNDO
PIN CONFIGURATIONS
Pin PECL_CLK Input PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL Q0-Q17 VCCO VCCI GNDO GNDI Input Input Output LVCMOS LVCMOS LVCMOS Supply Supply Supply Supply Alternative Reference Clock Input Selects Clock Source Clock Outputs Output Positive Power Supply Core Positive Power Supply Output Negative Power Supply Core Negative Power Supply LVPECL Reference Clock Input
VCCO
GNDI
I/O
Type
Function
MOTOROLA
2
TIMING SOLUTIONS DL207 -- Rev 0
MPC940L
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VDD + 0.3 20 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
DC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 3.3V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.4 2.4 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF per output IOH = -20mA IOH = 20mA Condition
W
mA
AC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 3.3V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK 2.0 1.8 2.0 1.8 2.7 2.5 2.9 2.4 Min Typ Max 250 3.4 3.0 3.7 3.2 150 150 1.4 1.2 1.7 1.4 850 750 45 40 50 50 55 60 1.1 Unit MHz ns ns ps ns ns ps % % ns Note 1. Notes 1., 2. Notes 1., 2. Notes 1., 3. Input DC = 50% Input DC = 50% 0.5 - 2.4 V Note 1. Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle
PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz
tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew.
TIMING SOLUTIONS DL207 -- Rev 0
3
MOTOROLA
MPC940L
DC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 10 23 0.5 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.4 1.8 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF per output IOH = -20mA IOH = 20mA Condition
W
mA
AC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK 2.0 1.7 2.0 1.8 2.8 2.5 2.9 2.5 Min Typ Max 250 3.5 3.0 3.8 3.3 150 150 1.5 1.3 1.8 1.5 850 750 45 40 50 50 55 60 1.2 Unit MHz ns ns ps ns ns ps % % ns Note 1. Notes 1., 2. Notes 1., 2. Notes 1., 3. Input DC = 50% Input DC = 50% 0.5 - 1.8 V Note 1. Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle
PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz
tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew.
MOTOROLA
4
TIMING SOLUTIONS DL207 -- Rev 0
MPC940L
DC CHARACTERISTICS (TA = 0 to 70C, VCCI = 2.5V 5%; VCCO = 2.5V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCC-1.0 1.8 0.5 200 Min 2.0 Typ Max VCCI 0.8 1000 VCC-0.6 Unit V V mV V V V A pF pF per output IOH = -12mA IOH = 12mA Condition
W
mA
AC CHARACTERISTICS (TA = 0 to 70C, VCCI = 2.5V 5%; VCCO = 2.5V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150MHz CMOS_CLK 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK 2.6 2.3 2.8 2.3 4.0 3.1 3.8 3.1 Min Typ Max 200 5.2 4.0 5.0 4.0 200 200 2.6 1.7 2.2 1.7 1.2 1.0 45 40 50 50 55 60 1.2 Unit MHz ns ns ps ns ns ns % % ns Note 1. Notes 1., 2. Notes 1., 2. Notes 1., 3. Input DC = 50% Input DC = 50% 0.5 - 1.8 V Note 1. Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle
PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz
tr, tf Output Rise/Fall Time 0.3 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, Includes output skew. 3. For a specific temperature and voltage, Includes output skew.
TIMING SOLUTIONS DL207 -- Rev 0
5
MOTOROLA
MPC940L
MPC940L DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 1. LVCMOS_CLK MPC940L AC test reference for Vcc = 3.3V and Vcc = 2.5V
MPC940L DUT Differential Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 2. PECL_CLK MPC940L AC test reference for Vcc = 3.3V and Vcc = 2.5V
VCC VCC VCC VCC
PECL_CLK PECL_CLK VPP VCMR VCC VCC
LVCMOS_CLK
B2 B2
GND
Q tPD
B2
Q
GND tPD
GND
Figure 3. Propagation delay (tPD) test reference
VCC VCC tP T0 DC = tP /T0 x 100%
Figure 4. LVCMOS Propagation delay (tPD) test reference
VCC VCC
B2
B2 B2
GND
GND VOH VCC
GND tSK(O)
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device
Figure 5. Output Duty Cycle (DC)
VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V
Figure 6. Output-to-output Skew tSK(O)
VCC=3.3V 2.0 0.8 tF tR VCC=2.5V 1.7V 0.7V
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
MOTOROLA
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TIMING SOLUTIONS DL207 -- Rev 0
MPC940L
OUTLINE DIMENSIONS
FA SUFFIX QFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS DL207 -- Rev 0
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
7
-T-, -U-, -Z- MOTOROLA
EE EE EE
MPC940L
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MOTOROLA
8
TIMING SOLUTIONS DL207 -- Rev MPC940L/D0

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