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| 10/97 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. General Information 1 - General Information 1*1 Introduction This document is an operation guide for the MPC8XXFADS board. It contains operational, functional and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/ w and h/w development around the MPC8XX family processors. Using its on-board resources and its associated debugger, a developer is able to download his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a desired system with the MPC8XX processor. 1*2 MPC8XX Family Support t t t t t t t The MPC8XXFADS supports the following MPC8XX family members: MPC801 MPC821 MPC823 MPC850 MPC860 MPC860SAR MPC860T 1*3 * * * * * * * * * Abbreviations' List FADSB - the MPC8XXFADS, the subject of this document. UPM - User Programmable Machine GPCM - General Purpose Chip-select Machine GPL - General Purpose Line (associated with the UPM) I/R - Infra-Red BCSR - Board Control & Status Register. ZIF - Zero Input Force BGA - Ball Grid Array SIMM - Single In-line Memory Module 1*4 * * A. Either on or off-board. B. Not to be mistaken for the M683XX Family Ads MOTOROLA PR Related Documentation MPC8XX User's Manuals. ADI Board Specification. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 1 AR Y This board could also be used as a demonstration tool, i.e., application s/w may be burnedA into its flash memory and ran in exhibitions etc`. General Information 1*5 SPECIFICATIONS TABLE 1-1. MPC8XXFADS Specifications CHARACTERISTICS SPECIFICATIONS +5Vdc @ 1.7 A (typical), 3 A (maximum) +12Vdc - @1A. MPC8XX running upto @ 50 MHz 4 GigaBytes The MPC8XXFADS specifications are given in TABLE 1-1. Power requirements (no other boards attached) Microprocessor Addressing Total address range: Flash Memory Dynamic RAM Synchronous DRAM Operating temperature Storage temperature Relative humidity Dimensions: Length Width Thickness 2 MByte, 32 bits wide expandable to 8 MBytes 4 MByte, 32 bits wide EDO SIMM Support for up to 32 MByte, EDO or FPM SIMM 4 MBytes, organized as 1 Meg X 32 bit. 0OC - 30OC 2 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 9.173" (233 mm) 6.3" (160 mm) 0.063" (1.6 mm) -25OC to 85OC 5% to 90% (non-condensing) AR Y MOTOROLA General Information 1*6 MPC8XXFADS Features t t 4 MByte, Unbuffered, Synchronous Dram On-Board. 4 MByte EDO 60nsec delay DRAM SIMM. Support for 4 - 32 MByte FPM or EDO Dram SIMM, with Automatic Dram SIMM identification. 16 Bit Data-Bus Width Support. 2 MByte Flash SIMM. Support for upto 8 MByte, 5V or 12V Programmable, with Automatic Flash SIMM identification. Memory Disable Option for each local memory map slaves. Board Control & Status Register - BCSR, Controlling Board's Operation. Programmable Hard-Reset Configuration via BCSR. t t t t t 5V only PCMCIA Socket With Full Buffering, Power Control and Port Disable Option. Complies with PCMCIA 2.1+ Standard. Module Enable Indications. t t t t t t t t t t Fast-IrDA (4MBps) Port with Stand-By Mode. Dual RS232 port with Low-Power Option per each port. On - Board Debug Port Controller with ADI I/F. MPC8XXFADS Serving as Debug Station for Target System option. External Tools' Identification Capability, via BCSR. Soft / HardB Reset Push - Button ABORT Push - Button SingleC 5V Supply. Reverse / Over Voltage Protection for Power Inputs. 3.3V / 2V MPC Internal Logic OperationD, 3.3V MPC I/O Operation. A. Available only if supported also on the MPC8XX. B. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons. C. Unless a 12V supply is required for a PCMCIA card or for a 12V programmable Flash SIMM. D. Implemented on Daughter Board. MOTOROLA PR t t t t t Power Indications for Each Power Bus. Software Option Switch provides 16 S/W options via BCSR. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Optional Hard-Reset Configuration Burned in FlashA. IM IN 10-Base-T Port On-Board, with Stand-By Mode. AR Y 3 General Information FIGURE 1-1 MPC8XXFADS Motherboard Block Diagram SDRAM 4 MBytes DATA & ADDRESS BUFFERS Reset, Interrupts & Clock FLASH SIMM. 2 - 8MByte Dram Width & Size Logic DAUGHTER BOARD CONN. Control & Status Register AR Y 4 - 32 Mbyte EEST PCMCIA Buffering & Control DRAM SIMM DEBUG PORT CONTROLLER (ADI I/F) IM EL (*) May be on a separate board. 1*7 The MPC8XXFADS is meant to become a general platform for s/w and h/w development around the MPC8XX family. Using its on-board resources and its associated debugger, the developer is able to load his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a system with the MPC. This board could also be used as a demonstration tool, i.e., application s/w may be programmedA into its flash memory and ran in exhibitions etc. A. Either on or off-board. 4 PR ADI PORT (*) MPC8XXFADS Goals MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA PCMCIA PORT ETHERNET PORT RS232 PORTS Debug Port Connector IN Fast IrDA Port Hardware Preparation and Installation 2 - Hardware Preparation and Installation 2*1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MPC8XXFADS. 2*2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier's agent to be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment. 2*3 HARDWARE PREPARATION MOTOROLA PR To select the desired configuration and ensure proper operation of the MPC8XXFADS board, changes of the Dip-Switch settings may be required before installation. The location of the switches, LEDs, Dip-Switches, and connectors is illustrated in FIGURE 2-1. The board has been factory tested and is shipped with Dip-Switch settings as described in the following paragraphs. Parameters can be changed for the following conditions: * ADI port address * MPC Clock Source * Power-On Reset Source. * MPC Keep Alive Power Source * MPC Internal Logic Supply Source * Debug Mode Indication Source MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY; STATIC DISCHARGE CAN DAMAGE CIRCUITS. AR Y 5 Hardware Preparation and Installation FIGURE 2-1 MPC8XXFADS Top Side Part Location diagram 6 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Hardware Preparation and Installation 2*3*1 ADI Port Address Selection The MPC8XXFADS can have eight possible slave addresses set for its ADI port, enabling up to eight MPC8XXFADS boards to be connected to the same ADI board in the host computer. The selection of the slave address is done by setting switches 1, 2 & 3 in the Dip-Switch - DS2. Switch 1 stands for the most-significant bit of the address and switch 3 stands for the least-significant bit. If the switch is in the 'ON' state, it stands for logical '1'. In FIGURE 2-2 DS1 is shown to be configured to address '0'. FIGURE 2-2 Configuration Dip-Switch - DS2 ON ADR2 ADR1 ADR0 3 - 5 MHz Generator via EXTCLK 1 2 3 4 DS2 ADR2 Table 2-1 ADI Address Selection 0 1 2 3 4 5 6 OFF OFF OFF OFF ON ON ON ON IM ADDRESS Switch 1 IN Switch 2 OFF OFF ON ON OFF OFF ON ON Table 2-1 describes the switch settings for each slave address: EL Clock Source Selection Power-On Reset Source Selection PR 7 2*3*2 Switch #4 on DS2 selects the clock source for the MPC. When it is in the 'ON' position while the FADS is powered-up, the on-board 32.768 KHz crystal resonatorA becomes the clock source and the PLL multiplication factor becomes 1:513. When switch #4 is in the 'OFF' position while the FADS is powered-up, the on-board 4BMHz clock generatorA becomes the clock source while the PLL multiplication factor becomes 1:5. 2*3*3 As there are differences between MPC revisions regarding the functionality of the Power-On Reset logic, it is therefore necessary to select different sources for Power-ON reset generation. The above selection is done on the Daughter Board and therefore, documented in the specific A. Located on the Daughter-Board B. A 5MHz clock generator is packed as well. MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y ADR1 ADR0 Switch 3 OFF ON OFF ON OFF ON OFF ON 32.678 KHz Crystal Resonator 7 Hardware Preparation and Installation Daughter Board user's manual. 2*3*4 VDDL Source Selection This selection is done on the Daughter Board and therefore, documented in the specific Daughter Board user's manual. 2*3*5 Keep Alive Power Source Selection This selection is done on the Daughter Board and therefore, documented in the specific Daughter Board user's manual. 2*3*6 Debug Mode Indication Source Selection When a jumper is positioned between pins 1 and 2 of J1 - VFLS(0:1) are selected towards the debugport controller. When a jumper is placed between positions 2 - 3 of J1(2) - FRZ signal is selected. FIGURE 2-3 J1 1 VFLS(0:1) Selected IM 2*4 INSTALLATION INSTRUCTIONS 2*4*1 In this configuration the MPC8XXFADS is controlled by a host computer via the ADI through the debug port. This configuration allows for extensive debugging using on-host debugger. 8 PR When the MPC8XXFADS has been configured as desired by the user, it can be installed according to the required working environment as follows: * Host Controlled Operation * Debug Port Controller for Target System * Stand-Alone Host Controlled Operation MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IN 1 FRZ Selected MOTOROLA AR Y J1 Jumper J1 selects between VFLS(0:1) signals and FRZ signal of the MPC as an indication for debug mode state. Since with the MPC8XXs, each of these signals has alternate function, it may be necessary to switch between the two sources, in favor of alternate function being used. Hardware Preparation and Installation FIGURE 2-4 Host Controlled Operation Scheme ADI 37 Wire Flat Cable P1 P1 Host Computer 5V Power Supply P6 P6 2*4*2 Debug Port Controller For Target System All debugger commands and debugging features are available in this mode, including s/w download, breakpoints, etc`... The target system may be reset or interrupted by the debug port or reset by the FADS's RESET switches. It is the responsibility of the target system designer, to provide Power-OnReset and HARD-Reset configurations, while SOFT-Reset configuration is provided by the debugport controller. See also 4*12*1 "MPC8XXFADS As Debug Port Controller For Target System" on page 58. A. On Daughter Board. MOTOROLA PR With this mode of operation, all on-board modules are disabled and can not be accessed in anyway, except for the debug port controller. Also, all indications except for 5V power, 3.3V-PowerA and RUN are darkened. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL When connecting the FADS to a target system via P5 and a 10 lead flat-cable, the MPC MUST be REMOVED from its SOCKET. Otherwise, PERMANENT DAMAGE might be inflicted to either the Local MPC or to the Target MPC. IM This configuration resembles the previous, but here the local MPC is removed from its socket while the FADS is connected via a 10 lead Flat-Cable between P5 and a matching connector on a target system. WARNNING IN AR Y 9 Hardware Preparation and Installation FIGURE 2-5 Debug Port Controller For Target System Operation Scheme Target System 10 Wire Flat Cable Flat Cable P1 P1 37 Wire ADI Host Computer 5V Power Supply P6 P6 MPC Removed From Socket 2*4*3 Stand Alone Operation 10 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL In this mode, the FADS is not controlled by the host via the ADI/Debug port. It may connect to host via one of its other ports, e.g., RS232 port, I/R port, Ethernet port, etc`. Operating in this mode requires an application program to be programmed into the board`s Flash memory (while with the host controlled operation, no memory is required at all). IM IN MOTOROLA AR Y P5 Hardware Preparation and Installation FIGURE 2-6 Stand Alone Configuration Host Computer RS 23 2 Et he rne P1 t I/R 5V Power Supply P6 P6 The MPC8XXFADS requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power supply to connector P6 as shown below: IM FIGURE 2-7 P6: +5V Power Connector +5V GND GND EL 2*4*5 The MPC8XXFADS requires +12 Vdc @ 1 A max, power supply for the PCMCIA channel Flash programming capability or for 12V programmable Flash SIMM. The MPC8XXFADS can work properly without the +12V power supply, if there is no need to program either a 12V programmable PCMCIA flash card or a 12V programmable Flash SIMM. Connect the +12V power supply to connector P7 as shown below: MOTOROLA PR P6 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two Gnd terminals are supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is connected with a single wire. NOTE Since hardware applications may be connected to the MPC8XXFADS via the Daughter-Boards' expansion connectors PX1, PX2 PX3, PX4 or FADS's P8, the additional power consumption should be taken into consideration when a power supply is connected to the MPC8XXFADS. P7: +12V Power Supply Connection MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 1 2 3 2*4*4 +5V Power Supply Connection AR Y 11 Hardware Preparation and Installation FIGURE 2-8 P7: +12V Power Connector +12V GND 1 2 P7 is a 2 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. 2*4*6 2*4*7 ADI Installation Host computer to MPC8XXFADS Connection The MPC8XXFADS ADI interface connector, P1, is a 37 pin, male, D type connector. The connection between the MPC8XXFADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE 2-9 below shows the pin configuration of the connector. FIGURE 2-9 P1 - ADI Port Connector Gnd Gnd Gnd Gnd Gnd Gnd (+ 12 v) N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ Gnd Gnd Gnd PD0 PD2 PD4 PD6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC8XXFADS. 2*4*8 A serial (RS232) terminal or any other RS232 equipment, may be connected to the RS-232 connectors PA2 and PB2. The RS-232 connectors is a 9 pin, female, Stacked D-type connector as shown in FIGURE 2-10. The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an IBMATA or compatibles, i.e. via a flat cable. A. IBM-AT is a trademark of International Business Machines Inc. 12 PR N.C D_C~ HST_ACK ADS_SRESET ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK N.C. N.C. N.C. N.C. PD1 PD3 PD5 PD7 Terminal to MPC8XXFADS RS-232 Connection MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y For ADI installation on various host computers, refer to APPENDIX C - "ADI Installation" on page 155. MOTOROLA Hardware Preparation and Installation FIGURE 2-10 PA2, PB2 - RS-232 Serial Port Connectors CD TX RX DTR GND 1 2 3 4 5 6 7 8 9 DSR RTS CTS N.C. NOTE: The RTS line (pin 7) is not connected on the MPC8XXFADS. The MPC8XXFADS is supplied with two types of memory SIMM: CAUTION EL (1) FIGURE 2-11 Memory SIMM Installation PR MOTOROLA Memory SIMM IM (2) The memory SIMMs have alignment nibble near their # 1 pin. It is important to align the memory correctly before it is twisted, otherwise damage might be inflicted to both the memory SIMM and its socket. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN * Dynamic Memory SIMM * Flash Memory SIMM. To avoid shipment damage, these memories are packed aside rather than being installed in their sockets. Therefore, they should be installed on site. To install a memory SIMM, it should be taken out of its package, put diagonally in its socket (no error can be made here, since the Flash socket has 80 contacts, while the DRAM socket has 72) and then twisted to a vertical position until the metal lock clips are locked. See FIGURE 2-11 "Memory SIMM Installation" below. AR Y Metal Lock Clip SIMM Socket 2*4*9 Memory Installation 13 OPERATING INSTRUCTIONS 3 - OPERATING INSTRUCTIONS 3*1 INTRODUCTION This chapter provides necessary information to use the MPC8XXFADS in host-controlled and standalone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 3*2 3*2*1 CONTROLS AND INDICATORS The MPC8XXFADS has the following switches and indicators. The ABORT switch is normally used to abort program execution, this by issuing a level 0 interrupt to the MPC. If the FADS is in stand alone mode, it is the responsibility of the user to provide means of handling the interrupt, since there is no resident debugger with the MPC8XXFADS. The ABORT switch signal is debounced, and can not be disabled by software. 3*2*3 HARD RESET - Switches SW1 & SW2 3*2*4 DS1 - Software Options Switch DS1 is a 4-switches Dip-Switch. This switch is connected over EXTOLI(0:3) lines which are available at BCSR, S/W options may be manually selected, according to DS1 state. PR 3*2*5 14 EL 1 2 3 4 When BOTH switches - SW1 and SW2 are depressed simultaneously, HARD reset is generated to the MPC. When the MPC is HARD reset, all its configuration is lost, including data stored in the DRAM or SDRAM and the MPC has to be re-initialized. At the end of the Hard Reset sequence, the Hard Reset Configuration stored in BCSR0 becomes valid. FIGURE 3-1 DS1 - Description IM DS1 The SOFT RESET switch SW2 performs Soft reset to the MPC internal modules, maintaining MPC's configuration (clocks & chip-selects) Dram and SDram contents. The switch signal is debounced, and it is not possible to disable it by software. At the end of the Soft Reset Sequence, the Soft Reset Configuration is sampled and becomes valid. EXTOLI0 Pulled to '1' EXTOLI1 Pulled to '1' EXTOLI2 Pulled to '1' EXTOLI3 Pulled to '1' GND Bridges There are 3 GND bridges on the MPC8XXFADS. They are meant to assist general measurements MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN ON 3*2*2 SOFT RESET Switch SW2 AR Y EXTOLI0 Driven to '0' EXTOLI1 Driven to '0' EXTOLI2 Driven to '0' EXTOLI3 Driven to '0' ABORT Switch SW1 MOTOROLA OPERATING INSTRUCTIONS and logic-analyzer connection. Warning When connecting to a GND bridge, use only INSULATED GND clips. Failure in doing so, might result in permanent damage to the MPC8XXFADS. 3*2*6 ETH ON - LD1 When the yellow ETH ON led is lit, it indicates that the ethernet port transceiver - the MC68160 EEST, is active. When it is dark, it indicates that the EEST is in power down mode, enabling the use of its associated SCC pins off-board via the expansion connectors. When the yellow IRD ON led is lit, it indicates that the Infra-Red transceiver - the TFDS6000, is active and enables communication via that medium. When it is dark, the I/R transceiver is in shutdown mode, enabling the use of its associated SCC pins off-board via the expansion connectors. 3*2*8 RS232 Port 1 ON - LD3 3*2*9 RS232 Port 2 ON - LD4 The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the Ethernet port. 3*2*11 Ethernet TX Indicator - LD6 3*2*12 The red Ethernet TP Jabber LED indicator - JABB, lights whenever a jabber condition is detected on the TP ethernet port. 3*2*13 The red Ethernet Collision LED indicator CLSN, blinks whenever a collision condition is detected on the ethernet port, i.e., simultaneous receive and transmit. 3*2*14 The red Ethernet TP Polarity LED indicator - PLR, lights whenever the wires connected to the receiver input of the ethernet port are reversed. The LED is lit by the EEST, and remains on while the EEST has automatically corrected for the reversed wires. 3*2*15 The yellow Ethernet Twisted Pair Link Integrity LED indicator - LIL, lights to indicate good link integrity on the TP port. The LED is off when the link integrity fails. MOTOROLA PR The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet port. Ethernet JABB Indicator - LD7 Ethernet CLSN Indicator LD8 Ethernet PLR Indicator - LD9 Ethernet LIL Indicator - LD10 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL 3*2*10 Ethernet RX Indicator - LD5 IM When the yellow RS232 Port 2 ON led is lit, it designates that the RS232 transceiver connected to PB2, is active and communication via that medium is allowed. When darkened, it designates, that the transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. IN When the yellow RS232 Port 1 ON led is lit, it designates, that the RS232 transceiver connected to PA2, is active and communication via that medium is allowed. When darkened, it designates that the transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. AR Y 3*2*7 IRD ON - LD2 15 OPERATING INSTRUCTIONS 3*2*16 3*2*17 5V Indicator - LD11 RUN Indicator - LD12 The yellow 5V led, indicates the presence of the +5V supply at P6. When the green RUN led - LD12 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 & VFLS1 == 0 (or FRZ == 0, which ever selected by J1). 3*2*18 AUXILARY Indicator LD13 This indication has no dedicated function over the FADS. It is meant to provide some visibility for program behavior. It is controlled by the Signal Lamp bit in BCSR4. 3*2*19 FLASH ON - LD14 When the yellow FLASH ON led is lit, it indicates that the FLASH SIMM is enabled in the BCSR1 register. I.e., any access done to the CS0~ address space will hit the flash memory. When it is dark, the flash is disabled and CS0~ may be used off-board via the expansion connectors. 3*2*20 DRAM ON - LD15 3*2*21 SDRAM ON - LD16 3*2*22 1) 2) 3) PCMCIA ON - LD17 When the yellow PCMCIA ON led is lit, it indicates the following: Data buffers are driven to / from the PCMCIA card whenever CE1A~A or CE2A~B signals are asserted. Card status lines are driven towards the MPC from the PCMCIA card. 3*3 All accesses to MPC8XXFADS's memories are controlled by the MPC's memory controller. Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is performed by the debug station, the debugger checks to see the size, delay and type of the DRAM and FLASH SIMMs mounted on board and initializes the chip-selects accordingly. The DRAM, A. Connected to CE1B~ for MPC823FADSDB. B. Connected to CE2B~ for MPC823FADSDB. C. Or B for MPC823FADSDB. 16 PR When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with PCMCIA channel AC, may be used off-board via the expansion connectors. MEMORY MAP MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Address & strobe buffers are driven towards the PCMCIA card IM When the yellow SDRAM ON led is lit, it indicates the SDRAM is enabled in BCSR1. Therefore, any access made to CS4~ (will hit on the SDRAM. When it is dark, it indicates that either the SDRAM is disabled in BCSR1, enabling the use of CS4~ off-board via the expansion connectors. IN When the yellow DRAM ON led is lit, it indicates the DRAM SIMM is enabled in BCSR1. Therefore, any access made to CS2~ (or CS3~) will hit on the DRAM. When it is dark, it indicates that either the DRAM is disabled in BCSR1, enabling the use of CS2~ and CS3~ off-board via the expansion connectors. AR Y MOTOROLA OPERATING INSTRUCTIONS SDRAM and the FLASH memory respond to all types of memory access i.e., user / supervisory, program / data and DMA. TABLE 3-1. MPC8XXADS Main Memory Map ADDESS RANGE 00000000 - 003FFFFF 00400000 - 007FFFFF 00800000 - 00FFFFFF 01000000 - 01FFFFFF 02000000 - 020FFFFF 02100000 - 02103FFF 02100000 - 02103FE3 2100004 - 02103FE7 2100008 - 02103FEB 210000C - 02103FEF 2100010 - 02103FF3 02104000 - 021FFFFF 02200000 - 02207FFF 02208000 - 027FFFFF 02800000 - 029FFFFF 02A00000 - 02BFFFFF 02C00000 - 02FFFFFF 03000000 - 033FFFFF Empty Space BCSR(0:4)b BCSR0 BCSR1 BCSR2 BCSR3 BCSR4 Empty Space MPC Internal MAPd Empty Space Flash SIMM Memory Type DRAM SIMM MB321Bxa08 Device Type MB322Bxa08 MC324Cxa00 MB328Cxa00 Port Size 32 32 32 AR Y IM IN MCM29F020 MCM29F040 SM732A1000A MCM29F080 SM732A2000 32 32c 32 EL 32 32 32 32 03400000 - FFFFFFFF a. x [B,T] b. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations 2100000, 2100020, 2100040..., while BCSR1 appears at 2100004, 2100024, 2100044... and so on. c. Only upper 16 bit (D0-D15) are in fact used. d. Refer to the relevant MPC User's Manual for complete description of the MPC internal memory map. 3*4 1) 2) 3) 4) The MPC provides the following functions on the MPC8XXFADS: DRAM Controller SDRAM Controller Chip Select generator. UART for terminal or host computer connection. MOTOROLA PR SDRAM Empty Space Programming The MPC Registers MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 17 OPERATING INSTRUCTIONS 5) 6) 7) Ethernet controller. Infra-Red Port Controller General Purpose I/O signals. The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs. The addresses and programming values are in hexadecimal base. For better understanding the of the following initializations refer to the MPC821 or to the MPC860 User's Manual for more information. TABLE 3-2. SIU REGISTERS' PROGRAMMING Register SIUMCR Init Value[hex] 01032440 Description Internal arbitration, External master arbitration priority - 0, External arbitration priority - 0, PCMCIA channel II pins - PCMCIA, Debug Port on JTAG port pins, FRZ/IRQ6~ - FRZ, debug register - locked, No parity for non-CS regions, DP(0:3)/ IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~ and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/ B(2:3)~ function as GPLs. TBSCR RTCSC PISCR 00C2 00C2 0082 Interrupt request level - 0, 32768 Hz source, second interrupt disabled, Alarm interrupt disabled, Real-time clock - FREEZE, Real-time clock enabled. No level for interrupt request, Periodic interrupt disabled, clear status, interrupt disabled, FREEZE, periodic timer disabled. 3*4*1 Memory Controller Registers Programming The reason for initializing the FADS for 50Mhz is to allow proper (although not efficient) FADS operation through all available FADS clock frequencies. A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been inadequate if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus bandwidth availability, refresh rate should be adapted to the current system clock frequency. 18 PR The memory controller on the MPC8XXFADS is initialized to 50 MHz operation. I.e., registers' programming is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16.67Mhz, the lowest frequency at which the FADS may wake up. Since the FADS may be made to wake-up at 25MHzA as well, the initializations are not efficient, since there are too many wait-states inserted. Therefore, additional set of initialization is provided to support efficient 25MHz operation. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM No interrupt level, reference match indications cleared, interrupts disabled, no freeze, time-base disabled. IN SYPCR FFFFFF88 Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if enabled) causes NMI, S/W (if enabled) not prescaled. AR Y MOTOROLA OPERATING INSTRUCTIONS Warning Due to availability problems with few of the supported memory components, the below initializations were not tested with all parts. Therefore, the below initializations are liable to CHANGE, throughout the testing period. TABLE 3-3. Memory Controller Initializations For 50Mhz Register BR0 OR0 Device Type All Flash supported. MCM29F020-90 MCM29F040-90 SM732A1000A-9 MCM29F080-90 SM732A2000-9 MCM29F020-12 MCM29F040-12 SM732A1000A-12 MCM29F080-12 SM732A2000-12 SIMMs Init Value [hex] 02200001 FFE00D34 FFC00D34 FF800D34 FFE00D44 FFC00D44 FF800D44 02100001 Description Base at 2200000, 32 bit port size, no parity, GPCM 2MByte block size, all types access, CS early negate, 6 w.s., Timing relax 4MByte block size, all types access, CS early negate, 6 w.s., Timing relax IM FFFF8110 00000081 FFC00800 FF000800 00400081 01000081 FFC00800 FF000800 030000C1 FFC00A00 OR1 BR2 OR2 EL SIMMs BR1 BCSR PR MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7 MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7 All Dram Supported MCM36100/200-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7 BR3 OR3 BR4 OR4 MB811171622A-100 MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 8MByte block size, all types access, CS early negate, 6 w.s., Timing relax 2MByte block size, all types access, CS early negate, 8 w.s., Timing relax 4MByte block size, all types access, CS early negate, 8 w.s., Timing relax 8MByte block size, all types access, CS early negate, 8 w.s., Timing relax Base at 2100000, 32 bit port size, no parity, GPCM 32 KByte block size, all types access, CS early negate, 1 w.s. Base at 0, 32 bit port size, no parity, UPMA 4MByte block size, all types access, initial address multiplexing according to AMA. 16MByte block size, all types access, initial address multiplexing according to AMA. Base at 400000, 32 bit port size, no parity, UPMA Base at 1000000, 32 bit port size, no parity, UPMA 4MByte block size, all types access, initial address multiplexing according to AMA 16MByte block size, all types access, initial address multiplexing according to AMA. Base at 3000000, on UPM B 4 MByte block size, all types access, initial address multiplexing according to AMB. AR Y 19 OPERATING INSTRUCTIONS TABLE 3-3. Memory Controller Initializations For 50Mhz Register MPTPR MAMR Device Type All Dram Supported SIMMs Init Value [hex] 0400 40A21114a 60A21114b C0A21114c Description Divide by 16 (decimal) refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB321BT08TASN60 MB324CT00TBSN60 40B21114a 60B21114b C0B21114c MB328CT00TBSN60 20 PR a. Assuming 16.67 MHz BRGCLK. b. Assuming 25MHz BRGCLK c. For 50MHz BRGCLK d. Assuming 32MHz BRGCLK. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL MBMR MB811171622A-100 IM D0802114c 80802114d 20B21114a 30B21114b 60B21114c IN refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by D0 or 80, periodic timer enabled, type 0 address multiplexing scheme, 1 cycle disable timer, GPL4enabled, 1 loop read, 1 loop write, 4 beats refresh burst. AR Y MB322BT08TASN60 20A21114a 30A21114b 60A21114c refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MOTOROLA OPERATING INSTRUCTIONS TABLE 3-4. UPMA Initializations for 60nsec DRAMs @ 50MHz Cycle Type Offset in UPM Contents @ Offset + 0 1 2 3 4 5 6 7 8 9 A B C D E F Single Read 0 8FFFEC24 0FFFEC04 0CFFEC04 00FFEC04 00FFEC00 37FFEC47 X X Burst Read 8 8FFFEC24 0FFFEC04 08FFEC04 00FFEC0C 03FFEC00 00FFEC44 00FFCC08 0CFFCC44 00FFEC0C 03FFEC00 00FFEC44 00FFCC00 3FFFC847 X X X Single Write 18 8FAFCC24 0FAFCC04 0CAFCC00 11BFCC47 X X X X Burst Write 20 8FAFCC24 0FAFCC04 0CAFCC00 Refresh 30 C0FFCC84 00FFCC04 07FFCC04 Exception 3C 33FFCC07 X X 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 03AFCC4C IN X X X X X X 0CAFCC00 33BFCC4F IM MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y 3FFFCC06 X FFFFCC85 FFFFCC05 X X X X X X 21 OPERATING INSTRUCTIONS TABLE 3-5. UPMA Initializations for 60nsec EDO DRAMs @ 50MHz Cycle Type Offset in UPM Contents @ Offset + 0 1 2 3 4 5 6 7 8 9 A B C D E F Single Read 0 8FFBEC24 0FF3EC04 0CF3EC04 00F3EC04 00F3EC00 37F7EC47 X X Burst Read 8 8FFFEC24 0FFBEC04 0CF3EC04 00F3EC0C 0CF3EC00 00F3EC4C 0CF3EC00 00F3EC4C 0CF3EC00 00F3EC44 03F3EC00 3FF7EC47 X X X X Single Write 18 8FFFCC24 0FEFCC04 0CAFCC00 11BFCC47 X X X X Burst Write 20 8FFFCC24 0FEFCC04 0CAFCC00 03AFCC4C 0CAFCC00 Refresh 30 C0FFCC84 00FFCC04 07FFCC04 3FFFCC06 Exception 3C 33FFCC07 X X X 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 IN X X X X X X 33BFCC4F Register BR0 PR TABLE 3-6. Memory Controller Initializations For 20Mhz Device Type Init Value [hex] 02200001 EL SIMMs IM All Flash supported. Base at 2200000, 32 bit port size, no parity, GPCM 22 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y FFFFCC85 FFFFCC05 X X X X X X Description MOTOROLA OPERATING INSTRUCTIONS TABLE 3-6. Memory Controller Initializations For 20Mhz Register OR0 Device Type MCM29F020-90 MCM29F040-90 SM732A1000A-9 MCM29F080-90 SM732A2000-9 MCM29F020-12 MCM29F040-12 SM732A1000A-12 MCM29F080-12 SM732A2000-12 Init Value [hex] FFE00D20 FFC00D20 FF800920 FFE00D30 FFC00D30 FF800930 02100001 FFFF8110 Description 2MByte block size, all types access, CS early negate, 2 w.s. 4MByte block size, all types access, CS early negate, 2 w.s. 8MByte block size, all types access, CS early negate, 2 w.s., Timing relax 4MByte block size, all types access, CS early negate, 3 w.s. 8MByte block size, all types access, CS early negate, 3 w.s. Base at 2100000, 32 bit port size, no parity, GPCM BR1 OR1 BR2 OR2 BCSR All Dram Supported SIMMs 00000081 FFC00800 MB321/2BT08TASN60 MB324/8CT00TBSN60 IM FF000800 00400081 01000081 FFC00800 FF000800 030000C1 FFC00A00 0400 MB322BT08TASN60 EL SIMMs BR3a MB328CT00TBSN60 OR3 MB322BT08TASN60 PR All Dram Supported MB328CT00TBSN60 MB811171622A-100 BR4 OR4 MPTPR MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 32 KByte block size, all types access, CS early negate, 1 w.s. Base at 0, 32 bit port size, no parity, UPMA 4MByte block size, all types access, initial address multiplexing according to AMA. 16MByte block size, all types access, initial address multiplexing according to AMA. Base at 400000, 32 bit port size, no parity, UPMA Base at 1000000, 32 bit port size, no parity, UPMA 4MByte block size, all types access, initial address multiplexing according to AMA 16MByte block size, all types access, initial address multiplexing according to AMA. Base at 3000000, on UPM B. 4MByte block size, all types access, initial address multiplexing according to AMB Divide by 16 (decimal) AR Y 2MByte block size, all types access, CS early negate, 3 w.s. 23 OPERATING INSTRUCTIONS TABLE 3-6. Memory Controller Initializations For 20Mhz Register MAMR Device Type MB321BT08TASN60 Init Value [hex] 60A21114 Description refresh clock divided by 60, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by 30, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by 60, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by 30, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. refresh clock divided by 42, periodic timer enabled, type 0 address multiplexing scheme, 1 cycle disable timer, GPL4 enabled, 1 loop read, 1 loop write, 4 beats refresh burst. MB322BT08TASN60 30A21114 MB324CT00TBSN60 60B21114 MB328CT00TBSN60 30B21114 MBMR MB811171622A-100 42802114b a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs. b. Assuming 16.67MHz BRGCLK 24 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y MOTOROLA OPERATING INSTRUCTIONS TABLE 3-7. UPMA Initializations for 60nsec EDO DRAMs @ 20MHz Cycle Type Offset in UPM Contents @ Offset + 0 1 2 3 4 5 6 7 8 9 A B C D E F Single Read 0 8FFFCC04 08FFCC00 33FFCC47 X X X X X Burst Read 8 8FFFCC04 08FFCC08 08FFCC08 08FFCC08 08FFCC00 3FFFCC47 X X X X X X X X X X Single Write 18 8FEFCC00 39BFCC47 X X X X X X Burst Write 20 8FEFCC00 09AFCC48 09AFCC48 09AFCC48 39BFCC47 X X X X X X X X X X X Refresh 30 80FFCC84 17FFCC04 FFFFCC86 FFFFCC05 X Exception 3C 33FFCC07 X X X IN IM MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y X X X X X X X 25 OPERATING INSTRUCTIONS TABLE 3-8. UPMB Initializations for MB811171622A-100 upto 32MHz Cycle Type Offset In UPM Contents @ Offset + 0 1 2 3 4 5 6 7 8 9 A B C D E F Single Read 0 0126CC04 0FB98C00 1FF74C47 X X 1FE77C34a EFAABC34 1FA57C35 Burst Read 8 0026FC04 10ADFC00 F0AFFC00 F1AFFC00 EFBBBC00 1FF77C47 X X X X X X X X X X Single Write 18 0E26BC04 01B93C00 1FF77C47 X X X X X Burst Write 20 0E26BC00 10AD7C00 F0AFFC00 F0AFFC00 Refresh 30 1FF5FC84 FFFFFC04 FFFFFC84 FFFFFC07 Exception 3C 7FFFFC07 X X X E1BBBC04 1FF77C47 X X X X X X X X X X IN IM a. MRS initialization. Uses Free space. 26 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y X X X X X X X X MOTOROLA OPERATING INSTRUCTIONS TABLE 3-9. UPMB Initializations for MB811171622A-100, 32+MHz - 50MHz Cycle Type Offset In UPM Contents @ Offset + 0 1 2 3 4 5 6 7 8 9 A B C D E F Single Read 0 1F07FC04 EEAEFC04 11ADFC04 EFBBBC00 1FF77C47 1FF77C34a EFEABC34 1FB57C35 Burst Read 8 1F07FC04 EEAEFC04 10ADFC04 F0AFFC00 F0AFFC00 F1AFFC00 EFBBBC00 1FF77C47 X X X X X X X X Single Write 18 1F27FC04 EEAEBC00 01B93C04 1FF77C47 X X X X Burst Write 20 1F07FC04 EEAEBC00 10AD7C00 F0AFFC00 F0AFFC00 Refresh 30 1FF5FC84 FFFFFC04 FFFFFC04 FFFFFC04 Exception 3C 7FFFFC07 X X X E1BBBC04 1FF77C47 X X X X X X X X X IN IM a. MRS initialization, Uses free space. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y FFFFFC84 FFFFFC07 X X X X X X 27 Functional Description 4 - Functional Description In this chapter the various modules combining the MPC8XXFADS are described to their design details. 4*1 Reset & Reset - Configuration 1) Keep Alive Power-On ResetA 2) Regular Power On Reset 4) Manual Hard-Reset 3) Manual Soft-Reset There are several reset sources on the FADS: 5) MPC Internal Sources. (See the appropriate Spec or U/M) 4*1*1 Keep Alive Power-On Reset The Keep Alive Power - On Reset logic resides on the daughter board this since the Keep Alive power bus is on that board and it also allows the use of the daughter board connected directly to a user's application. 4*1*2 Regular Power - On Reset When HRESET~ is asserted to the MPC, Hard-Reset configuration is made available to the MPC, via BCSR0. See 4*1*6*2 "Hard Reset Configuration" on page 29 and TABLE 4-9. "BCSR0 Description" on page 46. 4*1*3 Manual Soft Reset To support application development not around the debug port and resident debuggers, a soft reset push-button is provided. (SW2) Depressing that button, asserts the SRESET* pin of the MPC, generating a SOFT RESET sequence. 4*1*4 To support application development not around the debug port, a Hard-Reset push-button is providedC. When the Soft Reset push-button (SW2) is depressed in conjunction with the ABORT pushbutton (SW1), the HRESET* line is asserted, generating a HARD RESET sequence. The button sharing is for economy and board space saving and does not effect in any way, functionality. 4*1*5 Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic drives these lines with open-drain gates, the correct operation of the internal reset sources of the MPC is facilitated. As a rule, an internal reset source asserts HRESET* and / or SRESET* for a minimum time of 512 system clocks. It is beyond the scope of this document to describe these sources, however Debug-Port Soft / Hard Resets which are part of the development systemD, are A. In fact generated on the daughter board. B. Again not directly. C. It is not a dedicated button. 28 PR When the SRESET~ line is asserted to the MPC, the Soft-Reset configuration is made available to the MPC, by the debug-port controller. See 4*1*6*3 "Soft Reset Configuration" on page 29. Manual Hard Reset MPC Internal Sources MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM The regular power on reset operates in the same manner as the keep alive power-on reset, using a similar device - the Seiko - S-8052ANY-NH-X with detection voltage of 2.595V to 2.805V. The reference voltage of this device is the MAIN VDDH bus of the MPC while the reset line assertedB, is the HRESET* line. IN AR Y MOTOROLA Functional Description regarded as such. 4*1*6 Reset Configuration During reset the MPC device samples the state of some external pins to determine its operation modes and pin configuration. There are 3 kinds of reset levels to the MPC each level having its own configuration sampled: 1) Power - On Reset configuration 2) Hard Reset configuration 3) Soft Reset Configuration. 4*1*6*1 Power - On Reset Configuration Just before PORESET* is negated by the external logic, the power-on reset configuration which include the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the MPC. Two clock modes are supported on the MPC8XXFADS: 1) 1:5 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '11' duringA power on reset. 2) 1:513 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '00'. during power-on reset. 4*1*6*2 Hard Reset Configuration The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset, are listed below: 1) 2) Arbitration: internal arbitration is selected. Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to provide interrupt prefix at address 0, which is located within the DRAM. Boot Disable: Boot is enabled. Boot Port Size: 32 bit boot port size is selected. 4*1*6*3 The rising edge of SRESET* is used to configure the development port. Before the negation of SRESET*, DSCKD is sampled to determine for debug-mode enable / disable. After SRESET* is D. And therefore mentioned. A. The MODCK lines are in fact driven longer - by HRESET~ line. B. With respect the FADS's power-on defaults. C. Where they exist. MOTOROLA PR 3) 4) 5) 6) 7) 8) Initial Internal Space Base: Immediately after HARD reset, the internal space is located at $FF000000. Debug pins configuration: PCMCIA port BC pins become PCMCIA port B pins. Debug port pins configuration. Debug port pins are on the JTAG port. External Bus Division Factor: 1:1 internal to external clocks' frequencies ratio is selected. Soft Reset Configuration MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL On the FADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with the MPC's internal HARD reset configuration defaults. IM During HARD reset sequence, when RSTCONF* pin is asserted, the MPC data bus state is sampled to acquire the MPC's hard reset configuration. The reset configuration word is driven by BCSR0 register, defaults of which are set during power-on reset. The BCSR0 drives half of the configuration word, i.e., data bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset configuration is to be changedB, BCSR0 may be written with new values, which become valid after HARD reset is applied to the MPC. IN AR Y 29 Functional Description negated, if debug mode was enabled, DSCK is sampled again for debug-mode entry / non-entry. DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*. The Soft Reset configuration is provided by the debug-port controller via the ADI I/F. Option is given to enter debug mode directly or only after exception. 4*2 Local Interrupter To support external (off-board) generation of an NMI, the IRQ0* line which is routed as an NMI input, is driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w indeed does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate. 4*3 1) 2) Clock GeneratorA There are 2 ways to clock the MPC on the MPC8XXFADS: 32.768 KHz crystal resonatorB via EXTAL-XTAL pair of the MPC, 1:513 initial PLL multiplication factor. When mode (2) above is selected, the output of the clock generator is gated from EXTCLK input and driven to '0' constantly so that a jitter-free system clock is generated. On-board logic is clocked by the MPC's CLKOUT coming from the Daughter board. This clock is multiplexed with the debug port's clock generator, so that on-board logic is always clocked, even when the MPC is removed from its socketC. 4*4 As the FADS meant to serve also as a hardware development platform, it is necessary to buffer the MPC from the local bus, so the MPC's capacitive drive capability is not wasted internally and remains available for user's off-board applications via the expansion connectors. Buffers are provided for address and strobeD lines while transceivers are provided for data. Since the capacitive load over dram's address lines mightE exceed 200 pF, the dram address lines are separately buffered. Use is done with 74LCX buffers which are 3.3V operated and are 5V tolerant. This D. DSCK is configured at hard-reset to reside on the JTAG port. A. Although this module resides on the DAUGHTER boards, it is described here, as it is common to all MPC8XX supported. B. Located On the Daughter Board. C. When the FADS serves a debug station for target system. D. If necessary. E. Depended on dram SIMM's internal structure. 30 PR Buffering MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM The selection between the above modes is done using Dip-switch (DS2 / 4) with dual functionality: it is responsible to the combination driven to the MODCK lines during power-on reset and to the connection of the appropriate capacitor between MPC's XFC and VDDSYN lines to match the PLL's multiplication factor. When 1:5 mode is selected, a capacitor of 5nF is connected, while when 1:513 mode is selected a 0.68F capacitor is connected parallel to it via a TMOS gate. The capacitors' values are calculated to support a wider range of multiplication factors as possible. IN 3 - 5MHz Clock generatorB connected to CLK4IN input. 1:5 PLL mode. AR Y The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT (NMI), which is generated by a push-button. When this button is depressed, the NMI input to the MPC is asserted. The purpose of this type of interrupt, is to support the use of resident debuggers if any is made available to the FADS. All other interrupts to the MPC, are generated internally by the MPC's peripherals and by the debug port. MOTOROLA Functional Description type of buffers reduces noise on board due to reduced transitions' amplitude. To further reduce noise and reflections, series resistors are placed over dram's address and strobe lines. The data transceivers open only if there is an access to a validA B board address or during Hard Reset configurationC. That way data conflicts are avoided in case an off-board memory is read, provided that it is not mapped to an address valid on board. It is the users' responsibility to avoid such errors. 4*5 Chip - Select Generator When a CS region is disabled via BCSR1, the local data transceivers do not open during access to that region, avoiding possibleF contention over data lines. TABLE 4-1. MPC8XXFADS Chip Selects' Assignment Chip Select: CS0* CS1* CS2* CS3* CS4* EL PR DRAM CS(5-7)* a. If exists. 4*6 The MPC8XXFADS is provided with 4 MBytes of 60nsec delay EDO Dram SIMM. Support is given to any 5V powered FPM / EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32, with 60 nsec or 70nsec delay. All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM size (4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (includA. An address which covered in a Chip-Select region. B. Except for SDRAM, which is Unbuffered. C. To allow a configuration word stored in Flash memory become active. D. And off-board. See further. E. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to the FADS. F. During read cycles. MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM BCSR SDRAM Flash Memory DRAM Bank 1 DRAM Bank 2a Unused, user available IN Assignment The MPC's chip-selects assignment to the various memories / registers on the FADS are as shown in TABLE 4-1. "MPC8XXFADS Chip Selects' Assignment" below: AR Y The memory controller of the MPC is used as a chip-select generator to access on-boardD memories, saving board's area reducing cost, power consumption and increasing flexibility. To enhance offboard application development, memory modules (including the BCSRx) may be disabled via BCSR1E in favor of an external memory connected via the expansion connectors. That way, a CS line may be used off-board via the expansion connectors, while its associated local memory is disabled. 31 Functional Description ing the UPM) are programmed accordingly. Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for a dual-bank SIMM) region(s), i.e., RAS and CAS signals' generation, during normalA access as well as during refresh cycles and the necessary address multiplexingB are performed using UPMA. CS2* and CS3* signals are buffered from the DRAM and each is split to 2 to overcome the capacitive load over the Dram SIMM RAS lines. The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See TABLE 4-10. "BCSR1 Description" on page 48. 4*6*1 DRAM 16 Bit Operation To configure the DRAM for 16 bit data bus width operation, the following steps should be taken: 1) 2) 3) Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-10. "BCSR1 Description" on page 48 The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits. The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm volume or to 1/4 of the nominal dual-bank DRAM simm volume. If a Dual-Bank DRAM simm is being used: 4) 5) The AM bits of OR3 register, should be set to 1/4 Nominal_Volume. 4*6*2 DRAM Performance Figures The projected performance figures for the dram are shown in TABLE 4-2. "Regular DRAM Perfor- A. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write. B. Taking into account support for narrower bus widths. 32 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL If the above is executed out of running code, than this code should not reside on the DRAM while executing, otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash. IM The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4 Nominal_Volume, that is, if a contiguous block of DRAM is desired. IN AR Y To enhance evaluation capabilities, support is given to Dram with 16-bit and 32-bit data bus width. That way users can tailor dram configuration, to get best fit to their application requirements. When the DRAM is in 16 bit mode, half of it can not be used, i.e., the memory portion that is connected to data lines D(16:31). MOTOROLA Functional Description mance Figures" on page 33 and in TABLE 4-3. "EDO DRAM Performance Figures" on page 33. TABLE 4-2. Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] DRAM Delay [nsec] Single Read Single Write Burst Read Burst Write Refresh 6 4 6,2,3,2 4,2,2,2 21a b 50 60 6 4 6,3,2,3 4,2,2,2 25a b 25 70 3 3 60 4 3 70 a. Four-beat refresh burst. b. Not including arbitration overhead. TABLE 4-3. EDO DRAM Performance Figures System Clock Frequency [MHz] DRAM Delay [nsec] Single Read Single Write Burst Read Burst Write Refresh IM 50 60 6 4 6 4 6,2,2,2 4,2,2,2 21a b IN 70 6,3,2,2 4,2,2,2 25a b Number of System Clock Cycles 25 60 3 2 3,1,1,1 2,1,1,1 13a b 4 3 4,1,2,2 3,2,2,2 13a b 4*6*3 The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The refresh logic is clocked by the MPC's BRG clock which is not influenced by the MPC's low-power divider. MOTOROLA PR a. Four-beat refresh burst. b. Not including arbitration overhead. Refresh Control MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y 3,2,2,2 4,2,2,2 3,1,2,2 3,2,2,2 13a b 13a b 70 33 Functional Description FIGURE 4-1 Refresh Scheme BRG Clock PTP PTB UPMB DRAM BANKS As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP (Periodic Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If there are more than one dram banks, than refresh cycles are performed for consecutive banks, therefore, refresh should be made faster. The formula for calculation of the PTA is given below: Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle PTA = Number_Of_Rows_To_Refresh X T_BRG X MPTPR X Number_Of_Banks Where: * * * * Refresh_Period == 16 msec * Number_Of_Beats_Per_Refresh_Cycle: on the FADS it is 4. * Number_Of_Rows_To_Refresh == 1024 * T_BRG == 20 nsec (system clock @ 50 Mhz) * MPTPR arbitrarily chosen to be 16 * Number_Of_Banks == 2 for that SIMM If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex. 4*6*4 Since a port's width determines its address lines' connection scheme, i.e., the number of address lines required for byte-selection varies (1 for 16-bit port and 2 for 32-bit port) according to the port's width, it is necessary to change address connections to a memory port if its width is to be changed. E.g.: if a certain memory is initially configured as a 32-bit port, the list significant address line which is connected to that memory's A0 line should be the MPC's A29. Now, if that port is to be reconfigured as a 16-bit port, the LS address line becomes A30. If a linearA address scheme is to be maintained, all address lines connected to that memory are to A. Consequent addresses lead to adjacent memory cells 34 PR Variable Bus-Width Control MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL PTA - Periodic Timer A filed in MAMR. The value of the 2'nd divider. Refresh_Period is the time (usually in msec) required to refresh a dram bank Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to perform more than one refresh cycle per refresh burst (in fact upto 16). * Number_Of_Rows_To_Refresh: the number of rows in a dram bank * T_BRG: the cycle time of the BRG clock * MPTPR: the value of the periodic timer prescaler (2 to 64) * Number_Of_Banks: number of dram banks to refresh. If we take for example a MCM36200 SIMM which has the following data: IM IN AR Y MOTOROLA Functional Description be shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear addressing scheme is not a must, than only minimal multiplexing is required to support variable port width. In TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, the FADS's dram address connection scheme is presented: TABLE 4-4. DRAM ADDRESS CONNECTIONS Width 32 - Bit Depth Dram ADD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 16 - Bit Depth BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 IN BA21 BA20 BA30 DRAM A(0:8) A9 A10 IM BA20 BA19 BA(21:29) BA20 BA30 BA19 BA30 As can seen from the table above, most of the address lines remain fixed while only 2 lines (the shaded cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines' Switching Scheme" on page 35. The switches on that figure are implemented by active multiplexers controlled by the BCSR1/Dram_Half_Word* bit. MOTOROLA PR FIGURE 4-2 DRAM Address Lines' Switching Scheme MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA30 4M 1M 4M 1M 35 Functional Description 4*7 Flash Memory SIMM The MPC8XXFADS is provided with 2Mbyte of 90 nsec flash memory SIMM - the MCM29020 by Motorola. Support is given also to 4MBytes MCM29F040, 8 MBytes MCM29F080, 4 MBytes SM73218 and to 8 MBytes SM73228 by Smart Technology. The Motorola SIMMs are internally composed of 1, 2 or 4 banks of 4 Am29F040 compatible devices, while the Smart SIMMs are arranged as 1 or 2 banks of four 28F008 devices by Intel. The flash SIMM resides on an 80 pin SIMM socket. To minimize use of MPC's chip-select lines, only one chip-select line (CS0~) is used to select the flash as a whole, while distributing chip-select lines among the internal banks is done via on-board programmable logic, according to the Presence-Detect lines of the Flash SIMM inserted to the FADS. FIGURE 4-3 Flash Memory SIMM Architecture Flash Presence-Detect Lines ADD F_CS1~ M29F040 or 1M X 8 M29F040 or 1M X8 F_CS2~ CS0~ FADS's Logic M29F040 or 1M X 8 IN M29F040 or 1M X 8 M29F040 M29F040 IM M29F040 F_CS3~ F_CS4~ M29F040 EL DATA MCM29F020 SM73218 MCM29F040 SM73228 The Motorola SIMMs are built of AMD's Am29F0X0 devices which are 5V programmable, i.e., there is no need for external programming voltage and the flash may be written almostA as a regular memory. The SMART parts however, require 12V 0.5% programming voltage to be applied for programming. If on-boards programming of such device is required, a 12V supply needs to be connected to the FADS (P7). Otherwise, for normalB Flash operation, 12V supply is not required. The control over the flash is done using the GPCM and a dedicated CS0~ region, controlling the whole bank. During hard - reset initializations, the debugger reads the Flash Presence-Detect lines via BCSR2 and decides how to program BR0 & OR0 registers, within which the size and the delay of the region are determined. A. A manufacturer specific dedicated programming algorithm should be implemented during flash programming. B. I.e., Read-Only. 36 PR The access time of the Flash memory provided with the FADS is 90 nsec, however, 120 nsec devices may be used as well. Reading the delay section of the Flash SIMM Presence-Detect lines, the debugger establishes (via OR0) the correct number of wait-states (considering 50MHz system clock frequency). MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y M29F040 or 1M X 8 M29F040 or 1M X 8 M29F040 M29F040 M29F040 M29F040 or 1M X 8 M29F040 or 1M X 8 M29F040 MCM29F080 MOTOROLA Functional Description The performance of the flash memory is shown in TABLE 4-5. "Flash Memory Performance Figures" below: TABLE 4-5. Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] Flash Delay [nsec] Read / Writea Access [Clocks] 50 90 8 25 120 10 90 4 120 5 a. The figures in the table refer to the actual write access. The write operation continues internally and the device has to be polled for operation completion. The Flash module may disabled / enabled at any time by writing '1' / '0' the FlashEn~ bit in BCSR1. 4*8 Synchronous Dram The sdram connection scheme is shown in FIGURE 4-4 "SDRAM Connection Scheme" on page 38. The SDRAM's performance figures, are shown in TABLE 4-6. "Estimated SDRAM Performance Figures": PR TABLE 4-6. Estimated SDRAM Performance Figures Number of System Clock Cycles 50 5 3+1a 5,1,1,1 3,1,1,1 + 21 b 1a 3 2 + 1a 3,1,1,1 2,1,1,1 + 1a 13 b System Clock Frequency [MHz] EL The SDRAM's timing is controlled by UPMB via its assigned CS (See TABLE 4-1. "MPC8XXFADS Chip Selects' Assignment" on page 31) line. Unlike a regular dram the synchronous dram has a CS input in addition to the RAS and CAS signals. IM To enhance performance, the SDRAM is unbuffered from the MPC, saving the delay associated with address and data buffers. Since only 2 memory chips are involved, it does not adversely effect overall system performance. The SDRAM does not reside on a SIMM but is soldered directly to the FADS pcb. The SDRAM may be enabled / disabled at any time by writing 1 / 0 to the SDRAMEN bit in BCSR1. See TABLE 4-10. "BCSR1 Description" on page 48. IN To enhance performance, especially in higher operation frequencies - 4 MBytes of SDRAM is provided on board. The SDRAM is unbuffered from the MPC bus and is configured as 2 X 512K X 32. Use is done with two MB811171622A-100 chips by Fujitsu or compatibles. Single Read Single Write Burst Read Burst Write Refresh a. One additional cycle for RAS precharge b. 4-beat Refresh Burst, not including arbitration overhead. MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y 25 37 Functional Description FIGURE 4-4 SDRAM Connection Scheme CS4 GPL1 GPL2 GPL3 A10 GPL0 (A11) A(20:21) A(22:29) SDRAMEN SYSCLK BS0_B BS1_B CS RAS CAS W A11 A10 A(9:8) A(7:0) CKE CLK DQMU DQML DQ(15:0) D(0:15) BS2_B BS3_B D(16:31) CS RAS CAS W A11 A10 Mode Register programming values are shown in TABLE 4-7. "SDRAM's Mode Register Program- 38 PR After power-up, the sdram needs to be initialized by means of programming, to establish its mode of operation. Sdram is programmed by issuing a Mode Register Set command. During that command data is passed to the Mode Register through the sdram's address lines. This command is fully supported by the UPM by means of a dedicated Memory Address Register and a UPM command run option. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL 4*8*1 SDRAM Programming IM MOTOROLA IN AR Y A(7:0) CKE CLK DQMU DQML DQ(15:0) A(9:8) Functional Description ming" below: TABLE 4-7. SDRAM's Mode Register Programming Value @ Frequency SDRAM Option Burst Length Burst Type CAS Latency Write Burst Length 50MHz 4 Sequential 2 Burst 25MHz 4 Sequential 4*8*1*1 1) SDRAM Initializing Procedure After Power-up the SDRAM needs to be initialized in a certain manner, described below: 2) Memory controller's MPTPR, MBMR, OR4 and BR4 registers should be programmed according to TABLE 3-6. "Memory Controller Initializations For 20Mhz" on page 22 or TABLE 3-3. "Memory Controller Initializations For 50Mhz" on page 19. MAR should be set with proper value (0x48 for upto 32MHz or 0x88 for 32 - 50 MHz) MCR should be written with 0x80808105 to run the MRS command programmed in locations 5 - 8 of UPMB. MBMR's TLFB field should be changed to 8, to constitute 8-beat refresh Bursts. MCR should be written with 0x80808130 to run the refresh sequence (8 refresh cycles are performed now) MBMR's TLFB field should be restored to 4, to provide 4-beat refresh Bursts for normal operation. The SDRAM is initialized and ready for operation. 3) 4) 5) 6) 7) The SDRAM is refreshed using its auto-refresh mode. I.e., using UMPB's periodic timer, a burst of four auto-refresh commands is issued to the SDRAM every 62.4 sec, so that all 2048 SDRAM rows are refreshed within specified 32.8 msec. MOTOROLA PR 4*8*2 SDRAM Refresh MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN UPMB should be programmed with values described in TABLE 3-8. "UPMB Initializations for MB811171622A-100 upto 32MHz" on page 26 or in TABLE 3-9. "UPMB Initializations for MB811171622A-100, 32+MHz - 50MHz" on page 27. AR Y 1 Burst 39 Functional Description 4*9 Communication Ports Since the FADS platform is meant to serve all the MPC8XX family, it only contains modules that are common to all family members. The various communication ports for the present and future family members are shown in TABLE 4-8. "MPC8XX Family Comm. Ports" below: TABLE 4-8. MPC8XX Family Comm. Ports Family Member - MPC Comm. Port 801 Uart, IrDA Uart, IrDA 823 USB +Enet, Fast IrDA 821 +Enet +IrDA 860 +Enet 860SAR +Enet 860T +Enet SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPIa I2Ca Fast Enet Utopia +Enet, IrDA +Enet +Enet Uart TDM Only Uart Uart Uart IN Uart IM a. This is an interchip protocol and therefore will not be supported for evaluation. As can be seen from the above table the Ethernet, I/R and Uart (RS232) support are common to allA family members. Therefore, the FADS is equipped with 2 port of RS232, each with independent enable via BCSR and an IRDA transceiver, supporting Fast IRDA. 4*9*1 An Ethernet port with T.P. (10-Base-T) I/F is provided on the MPC8XXFADS. The comm. port over which this port resides, is determined according to the MPC typeB. Use is done with the MC68160 EEST 10-base-T transceiver, used also with the MPC8XXFADS. To allow alternative use of the Ethernet's SCC pins, they appear at the expansion connectors over the daughter-board and over the Comm. Ports expansion connector (P8) of the this board, while the Ethernet transceiver may be Disabled / Enabled at any time by writing '1' / '0' to the EthEn~ bit in BCSR1. 4*9*2 An infra-Red communication port is provided with the FADS - the Temic's TFDS 6000 integrated transceiver, which incorporates both the receiver and transmitter optical devices with the translating logic and supports Fast IrDA (upto 4 Mbps). The comm. port over which this port resides, is deter- A. Except for the MPC801 which does not have Ethernet support. B. I.e., routing is done on the daughter board. 40 PR Ethernet Port Infra-Red Port MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL AR Y +Enet, IrDA +Enet +Enet, IrDA +Enet +Enet Uart +Enet Uart Uart Uart MOTOROLA Functional Description mined according to the MPC typeB. To allow alternative use of the I/R's SCC or its pins, the infra-red transceiver may be disabled / enabled at any time, by writing '1' / '0' to the IrdEn~ bit in BCSR1, while all pins appear on the daughter-board expansion connector, as well as on P8 of this board. 4*9*2*1 1) 2) Infra-Red Port Rate Range Selection 9600 Bps to 1.2 MBps 1.2 MBps to 4 MBps. The TFDS6000 has 2 bit-rate ranges: When TX input is LOW at least 200 nsec before the falling edge of IrdEn~, then, the LOWER range is selected. If TX is HIGH for that period of time, then, the HIGHER range is selected. 4*9*3 RS232 Ports Use is done with 9 pins, female D-Type stacked connector, configured to be directly (via a flat cable) connected to a standard IBM-PC like RS232 connector. FIGURE 4-5 RS232 Serial Ports' Connector EL TX TX DTR IM DCD 1 2 3 4 5 6 7 8 9 GND 4*9*3*1 In the list below, the directions 'I', 'O', and 'I/O' are relative to the FADS board. (I.e. 'I' means input to the FADS) * * * * CD ( O ) - Data Carrier Detect. This line is always asserted by the FADS. TX ( O ) - Transmit Data. RX ( I ) - Receive Data. DTR ( I ) - Data Terminal Ready. This signal may be used by the software on the FADS to detect if a terminal is connected to the FADS board. DSRA ( O ) - Data Set Ready. This line is always asserted by the FADS. RTS ( I ) - Request To Send. This line is not connected in the FADS. CTS ( O ) - Clear To Send. This line is always asserted by the FADS. A. Since there are only 3 RS232 transmitters in the device, DSR is connected to CD. MOTOROLA PR * * * RS-232 Ports' Signal Description MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN DSR RTS CTS N.C. To assist user's applications and to provided convenient communication channels with both a terminal and a host computer, two identical RS232 ports are provided on the FADS. The MPC's communication ports to which these RS232 ports is routed, is established according to the type of MPC residing on the daughter board. Use is done with MC145707 transceivers which generates RS232 levels internally using a single 5V supply and are equipped with OE and shutdown mode. When the RS232EN1 or RS232EN2 bits in BCSR1 are asserted (low), the associated transceiver is enabled. When negated, the associated transceiver enters standby mode, in which the receiver outputs are tristated, enabling use of the associated port's pins, off-board via the expansion connectors. AR Y Selection between the 2 ranges is determined by the state of the transceiver's TX input on the falling edge of IrdEn~. 41 Functional Description 4*10 PCMCIA PortA To enhance PCMCIA i/f development, a dedicated PCMCIA port is provided on the FADS. Support is given to 5V only PC-Cards, PCMCIA standard 2.1+ compliant. All the necessary control signals are generated by the MPC itself. To protect MPC signals from external hazards, and to provide sufficient drive capability, a set of buffers and latches is provided over PC-Card's address, data & strobe lines. To conform with the design spirit of the FADS, i.e., making as much as possible MPC resources available for external application development, input buffers are provided for input control signals, controlled by the PCC_EN~ bit in BCSR1, so the PCMCIA port may be Disabled / Enabled at any time, by writing '1' / '0' to that bit. When the PCMCIA channel is disabled, its associated pins are available for off-board use via the expansion connectors. Since it is not desirableB to apply control signals to unpowered PC-Card, the strobe / data signal buffers / transceivers are tri-stated and may be driven only when the PC-Card is powered. The block diagram of the PCMCIA port is shown in FIGURE 4-6 "PCMCIA Port Configuration" on page 43. A. As the MPC801 does not have a PCMCIA port, this port is not operational with an MPC801 daughter board. B. This since the PC-Card might have protection diodes on its inputs, which will force down input signals regardless of their driven level. 42 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y A loudspeaker is provided on board and connected to SPKROUT line of the MPC. The speaker is buffered from the MPC and low-pass filtered. When the PCC_EN~ bit in BCSR1 is negated (high) the speaker buffer is tri-stated so the SPKROUT signal of the MPC may be used for alternate function. Functional Description FIGURE 4-6 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC From BCSR PCMCIA POWER CONTROL Power Logic LTC1315 or equiv. PCCVPP 1 1 1 5V 12V D[8:15] 8 D[0:7] 8 AR Y Data_A[15:8] Data_A[7:0] CE1 CE2 WE/PGM OE IORD,IOWR RESET Address_A[25:0] REG VDD OE VDD VDD 8 8 OE From BCSR 1 1 1 R/W CE1_A(B) CE2_A(B) WE/PGM OE PCMCIA_EN 1 1 1 1 2 1 1 1 2 1 IORD,IOWR RESET_A(B) IM MPC8XX On Daughter - Board EL 1 POE_A(B) A[6:31] IN buffer with OE Transparent latch with OE WAIT_A(B), IOIS16_A(B) RDY/BSY_A(B), BVD(1:2)_A(B) VDD CD(1:2)_A(B),VS(1:2)_A(B) LPF PR 26 1 26 1 REG 1 ALE_A(B) 2 2 3 5 3 4 1 SPKROUT 4 4*10*1 PCMCIA Power Control MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 43 Functional Description To support hot-insertionA the socket's power is controlled via a dedicated PCMCIA power controller the LTC1315 made by LINEAR TECHNOLOGY. This device, controlled by BCSR1, switches 12V VPP for card programming and controls gates of external MOSFET transistors, through which the PC Card VCC is switched. When a card is inserted while the channel is enabled via BCSR1, i.e., both of the CD(1:2)* (Card Detect) lines are asserted (low), the status of the voltage select lines VS(1:2)* should be read to determine the PC Card's operation voltage level according to which, PCCVCC(0:1) bits in BCSR1 should be set, to drive the correct VCC (5V) to the PC-Card. When a card is being removed from the socket while the channel is enabled via BCSR1, the negation of CD1~ and CD2~ may be sensed by the MPC and power supply to the card may be cut. Any application S/W handling the PCMCIA channel must check the Voltage-Sense lines before Power is applied to the PC-Card. Otherwise, if 5V power is applied to a 3.3V-Only card, permanent damage will be inflicted to the PC-Card. 4*11 Board Control & Status Register - BCSR The following functions are controlled / monitored by the BCSR: 1) 2) 3) 4) 5) 6) 7) 8) 9) MPC's Hard Reset Configuration. Flash Module Enable / Disable Dram Module Enable / Disable Dram port width - 32 bit / 16 bit. Ethernet port Enable / Disable. SDRAM Module Enable / Disable. Infra-Red port Enable / Disable. RS232 port 1 Enable / Disable. RS232 port 2 Enable / Disable. A. I.e., card insertion when the FADS is powered B. In fact only the upper 16 bits - D(0:15) are used, but the BCSR is mapped as a 32 bit wide register and should be accessed as such. C. Provided that support is provided also within the MPC. 44 PR * * * 13) USBD 10) BCSR Enable / Disable. 11) Hard Reset Configuration Source - BCSR0 / FlashC Memory 12) PCMCIA control which include: Channel Enable / Disable. PC Card VCC appliance. PC Card VPP appliance. Port Enable or UtopiaE Port Enable or 100-Base-TF Port Enable MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM Most of the hardware options on the MPC8XXFADS are controlled or monitored by the BCSR, which is a 32B bit wide read / write register file. The BCSR is accessed via the MPC's CS1 region and in fact includes 5 registers: BCSR0 to BCSR4. Since the minimum block size for a CS region is 32KBytes, BCSR0 - BCSR4 are multiply duplicated within that region. See also TABLE 3-1. "MPC8XXADS Main Memory Map" on page 17. IN AR Y WARNNING MOTOROLA Functional Description 14) USB Power Control. 15) Video Port Enable 16) Video Port Clock Select 17) Ethernet Port Control. 18) Dram Type / Size and Delay Identification. 19) Flash Size / Delay Identification. 20) External (off-board) tools identification or S/W option selection switch - DS1 status. 21) Daughter Board ID. 23) Daughter Board Revision code 22) Mother Board Revision code Since all of the FADS's modules are controlled by the BCSR and since they may be disabled in favor of external hardware, the enable signals for these modules are presented at both the daughter board connector and at the expansion connector over the daughter board, so that off- board hardware may be mutually exclusive enabled with on-board modules. 4*11*1 BCSR Disable Protection Logic The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not be changedA unless BCSR_EN_PROTECT~ bit in BCSR3 is written with '1' previously. D. For the MPC823 daughter board E. For the MPC860SAR daughter board F. For the MPC860T daughter board A. It may be written but will not be influenced. B. Provided that BCSR is not disabled. C. I.e., when VDDH to the MPC is powered. MOTOROLA PR BCSR0 is located at offset 0 on BCSR space. It may be read or written at any timeB. BCSR0 gets its defaults upon MAINC Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the data bus to provide the Hard-Reset configuration for the MPC, this, if the Flash_Configuration_Enable~ bit in BCSR1 is not active. BCSR0 may be written at any time to change the Hard-Reset configuration of the MPC. The new values become valid when the next HardReset is issued to the MPC regardless of the Hard-Reset source. The description of BCSR0 bits is MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL 4*11*2 BCSR0 - Hard Reset Configuration Register IM After the BCSR_EN_PROTECT~ is written with '1' to unprotect the BCSR_EN~ bit there is only one shot at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is re-activated and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if desired. IN The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR, an event from which only power re-appliance recovers, protection logic is provided: AR Y 45 Functional Description shown in TABLE 4-9. "BCSR0 Description" on page 46. TABLE 4-9. BCSR0 Description PON BIT MNEMONIC FUNCTION DEF. 0 1 2 3 4-5 6 7-8 ERB IP Reserved BDIS BPS(0:1) Reserved ISB(0:1) External Arbitration. When '0' during Hard-Reset, Arbitration is performed internally. When '1' during Hard-Reset, Arbitration is performed externally. 0 0 0 0 '00' 0 '10' R,W R,W R,W R,W R,W R,W R,W ATT Implementeda Boot Disable. When '0' during Hard-Reset, CS0~ region is enabled for boot. When '1', CS0~ region is disabled for boot. Boot Port Size. Determines the port size for CS0~ at boot. '00' - 32 bit, '01' 8 bit, '10' - 16 bit, '11' - reserved. 9 - 10 DBGC(0:1) 11-12 DBPC(0:1) EL Debug Pins Configuration. Value during Hard-Reset determines the function of the PCMCIA channel II pins. When '00' - these pins function as PCMCIA channel II pins, when '01' - they serve as Watch-Points,'10' Reserved, when '11' - they become show-cycle attribute pins, e.g., VFLS, VF... Debug Port Pins Configuration. Value during Hard-Reset determines the location of the debug port pins. When '00' - debug port pins are on the JTAG port, when '01' - debug port non-existent, '10' - Reserved, when '11' debug port is on PCMCIA channel II pins. External Bus Division Factor. Value during Hard Reset determines the factor upon which the CLKOUT of the MPC external bus, is divided with respect to its internal MPC clock. When '00' - CLKOUT is GCLK2 divided by 1, when '01', CLKOUT is GCLK2 divided by 2. Implementeda. Un-Implemented IM Initial Space Base. Value during Hard-Reset determines the initial base address of the internal MPC memory map. When '00' - initial space at 0, when '01' - initial space at 0x00F00000, when '10' - initial space at 0xFF000000, when '11' - initial space at 0xFFF00000. IN Implementeda AR Y Interrupt Prefix. When '0' during Hard-Reset, Interrupt prefix set to 0xFFF00000, if '1' Interrupt Prefix set to 0. '11' R,W '00' R,W 13 - 14 PR EBDF(0:1)b '00' R,W 15 16 - 31 Reserved Reserved '0' - R,W - a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset. b. Applicable for MPC's revision A or above. Otherwise have no influence. 4*11*3 BCSR1 - Board Control Register 1 The BCSR1 serves as a control register on the FADS. It is accessed at offset 4 from BCSR base address. It may be read or written at any timeA. BCSR1 gets its defaults upon Power-On reset. Most of BCSR1 pins are available at the daughter board connectors and on the expansion connectors A. Provided that BCSR is not disabled. 46 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Functional Description residing over the daughter boards, providing visibility towards daughter boards' and external logic. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 47 AR Y Functional Description BCSR1 fields are described in TABLE 4-10. "BCSR1 Description" on page 48. TABLE 4-10. BCSR1 Descriptiona PON BIT MNEMONIC Function DEF 0 FLASH_EN ATT. 1 DRAM_EN Dram Enable. When this bit is active (low), the DRAM module is enabled on the local memory map. When in-active, the DRAM is removed from the local memory map and CS2~ and CS3~b, to which the DRAM is connected may be used off-board via the expansion connectors. AR Y Flash Enable. When this bit is active (low), the Flash memory module is enabled on the local memory map. When in-active, the Flash memory is removed from the local memory map and CS0~, to which the Flash memory is connected may be used off-board via the expansion connectors. 0 R,W 0 R,W 2 ETHEN Ethernet Port Enable. When asserted (low) the EEST connected to SCC1 is enabled. When negated (high) that EEST is in standby mode, while all its system i/f signals are tri-stated. Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver, connected to SCC2 is enabled. When negated, the Infra-Red transceiver is put in shutdown mode. And SCC2 pins are available for off-board use via the expansion connectors. Flash Configuration Enable. When this bit is asserted (low): (A) - the Hard-Reset configuration held in BCSR0 is NOT driven on the data bus during Hard-Reset and (B) - configuration data held at the 1'st word of the flash memory is driven to the data bus during Hard-Reset. c 1 R,W IN 3 IRDEN 1 R,W 4 FLASH_CFG_EN IM 1 R,W EL 5 CNT_REG_EN_P ROTECT Control Register Enable Protect. When this bit is active (low) the BCSR_EN bit in that register can not be written. When in-active, BCSR_EN may be written to remove the BCSR from the memory map. After any write to BCSR1 this bit becomes active again. This bit is a read-onlyd bit on that register. BCSR Enable. When this bit is active (low) the Board Control & Status Register is enabled on the local memory map. When inactive, the BCSR may not be read or written and its associated CS1~ is available for off-board use via the expansion connectors. This bit may be written with '1' only if CNT_REG_EN_PROTECT bit is negated (1). When the BCSR is disabled it still continues to configure the board according the last data held in it even during Hard-Reset. 0 R 7 PR 6 BCSR_EN 0 R,W RS232EN_1 RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port 1, is enabled. When negated, the RS232 transceiver for port 1, is in standby mode and the relevant MPC communication port pins are available for offboard use via the expansion connectors. PC Card Enable. When asserted (low), the on-board PCMCIA channel is enabled, i.e., address and strobe buffers are enabled to / from the card. When negated, all buffers to / from the PCMCIA channel are disabled allowing off-board use of its associated lines. Pc Card VCC Select 0. These signal in conjunction with PCCVCC1 determine the voltage applied to the PCMCIA card's VCC. Possible values are 0 / 3.3 / 5 V. For the encoding of these lines and their associated voltages see TABLE 4-11. "PCCVCC(0:1) Encoding" on page 49. 1 R,W 8 PCCEN 1 R,W 9 PCCVCC0 0 R,W 48 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Functional Description TABLE 4-10. BCSR1 Descriptiona PON BIT MNEMONIC Function DEF 10 - 11 PCCVPP(0:1) ATT. PC Card VPP. These signals determine the voltage applied to the PCMCIA card's VPP. Possible values are 0 / 5 / 12 V. For the encoding of these lines and their associated voltages see TABLE 4-12. "PCCVPP(0:1) '11' R,W Encoding" on page 49. 12 Dram_Half_Word Dram Half Word. When this bit is active (low) and the steps listed in 4*6*1 "DRAM 16 Bit Operation" on page 32, are taken, the DRAM becomes 16 bit wide. When inactive the DRAM is 32 bit wide. 1 R,W 13 RS232EN_2 RS232 port 2 Enable. When asserted (low) the RS232 transceiver for port 2, is enabled. When negated, the RS232 transceiver for port 2, is in standby mode and the relevant MPC communication port pins are available for offboard use via the expansion connectors. AR Y 1 R,W 14 SDRAMEN 15 PCCVCC1 16 - 31 Reserved Un-implemented IM Pc Card VCC Select 1. These signal in conjunction with PCCVCC0 determine the voltage applied to the PCMCIA card's VCC. Possible values are 0 / 3.3 / 5 V. For the encoding of these lines and their associated voltages see TABLE 4-11. "PCCVCC(0:1) Encoding" on page 49. IN PC-Card VCC [V] 0 5 3.3 0 SDRAM Enable. When this bit is active (high), the SDRAM module is enabled on the local memory map. When in-active, the DRAM is place in low-power mode, in fact removed from the local memory map, allowing its associated CS line, to be used off-board via the expansion connectors. 1 R,W 0 R,W - - PR MOTOROLA EL 00 01 10 11 00 a. Shaded areas are additions with respect to the MPC8XXFADS. b. In case a Single Bank DRAM SIMM is used CS3~ is free as well. c. Provided that this option is supported by the MPC by driving address lines low and asserting CS0~ during Hard-Reset. d. It is written in BCSR3. TABLE 4-11. PCCVCC(0:1) Encoding PCCVCC(0:1) TABLE 4-12. PCCVPP(0:1) Encoding PCCVPP(0:1) PC Card VPP [V] 0 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 49 Functional Description TABLE 4-12. PCCVPP(0:1) Encoding PCCVPP(0:1) 01 10 11 PC Card VPP [V] 5 12a Hi-Z a. Provided that a 12V power supply is applied. 4*11*4 BCSR2 - Board Control / Status Register - 2 BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a read only register which may be read at any timeA. BCSR2's various fields are described in TABLE 4-13. A. Provided that BCSR is not disabled. 50 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Functional Description "BCSR2 Description" on page 51. TABLE 4-13. BCSR2 Descriptiona PON BIT MNEMONIC Function DEF 0-3 FLASH_PD(4:1) ATT. Encoding" on page 51. 4 5-8 Reserved DRAM_PD(4:1) Un-implemented AR Y Flash Presence Detect(4:1). These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket. There are additional 3 presence detect lines which encode the SIMM's delay but appear in BCSR3. For the encoding of FLASH_PD(4:1) see TABLE 4-14. "Flash Presence Detect (4:1) - R - R (4:3) Encoding" on page 52. 9 - 12 EXTTOLI(0:3) 13 - 15 DBREVN(0:2) EL External Tools Identification. These lines, which are available at the expansion connectors over the daughter board, are intended to serve as tools' identifier or as S/W option selection. On board s/w may check these lines to detect The presence of various tools (h/w expansions) at the expansion connectors or the state of a dedicated 4 switches dip-switch which resides over the same lines or a combination of both. Half of the available combinations is reserved while the other half is available to users' applications. For the external tools' codes and their associated combinations see TABLE 4-17. "EXTOOLI(0:3) Assignment" on page IN Dram Presence Detect. These lines are connected to the DRAM SIMM presence detect lines which encode the size and the delay of the DRAM SIMM mounted on the DRAM SIMM socket. For the encoding of DRAM_PD(4:1) see TABLE 4-15. "DRAM Presence Detect (2:1) Encoding" on page 52 and TABLE 4-16. "DRAM Presence Detect - R 52. Daughter Board Revision Number (0:2). This field represents the revision code, hard-assigned to each daughter board. This is a production revision which may be identical for different types of daughter boards. See TABLE IM - R 13 - 31 PR Reserved 4-18. "MPC8XXFADS Daughter Boards' Revision Encoding" on page 53, for revisions' encoding. - Un-implemented. a. Shaded areas are additions with respect to the MPC812/860ADS. TABLE 4-14. Flash Presence Detect (4:1) Encoding FLASH_PD(4:1) 0-3 4 5 6 Reserved SM732A2000 / SM73228 - 8 Mbyte SIMM, by SMART Modular Technologies. SM732A1000A / SM73218 - 4 Mbyte SIMM, by SMART Modular Technologies. MCM29080 - 8 MByte SIMM, by Motorola FLASH TYPE / SIZE MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 51 Functional Description TABLE 4-14. Flash Presence Detect (4:1) Encoding FLASH_PD(4:1) 7 8 9-F FLASH TYPE / SIZE MCM29040 - 4 MByte SIMM, by Motorola MCM29020 - 2 MByte SIMM, by Motorola Reserved TABLE 4-15. DRAM Presence Detect (2:1) Encoding DRAM_PD(2:1) 00 01 10 11 DRAM TYPE / SIZE MCM36100 by Motorola or MT8D132X by Micron- 4 MByte SIMM MCM36800 by Motorola or MT16D832X by Micron - 32 MByte SIMM MCM36400 by Motorola or MT8D432X by Micron - 16 MByte SIMM MCM36200 by Motorola or MT16D832X by Micron - 8 MByte SIMM TABLE 4-16. DRAM Presence Detect (4:3) Encoding DRAM_PD(4:3) 00 01 10 11 EL PR 52 EXTTOOLI(0:3) 0000-0111 1000-1110 1111 TABLE 4-17. EXTOOLI(0:3) Assignment External Tool Reserved User Available Non Existent MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM IN DRAM DELAY Reserved Reserved 70 nsec 60 nsec AR Y MOTOROLA Functional Description WARNING Since EXTOLI(0:3) lines may be DRIVEN LOW ('0') by the dip-switch, OFF-BOARD tools should NEVER DRIVE them HIGH. Failure in doing so, might result in PERMANENT DAMAGE to the FADS and / or to OFF-BOARD logic. TABLE 4-18. MPC8XXFADS Daughter Boards' Revision Encoding 0 1 2-7 ENG (Engineering) PILOT Reserved BCSR3 is an additional control / status register which may be accessed at offset 0xC from BCSR base address. BCSR3 gets its defaults during Power-On reset and may be read or written at any time. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 4*11*5 BCSR3 - Board Control / Status Register 3 AR Y 53 Revision Number (0:3) [Hex] MPC8XXFADS Daughter Board Revision Functional Description The description of BCSR3 is shown in TABLE 4-19. "BCSR3 Description" on page 54. TABLE 4-19. BCSR3 Description PON BIT MNEMONIC Function DEF 0-1 2-7 Reserved DBID(0:5) Implemented Daughter Board ID. This field holds a code for the daughter board ID. Each Daughter board carries a unique ID code. For the specific daughter boards' codes see TABLE 4-20. "Daughter Boards' ID Codes" on page 54. '00' R R ATT. 5a CNT_REG_EN_P ROTECT Control Register Enable Protect. When this bit is active (low) the BCSR_EN bit in that register can not be written. When in-active, BCSR_EN may be written to remove the BCSR from the memory map. After any write to BCSR1 this bit becomes active again. This bit is a write-only bit on that register. Un-Implemented AR Y 0 W 6-7 8 Reserved BREVN0 - R 12 BREVN1 EL Encoding" on page 55. Board Revision Number 1. Second bit of the Board Revision Number. See IM 9 - 11 FLASH_PD(7:5) Flash Presence Detect(7:5). These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket - U15. There are additional 4 presence detect lines which encode the SIMM's Type but appear in BCSR2. For the encoding of FLASH_PD(7:5) see TABLE 4-22. "FLASH Presence Detect (7:5) IN MPC8XX On D/B Reserveda. MPC813b Board Revision Number 0. This is the MS bit of the Board Revision Number. See TABLE 4-18. "MPC8XXFADS Daughter Boards' Revision Encoding" on page 53, for the interpretation of the Board Revision Number. - - R TABLE 4-18. "MPC8XXFADS Daughter Boards' Revision Encoding" on page 53, for the interpretation of the Board Revision Number. Implemented '0' R R 13 14 - 15 Reserved BREVN(2:3) a. This is a WRITE ONLY bit so it does not conflict with the DBID filed which is READ ONLY. PR Board Revision Number (2:3). The 2 LS bits of the Board Revision Number. See TABLE 4-18. "MPC8XXFADS Daughter Boards' Revision Encoding" on page 53, for the interpretation of the Board Revision Number. TABLE 4-20. Daughter Boards' ID Codes DBID(0:5) [HEX} 0 1 54 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Functional Description TABLE 4-20. Daughter Boards' ID Codes DBID(0:5) [HEX} 2 3 4 - 1F 20 21 22 23 24 25 - 3F MPC8XX On D/B MPC821 MPC823 Reserved MPC801 MPC850b MPC860 MPC860SARb MPC860Tb Reserved TABLE 4-21. MPC8XXFADS Revision Number Conversion Table Revision Number (0:3) [Hex] MPC8XXFADS Revision EL 0 1 2-F PR 4*11*6 MOTOROLA TABLE 4-22. FLASH Presence Detect (7:5) Encoding FLASH_PD(7:5) 000 001 010 011 100 - 111 IM 150 120 90 BCSR4 - Board Control / Status Register 4 The BCSR4 serves as a control register on the FADS. It is accessed at offset 10H from BCSR base address. It may be read or written at any timeA. BCSR4 gets its defaults upon Power-On reset. Most of BCSR4 pins are available at the daughter board connectors and on the expansion connectors MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN ENG (Engineering) PILOT Reserved a. To distinguish between MPC8XXFADS and MPC8XXFADS b. Future 8XX Members Flash Delay [nsec] Not Supported Not Supported AR Y 55 Functional Description residing over the daughter boards, providing visibility towards daughter boards' and external logic. BCSR4 fields are described in TABLE 4-23. "BCSR4 Description" on page 56. TABLE 4-23. BCSR4 Descriptiona PON BIT MNEMONIC Function DEF 0 ETHLOOP ATT. Ethernet port Diagnostic Loop-Back. When active (high), the MC68160 EEST is configured into diagnostic Loop-Back mode, where the transmit output is internally fed back into the receive section. Twisted Pair Full-Duplex. When active (low), the MC68160 EEST is put into full-duplex mode, where, simultaneous receive and transmit are enabled. Twisted Pair Signal Quality Error Test Enable. When active (low), a simulated collision state is generated within the EEST, so the collision detection circuitry within the EEST may be tested. 0 R,W 1 TFPLDL~ AR Y 1 R,W 2 TPSQEL~ 1 R,W 3 SIGNAL_LAMP 4 USB_ENb UTOPIA_ENc FETH_ENd / / 7 8 PR 6 USB_VCC0 EL 5 USB_SPEED USB Port Speed. When this signal is active (high) the USB transceiver of the MPC823 daughter board is in full-speed mode. When inactive, the USB transceiver is in low-speed mode. This signal has no function with any daughter board other the MPC823 or MPC850 daughter boards. IM USB port Enable or Utopia Port Enable or Fast Ethernet Port Enable. When this signal is active (low) it enables the USB port transceiver in case an MPC823 daughter board is attached to the FADS or it enables the Utopia port in case an MPC860SAR daughter board is attached to the FADS or it enables the Fast Ethernet Port (100-Base-T) if an MPC860T daughter board is connected. This signal has no function with the MPC801, MPC821 and MPC860 daughter boards. IN Signal Lamp. When this signal is active (low), a dedicated LED illuminates. When in-active, this led is darkened. This led is used for S/W signalling to user. 1 R,W 1 R,W 1 R,W USB Port VCC EN. When this signal is active (low), 5V power is enabled to the USB port. When inactive, power to the USB port is disconnected. This signal has no function with any daughter board other the MPC823 or MPC850 daughter boards. Implemented. 1 R,W Reserved. 0 1 R,W R,W VIDEO_ON Video Port Enable. When this signal is active (low), the Video-On Led on the MPC823FADSDB is lit. When inactive, the led is darkened. This is merely an indication that should be set by application S/W to indicate activity of the Video Port, after it has been enabled via the I2C port. This signal has no function with any daughter board other the MPC823 daughter board. A. Provided that BCSR is not disabled. 56 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Functional Description TABLE 4-23. BCSR4 Descriptiona PON BIT MNEMONIC Function DEF 9 VDO_EXT_CLK_ EN ATT. 10 VIDEO_RST Video Port Reset. when this active (low) signal is beinge asserted, the Video Encoder, located on the MPC823FADSDB, is being reset. For further informations see 2*4 "VIDEO Support" on page 4 of the MPC823FADSDB spec. This signal has no function with any daughter board other the MPC823 daughter board AR Y Video Port Clock Enable. When this signal is active (high), it enables an on-board 27MHz clock generator as a source for both the video encoder and the video port controller of the MPC823. The system programmer should avoid asserting this signal, until it is assured that the MPC823 is set to accept external video clock. Failure in doing so might result in permanent damage to the MPC823 and / or the onboard 27 MHz clock generator. This signal has no function with any daughter board other the MPC823 daughter board. 1 R,W 1 R,W 13 - 31 Reserved Un-implemented IM 12 DATA_VOICE Modem Tool Function Select. Effective only with MPC823AFDSDB. When This signal is high, the DATA function of the modem tool is selected. When low, the VOICE function of the modem tool is selected. IN 11 MODEM_EN Modem Enable for MPC823. When this signal is active (low) while an MPC823FADSDB is connected to the FADS, it is possible to operate the MPC821 Modem Tool. This signal has no function with any other daughter board. 1 R,W 1 R,W - - 4*12 The debug port of the MPC8XXFADS is implemented on-board, connected to the MPC via the JTAGA port. Since the locationB of the debug port is determined via the Hard-Reset configuration, It is important that the relevant configuration bits (see 4*1*6 "Reset Configuration" on page 29) are not changed, if working with the local debug port is desired. The debug port controller is interfaced to host computer via Motorola's ADI port, which is an 8-bit wide parallel port. Since the debug port is serial, conversion is done by hardware between the parallel and serial protocols. The MPC's debug port is configured at SOFT-Reset to "Asynchronous Clock Mode" i.e., the debug port generates the debug clock - DSCK, which is asynchronous with the MPC system clock. The debug port controller block diagram is shown in FIGURE 4-7 "Debug Port Controller Block Diagram" on page 58. A. The debug port location is determined by the HARD - Reset configuration. B. In terms of MPC pins. MOTOROLA PR Debug Port Controller MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL a. Shaded areas are additions with respect to the MPC8XXFADS. b. MPC823 Daughter Board function. c. MPC860SAR Daughter Board function. d. MPC860T Daughter Board function. e. I.e., on the negative edge. 57 Functional Description FIGURE 4-7 Debug Port Controller Block Diagram ADI Port Connector Debug Port Conn. Daughter Board Connector ADI Address Selection ADI - Handshake Logic & Port Control HRESET* SRESET* S0 Control / Status Register Data Register Parallel <--> Serial Converter IN IM In this state, VFLS(0:1) or FRZB signals are routed to the debug port connector, so that, the external debug port controller has run mode status information. The ADI I/F supports upto 8 boards connected on the same bundle. Address selection is done by DS2 / 1,2,3. See 2*3*1 "ADI Port Address Selection" on page 7. The debug port I/F has two registers: a control / status register and a data register. The control / status register hold I/F related control / status functions, while the data register serves as the parallel side of the Transmit / Receive shift register. The control / status register is accessed when D_C~ bit is low while the data register is accessed when D_C~ is driven high by the host via the ADI port. 4*12*1 The FADS may be used as a debug port controller for a target system, provided that the target system A. I.e., debug port controller outputs are tri-stated, allowing debug port to be driven by an external debug-tool. B. Depended on H/W settings. 58 PR When the ADI's 37 lead cable is disconnected from either the ADI connector or from the FADS's 37 pin connector, the debug port controller is disabled allowing either the connection of an external debug port controller, or independent s/w run, i.e., the MPC boots from the flash memory to run user's application without debug port controller intervention. This feature becomes especially handy regarding demo's. MPC8XXFADS As Debug Port Controller For Target System MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL To allow for an external debug port controller to be incorporated with the FADS and to allow target system debug by the FADS, a standard 10 pin, debug port connector is provided and the local debug port controller may be disabledA by removing the ADI bundle from the its connector. AR Y 1 VFLS0 0 1 1 0 S 1 0 VFLS1 FRZ CHINS* DSDI DSCK DSDO '1' J1 '0' MOTOROLA Functional Description has a 10 pin header connector matching the one on the FADS. In this mode of operation, the on-board debug port controller, is connected to the target system's debug-port connector (see 4*12*1*1 "Debug Port Connection - Target System Requirements" below). Since DSDO signal is driven by the MPC, it is a must, to remove the local MPC from its socket, to avoid contention over this line. When either the local MPC is removed from its socket or the daughter board is removed from the FADS, all FADS's modules are inaccessible, except for the debug-port controller. All module-enable indications are darkened, regardless of their associated enable bits in the BCSR. Pull-up resistors are connected to Chip-Select lines, so they do not float when the MPC is removed from its socket, avoiding possible contention over data-bus lines. In order for a target system may be connected to the FADS, as a debug port controller, few measures need to be taken on the target system: 1) 2) A 10-pin header connector should be made available, with electrical connections matching FIGURE 4-8 "Standard Debug Port Connector" on page 61. Pull-down resistors, of app. 1K should be connected over DSDIA and DSCKA signals. These resistors are to provide normalB operation, when a debug-port controller, is not connected to the target system The debug-port should be enabled and routed to the desired pins. See the DBGC and DBPC fields within the HARD-RESET configuration word. 3) 4*12*2 Debug Port Control / Status Register A. Remember that the location of DSDI and DSCK is determined by the HARD-Reset configuration. B. Normal - i.e., boot via CS0~. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM The control / status register is an 8 bit register (bit 7 stands for MSB). For the description of the ADI IN AR Y 4*12*1*1 Debug Port Connection - Target System Requirements 59 Functional Description control status register see TABLE 4-24. "Debug Port Control / Status Register" on page 60. TABLE 4-24. Debug Port Control / Status Register I/F Res et DEF - BIT MNEMONIC Function ATT. 7 6 MpcRst TxError Mpc Reset. When this status only bit indicates when active (high) that either a SOFT or a HARD reset is driven by the MPC. Transmit Error. When this status only bit is active (high) it indicates that the last transmission towards the MPC, was cut by an internal MPC8XX reset source. This bit is updated for each byte sent. In Debug Mode. When this status only bit is active (high) it indicates that the MPC is in debug modea. R R AR Y 5 4-3 InDebug DebugClockFreq '00' R R/W Debug Clock Frequency Select. This field controls a frequency divider which divides DSCK. For the division factors and associated DSCK frequencies see TABLE 4-25. "DSCK Frequency Select" below. 2 StatusRequest 1 DiagLoopBack 0 DebugEntry EL Diagnostic Loopback Mode. When this control bit is active (low) the I/F is placed in Diagnostic Loopback Mode. I.e., DSDI is connected internally to DSDO, DSDI is tri-stated, and each data byte sent to the I/F data register, is sampled back into the receive shift register. This mode allows for complete ADI I/F test, upto transmit and receive shift registers. Upon I/F reset this bit wakes-up active. IM Status Request. When the host writes this bit active (low), the I/F will issue a status read request to the host by asserting ADS_REQ line to the host. When the host writes the control register with this bit negated, no status read request is issued. Upon I/F reset this bit wakes-up active. IN DSCK Frequency [MHz] 10 5 2.5 1.25 0 R/W 0 R/W a. Provided that the PCMCIA channel II pins are configured as debug pins - i.e, VFLS(0:1) signals are available. If not, the debug port can not be operated correctly. PR Debug Mode Entry. When this bit is active (low), the MPC will enter debug mode instantly after SOFT reset. When inactive, the MPC will start executing normally and will enter debug mode only after exception. Upon I/F reset this bit wakes-up active. 0 R/W TABLE 4-25. DSCK Frequency Select DebugClockFreq 00 01 10 11 60 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Functional Description FIGURE 4-8 Standard Debug Port Connector 1 VFLS0 GND GND 3 5 2 4 6 VFLS1 8 10 DSDI DSDO SRESET DSCK HRESET 7 VDD 9 4*12*3 Standard MPCXXX Debug Port Connector Pin Description The pins on the standard debug port connector are the maximal group needed to support debug port controllers for both the MPC5XX and MPC8XX families. Some of the pins are redundant for the MPC8XX family but are necessary for the MPC5XX family. 4*12*3*1 VFLS(0:1) These pins indicate to the debug port controller whether or not the MPC is in debug mode. When both VFLS(0:1) are at '1', the MPC is in debug mode. These lines may serve alternate functions with the MPC, in which case FRZ needs to selected, on either the FADS or target systemA. 4*12*3*2 HRESET* 4*12*3*3 SRESET* 4*12*3*4 DSDI - Debug-port Serial Data In Via the DSDI signal, the debug port controller sends its data to the MPC. The DSDI serves also a role during soft-reset configuration. (See 4*1*6*3 "Soft Reset Configuration" on page 29). 4*12*3*5 DSCK - Debug-port Serial Clock During asynchronous clock mode, the serial data is clocked into the MPC accordingC to the DSCK clock. The DSCK serves also a role during soft-reset configuration. (See 4*1*6*3 "Soft Reset Configuration" on page 29). 4*12*3*6 DSDO - Debug-port Serial Data Out DSDO is clocked out by the MPC according to the debug port clock, in parallelD with the DSDI being clocked in. The DSDO serves also as "READY" signal for the debug port controller to indicate that the debug port is ready to receive controller's command (or data). A. If a target system needs to use VFLS(0:1) alternate function, then, FRZ line should be connected to both VFLS(0:1) pins on the debug port connector. B. In fact that configuration is divided into 2 parts, the first is sampled 3 system clock cycles prior to the rising edge of SRESET* and the second is sampled 8 clocks after that edge. C. I.e., DSDI must meat setup / hold time to / from rising edge of the DSCK. D. I.e., full-duplex communication. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL This is the Soft-Reset bidirectional signal of the MPC8XX. On the MPC5XX it is an output. The debug port configuration is sampled and determined on the rising-edgeB of SRESET* (for both processor families). On the MPC8XX it is a bidirectional signal which may be driven externally to generate soft reset sequence. This signal is in fact redundant regarding the MPC8XX debug port controller since there is a soft-reset command integrated within the debug port protocol. However, the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s/w. IM This is the Hard-Reset bidirectional signal of the MPC. When this signal is asserted (low) the MPC enters hard reset sequence which include hard reset configuration. This signal is made redundant with the MPC8XX debug port controller since there is a hard-reset command integrated within the debug port protocol. However, the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s/w. IN AR Y 61 Functional Description 4*13 Power 1) I/O 2) Internal Logic 3) Keep Alive 4) PLL There are 4 power buses with the MPC8XXs: and there are 3 power buses on the MPC8XXFADS: 1) 5V bus 3) 12V bus FIGURE 4-1 MPC8XXFADS Power Scheme FADS Logic & Peripherals Daughter Board Con. IN 2V VDDSYN AR Y K.A. VDDL VDDH 2) 3.3V bus PR 5V PCMCIA Power Control VCC PC-Card Socket EL PCMCIA Buffers IM 3.3V VKA MPC8XX VPP 12V DAUGHTER BOARD MOTHER BOARD To support off-board application development, the power buses are connected to the expansion connectors, so that external logic may be powered directly from the board. The maximum current allowed to be drawn from the board on each bus is shown in TABLE 4-26. "Off-board Application Maximum 62 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Expansion Con. Functional Description Current Consumption" below. TABLE 4-26. Off-board Application Maximum Current Consumption Power BUS 5V 3.3V 2V 12V Current 2A 2A 0.5A 100 mA. To protect on board devices against supply spikes, decoupling capacitors (typically 0.1F) are provided between the devices' power leads and GND, located as close as possible to the power leads. 4*13*1 5V Bus 4*13*2 3.3V Bus The sole purpose of the 12V bus is to supply VPP (programming voltage) for the PCMCIA card and for the Flash SIMMB. It is connected to a dedicated input connector via a fuse (1A) and protected from over / reverse voltage application. If the 12V supply is not required for either the PC-Card and for the flash SIMM, the 12V input to the FADS may be omitted. A. At full speed. When lower performance is needed the internal logic may be powered from the 2V bus. B. If necessary. MOTOROLA PR 4*13*3 12V Bus MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL The MPC itself as well as the SDRAM, the address and data buffers are powered by the 3.3A bus, which is produced from the 5V bus using a special low-voltage drop, linear voltage regulator made by Micrel, the MIC29500-3.3BT which is capable of driving upto 5A, facilitating operation of external logic as well. IM To protect against reverse-voltage or over-voltage being applied to the 5V inputs a set of high-current diodes and zener diode is connected between the 5V bus GND. When either over or reverse voltage is applied to the FADS, the protection logic will blow the fuse, while limiting the momentary effects on board. IN Some of the FADS peripherals reside on the 5V bus. Since the MPC is 5V friendly, it may operate with 5V levels on its lines with no damage. The 5V bus is connected to an external power connector via a fuse (5A). AR Y 63 Support Information 5 - Support Information In this chapter all information needed for support, maintenance and connectivity to the MPC8XXFADS is provided. 5*1 1) 2) 3) 4) 5) 6) 7) 8) 9) Interconnect Signals P1 - ADI Port connector PA2 - RS232 port 1 P3 - Ethernet port P4 - PCMCIA port P5 - External Debug port controller input / output P6 - 5V Power In P7 - 12V Power In P8 - Serial Ports' Expansion connector PB2 - RS232 port 2 The MPC8XXFADS interconnects with external devices via the following set of connectors: 10) PD1, PD2, PD3 & PD4 - Daughter-Board Connectors 5*1*1 P1 ADI - Port Connector TABLE 5-1 P1 - ADI Port Interconnect Signals Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PD1 PD3 PD5 PD7 D_C~ HST_ACK Signal Name IM The ADI port connector - P1, is a 37-pin, Male, 90o, D-Type connector, signals of which are described in TABLE 5-1 "P1 - ADI Port Interconnect Signals" below: PR ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 ADS_REQ ADS_ACK HOST_REQ ADS_SRESET 64 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Not connected with this application Data / Control selection. When '1', the debug port controller's data register is accessed, when '0' the debug port controller's control register is accessed. Host Acknowledge input signal from the host. When asserted ('1') and the FADS is selected by the host, generates Soft Reset to the MPC. When asserted ('1') and the FADS is selected by the host, generates Hard Reset to the MPC. ADI I/F address line 2 (MSB). ADI I/F address line 1. ADI I/F address line 0 (LSB). HOST Request input signal from the host ADS Request output signal from the MPC8XXFADS to the host ADS Acknowledge output signal from the MPC8XXFADS to the host Not connected with this application Not connected with this application Not connected with this application Not connected with this application Bit 1 of the ADI port data bus Bit 3 of the ADI port data bus Bit 5 of the ADI port data bus Bit 7 of the ADI port data bus IN AR Y Description MOTOROLA Support Information TABLE 5-1 P1 - ADI Port Interconnect Signals Pin No. 20 - 25 26 27 - 29 30 HOST_VCC HOST_ENABLE~ Signal Name GND Ground. Not connected with this application Description HOST VCC input from the host. Used to qualify FADS selection by the host. When host is off, the debug port controller is disabled. HOST Enable input signal from the host. (Active low). Indicates that the host computer is connected to FADS. Used, in conjunction with HOST_VCC and ADS_SEL(2:0) to qualify FADS selection by the host. Ground. Bit 2 of the ADI port data bus Bit 4 of the ADI port data bus Bit 6 of the ADI port data bus 31 - 33 34 35 36 37 GND PD0 PD2 PD4 PD6 5*1*2 PA2, PB2 - RS232 Ports' Connectors The RS232 ports' connectors - PA2 and PB2 are 9 pin, 90o, female D-Type Stacked connectors, signals of which are presented in TABLE 5-2. "PA2, PB2 Interconnect Signals" below TABLE 5-2. PA2, PB2 Interconnect Signals 1 2 3 4 5 6 7 8 9 CD TX RX DTR GND DSR RTS (N.C.) CTS - Carrier Detect output from the MPC8XXFADS. Transmit Data output from the MPC8XXFADS. PR 5*1*3 Signal Name TPTX TPTX~ P3 - Ethernet Port Connector The Ethernet connector on the MPC8XXFADS - P3, is a Twisted-Pair (10-Base-T) compatible connector. Use is done with 90o, 8-pin, RJ45 connector, signals of which are described in TABLE 5-3. "P3 - Ethernet Port Interconnect Signals" below. TABLE 5-3. P3 - Ethernet Port Interconnect Signals Pin No. 1 2 EL Not connected Receive Data input to the MPC8XXFADS. Data Terminal Ready input to the MPC8XXFADS. Ground signal of the MPC8XXFADS. Data Set Ready output from the MPC8XXFADS. Request To Send. This line is not connected in the MPC8XXFADS. Clear To Send output from the MPC8XXFADS. IM Pin No. Signal Name Twisted-Pair Transmit Data positive output from the MPC8XXFADS. Twisted-Pair Transmit Data negative output from the MPC8XXFADS. MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN AR Y Description Description Bit 0 of the ADI port data bus 65 Support Information TABLE 5-3. P3 - Ethernet Port Interconnect Signals Pin No. 3 4 5 6 7 8 Signal Name TPRX TPRX~ - Description Twisted-Pair Receive Data positive input to the MPC8XXFADS. Not connected Not connected Twisted-Pair Receive Data negative input to the MPC8XXFADS. Not connected 5*1*4 PCMCIA Port Connector The PCMCIA port connector - P4, is a 68 - pin, Male, 900, PC Card type, signals of which are presented in TABLE 5-4. "P4 - PCMCIA Connector Interconnect Signals" below TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals 1 2 3 4 5 6 7 8 9 GND PCCD3 PCCD4 PCCD5 PCCD6 PCCD7 BCE1A~ PCCA10 OE~ I/O I/O I/O I/O I/O O Ground. PCMCIA Data line 3. PCMCIA Data line 4. PCMCIA Data line 5. PCMCIA Data line 6. PCMCIA Data line 7. PR PCCA11 PCCA9 PCCA8 PCCA13 PCCA14 WE~/PGM~ RDY PCCVCC 10 11 12 13 14 15 16 17 66 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O O O O O O O O I O IM PCMCIA Chip Enable 1. Active-low. Enables EVEN numbered address bytes. PCMCIA Address line 10. PCMCIA Output Enable signal. Active-low. Enables data outputs from PC-Card during memory read cycles. PCMCIA Address line 11. PCMCIA Address line 9. PCMCIA Address line 8. PCMCIA Address line 13. PCMCIA Address line 14. PCMCIA Memory Write Strobe. Active-low. Strobes data to PCCard during memory write cycles. +Ready/-Busy signal from PC-Card. Allows PC-Card to stall access from the host, in case a previous access's processing is not completed. 5V VCC for the PC-Card. Switched by the MPC8XXFADS, via BCSR1. IN Pin No. Signal Name Attribute AR Y Description Not connected MOTOROLA Support Information TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals Pin No. 18 Signal Name PCCVPP Attribute O Description 12V/5V VPP for the PC-Card programming. 12V available only if12V is applied to P8. Controlled by the MPC8XXFADS, via BCSR1. PCMCIA Address line 16. PCMCIA Address line 15. PCMCIA Address line 12. PCMCIA Address line 7. PCMCIA Address line 6. PCMCIA Address line 5. PCMCIA Address line 4. PCMCIA Address line 3. PCMCIA Address line 2. PCMCIA Address line 1. PCMCIA Address line 0. PCMCIA Data line 0. PCMCIA Data line 1. PCMCIA Data line 2. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PCCA16 PCCA15 PCCA12 PCCA7 PCCA6 PCCA5 PCCA4 PCCA3 PCCA2 PCCA1 PCCA0 PCCD0 PCCD1 PCCD2 WP GND GND CD1~ PCCD11 PCCD12 PCCD13 PCCD14 PCCD15 BCE2A~ VS1 IORD~ IOWR~ PCCA17 O O O O O O O O O O O I/O I/O I/O I PR MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I I/O I/O I/O I/O I/O O I O O O IM Ground Ground Write Protect indication from the PC-Card. Card Detect 1~. Active-low. Indicates in conjunction with CD2~ that a PC-Card is placed correctly in socket. PCMCIA Data line 11. PCMCIA Data line 12. PCMCIA Data line 13. PCMCIA Data line 14. PCMCIA Data line 15. PCMCIA Chip Enable 2. Active-low. Enables ODD numbered address bytes. Voltage Sense 1 from PC-Card. Indicates in conjunction with VS2 the operation voltage for the PC-Card. I/O Read. Active-low. Drives data bus during I/O-Cards' read cycles. I/O Write. Active-low. Strobes data to the PC-Card during I/OCard write cycles. PCMCIA Address line 17. IN 67 AR Y Support Information TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals Pin No. 47 48 49 50 51 52 Signal Name PCCA18 PCCA19 PCCA20 PCCA21 PCCVCC PCCVPP Attribute O O O O O O PCMCIA Address line 18. PCMCIA Address line 19. PCMCIA Address line 20. PCMCIA Address line 21. Description 5V VCC for the PC-Card. Switched by the MPC8XXFADS, via BCSR1. 12V/5V VPP for the PC-Card programming. 12V available only if12V is applied to P8. Controlled by the MPC8XXFADS, via BCSR1. PCMCIA Address line 22. PCMCIA Address line 23. PCMCIA Address line 24. PCMCIA Address line 25. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PCCA22 PCCA23 PCCA24 PCCA25 VS2 RESET WAITA~ INPACK~ PCREG~ BVD2 BVD1 O O O O I O I I Voltage Sense 2 from PC-Card. Indicates in conjunction with VS1 the operation voltage for the PC-Card. Reset signal for PC-Card. PR PCCD8 PCCD9 PCCD10 CD2~ GND 5*1*5 P5 - External Debug Port Controller Input Interconnect. The debug port connector - P5, is a 10 pin, Male, header connector, signals of which are described 68 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O I I I/O I/O I/O I IM Ground. Cycle Wait from PC-Card. Active-low. Input Port Acknowledge. Active-low. Indicates that the Pc-Card can respond to I/O access for a certain address. Attribute Memory or I/O Space - Select. Active-low. Used to select either attribute (card-configuration) memory or I/O space. Battery Voltage Detect 2. Used in conjunction with BVD1 to indicate the condition of the PC-Card's battery. Battery Voltage Detect 1. Used in conjunction with BVD2 to indicate the condition of the PC-Card's battery. PCMCIA Data line 8. PCMCIA Data line 9. PCMCIA Data line 10. Card Detect 2~. Active-low. Indicates in conjunction with CD1~ that a PC-Card is placed correctly in socket. IN AR Y MOTOROLA Support Information in TABLE 5-5. "P5 - Interconnect Signals" below TABLE 5-5. P5 - Interconnect Signals Pin No. 1 Signal Name VFLS0 Attribute O Description Visible history FLushes Status 0. Indicates in conjunction with VFLS1, the number of instructions flushed from the core's history buffer. Indicates also whether the MPC is in debug mode. If not using the debug port, may be configured for alternate function. When the FADS is disconnected from the ADI bundle, it may be FRZ signal, depended on J1's position. Soft Reset line of the MPC. Active-low, Open-Drain. Ground. 2 3 4 SRESET~ GND DSCK I/O I/O 5 6 7 8 GND VFLS1 HRESET~ DSDI O I/O Ground See VFLS0. When the FADS is disconnected from the ADI bundle, it may be FRZ signal, depended on J1's position. Hard Reset line of the MPC. Active-low, Open-Drain I/O 9 10 V3.3 DSDO 5*1*6 The 5V power connector - P6, is a 3-lead, two-part terminal block. The male part is soldered to the pcb, while the receptacle is connected to the power supply. That way fast connection / disconnection of power is facilitated and physical efforts are avoided on the solders, which therefore maintain solid connection over time. Pin Number 1 2 PR Signal Name 5V GND P6 - 5V Power Connector EL O I/O TABLE 5-6. P6 - Interconnect Signals Description 5V input from external power supply. GND line from external power supply. MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM Debug Serial Data In of the debug port. Configured on the MPC's JTAG port. When the debug-port controller is on the local MPC or when the FADS is a debug-port controller for a target system - OUTPUT, when the ADI bundle is disconnected from the FADS - INPUT. 3.3V Power indication. This line is merely for indication. No significant power may be drawn from this line. Debug Serial Data Output from the MPC. Configured on the MPC's JTAG port. When the debug-port controller is on the local MPC or when the ADI bundle is disconnected from the FADS - OUTPUT, when the FADS is a debug-port controller for a target system - INPUT. IN Debug Serial Clock. Over the rising edge of which serial date is sampled by the MPC from DSDI signal. Over the falling edge of which DSDI is driven towards the MPC and DSDO is driven by the MPC. Configured on the MPC's JTAG port. When the debug-port controller is on the local MPC or when the FADS is a debug-port controller for a target system - OUTPUT, when the FADI bundle is disconnected from the FADS - INPUT. AR Y 69 Support Information TABLE 5-6. P6 - Interconnect Signals Pin Number 3 Signal Name GND Description GND line from external power supply. 5*1*7 P7 - 12V Power Connector The 12V power connector - P7, is a two-lead, 2 part, terminal block connector, identical in type to the 5V connector. P7 supplies, when necessary, programming voltage to the Flash SIMM and / or to the Pin Number 1 2 Signal Name 12V GND Description 12V input from external power supply. GND line from external power supply. 5*1*8 P8 - Serial Ports' Expansion Connector P8 is a 96 pin, Female, DIN 41612 connector. 5*1*9 PD1, PD2, PD3 & PD4 - Daughter Boards' Connectors Interconnect Signals To be described in the next edition of this document. In this section the MPC8XXFADS's bill of material is listed according to their reference designation. To be added in the next edition of this document. A. True for the MPC860, but true upto an extent for other derivatives. 70 PR 5*2 MPC8XXFADS Part List MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Since the pinout of P8 is specific to the Daughter-Board connected to the FADS, it is described in each Daughter-Board User's manual. IM P8 is the serial ports expansion connector. Its is compatibleA with the QUADS board and with the previous MPC8XXFADS. IN PCMCIA slot. AR Y MOTOROLA TABLE 5-7. P7 - Interconnect Signals Support Information APPENDIX A - Programmable Logic Equations The MPC8XXFADS has 3 programmable logic devices on it. Use is done with MACH220-12 by AMD. These device support the following function on the FADS: 1) 2) 3) U7 - Debug Port Controller U10 - auxiliary board control functions, e.g,. buffers control, local interrupter, reset logic, etc'. U11 - the BCSR. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 71 AR Y Support Information A*1 U2 - Debug Port Controller "****************************************************************************** "****************************************************************************** "* MPC8XX FADS Debug Port Controller. "* Mach controller for an interface between Sun ADI port at one side, to "* debug port at the other. * * * "****************************************************************************** "* In this file (8): "* - Added support for VFLS / FRZ switching, for both normal operation and "* "* "* "* "* "* "* "* external debug station connected to the FADS. Support includes: - separating vfls between MPC and debug port. - Selection between frz / vfls (default) is done by VflsFrz~ input pin. - Selection between on-board / off-board vfls/frz is done by ChinS~ coming from the expansion connectors. selected, i.e., either ADI is disconnected or addresses don't match. "****************************************************************************** "* In this file (7): "* - BundleDelay field in the control register is changed to debug port "* "* "* "* "* clock frquency select according to the following values: 0 - divide by 8 (1.25 Mhz) 1 - divide by 4 (2.5 Mhz) 2 - divide by 2 (5 Mhz) 3 - divide by 1 (10 Mhz) default. "* - Added clock divider for 2 , 4, 8 output of which is routed externaly "****************************************************************************** "* In this file (6): "* - RUN siganl polarity was changed to active-high, this, to support "* other changes for revision PILOT of the fads. "****************************************************************************** "* In this file (5) added: "* - protection against spikes on the reset lines, so that the interface "* will not be reset by an accidental spike. "* - D_C~ signal was synchronized to avoid accidental write to control "* during data write. "* - DSDI is given value (H) prior to negation of SRESET* to comply with 5XX "* family "****************************************************************************** "* In this file (4) the polarity of address selection lines is reversed so 72 PR "* to the i/f clock input. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN - VFLS(0:1) are driven towards the debug-port connector when board is not AR Y MOTOROLA Support Information "* that ON the switch represent address line at high and vice-versa "****************************************************************************** "* In this file (3) the IClk is not reseted at all so it can be used to "* sync MPC8XX reset signals inside. "* Added consideration for reset generated by the MPC8XX: "* - when MPC8XX is reset (i.e., its hard | soft reset signals are asserted, "* "* "* it is not allowed for the host to initiate data trnasfer towards the MPC8XX. It can however, access the control / status register to either change parameters and / or check for status. "* - The status of reset signals is added to the status register, so it can "* be polled by the host. "****************************************************************************** module dbg_prt8 title 'MPC8XXFADS Debug Port Controller' "****************************************************************************** "* Device declaration. * U02 device 'mach220a'; "****************************************************************************** "* ####### "* # "* # "* ##### "* # "* # # # * # # EL ##### # # # # # ###### # IM ##### # # # # # ## ## # # # ##### # # # # "****************************************************************************** IN # # # ## # # # # ## ## # ###### # # # # ## ## ##### # # PR # # "* ####### # # ###### "****************************************************************************** "****************************************************************************** "* Pins declaration. * "****************************************************************************** "ADI Port pins. HstReq PIN 20 ; "Host to ADS, write pulse. (IN) AdsAck PIN 31 ISTYPE 'reg, buffer'; MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y # # # # # ###### # #### # #### # # * * * * * * #### "ADS to host, write ack. "(OUT,3s) 73 Support Information AdsReq PIN 2 ISTYPE 'reg, buffer'; "signal. (OUT,3s) "ADS to host, write HstAck PIN 54; "Host to ADS, write ack. (IN) AdsHardReset PIN 50; "Host to ADS, Hard reset. (IN) AdsSoftReset PIN 17; "Host to ADS, Soft reset. (IN) HstEn~ PIN 3; "Host connected to ADS. HostVcc PIN 49; "Host to ADS, host is on. D_C~ PIN 51; "Host to ADS, select data "or control access. AdsSel0 AdsSel1 AdsSel2 PIN 22; PIN 21; PIN 9; AdsAddr0 AdsAddr1 AdsAddr2 PIN 7; PIN 6; AdsSelect~ "****************************************************************************** "* MPC pins. Including debug port. * "****************************************************************************** PdaHardReset~ PdaSoftReset~ VFLS0 VFLS1 Freeze DSCK DSDI DSDO PIN 40; PIN 65; PIN 10 ; PIN 11 ; PIN 24; "Debug/Trap mode, report. (IN) "Alternative debug mode report (IN) "Pda's hard reset input. (I/O. o.d.) PR PIN 47 istype 'com'; "Pda's debug serial data in (Out) PIN 4; " MPC8XX's debug serial data output (In) "****************************************************************************** "* Dedicated Debug Port pins. "****************************************************************************** 74 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL PIN 5; "ADS board address switch. (IN) NODE ISTYPE 'com, buffer'; "ADS selection indicator. (OUT) PIN 48 istype 'com'; "Pda's debug port clock. (Out) IM "Host to ADS, card addr. "Pda's soft reset output. (I/O. o.d.) IN AR Y (IN) (IN) (IN) (IN) MOTOROLA Support Information VflsP0 VflsP1 VflsFrz~ PIN 38 istype 'com'; PIN 37 istype 'com'; PIN 13; " selectes between VFLS/FRZ from MPC "****************************************************************************** "* Mach to ADI data bus. * "****************************************************************************** PD7, PD6, PD5, PD4, PD3, PD2, PD1, PD0 PIN 66,60,67,59,58,57,56,55; "ADI data bus.(I/O) "****************************************************************************** "* Clock gen pins. IN * # ## ## # # # # # ## # # # # ## ## ###### # # "****************************************************************************** DbgClk DbgClkOut PIN 16; PIN 33 istype 'com' ; "Debug Clock input source. (IN) Clk2 PIN 14 istype 'reg, buffer'; "IClk divided by 2 (Out) " (Out for testing, may be node) IClk PIN 15; "****************************************************************************** "* Misc. "****************************************************************************** Run PR PIN 23 istype 'com'; PIN 12; ChinS~ EL "****************************************************************************** "* "* "* "* "* "* ### # # # # # # ## ## # # # # # ##### # # # # ###### # ##### # # ##### # # # # IM ##### # # " to be connected to IClk. (out) " Connected to Clkout externally (In) "external indication " active (L) when chips is In socket ## ## MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y * # # # # # # #### # #### # # * * * * * 75 Support Information "* ### # # # ###### # # # # # # ###### #### * "****************************************************************************** "****************************************************************************** "* Clock genrator Internals: "****************************************************************************** DbgClkDivBy2 DbgClkDivBy4 DbgClkDivBy8 NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; " counter (divider) signals. Cstr0 Cstr1 NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; " Clock Safe Transition Register "****************************************************************************** "* Reset active. (Active when at least one of the reset sources is active) * "****************************************************************************** PrimReset D_PrimReset DD_PrimReset NODE istype 'com'; NODE istype 'com'; NODE istype 'com'; Reset PdaRst NODE istype 'com'; NODE istype 'reg, buffer'; " MPC8XX continued / initiated. " part of the status register. "****************************************************************************** "* ADS_ACK, ADS_REQ auxiliary internal control signals * "****************************************************************************** S_HstReqNODE istype 'reg'; DS_HstReqNODE istype 'reg'; PR " delay timer. S_D_C~NODE istype 'reg, buffer'; " synchronized data/ control selection S_HstAckNODE istype 'reg, buffer'; " sync host ack DS_HstAckNODE istype 'reg, buffer'; " double sync host ack BundleDelay1, BundleDelay0NODE istype 'reg, buffer'; " delay compensation BndTmrExpNODE istype 'com';" terminal count for bundle "delay counter for bundle PDOe NODE istype 'com'; 76 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL "sync. host req. " double sync. host req. "Mach to ADI data OE. IM IN " delayed Reset " Primary Reset. Host initiated " double delayed primary reset. " Interface reset. AR Y MOTOROLA Support Information PdaHardResetEnNODE istype 'com'; PdaSoftResetEnNODE istype 'com'; " enables hard reset buffer. " enables soft reset buffer. "****************************************************************************** "* Tx Shift Register * "****************************************************************************** TxReg7, TxReg6, TxReg5, TxReg4, TxReg3, TxReg2, TxReg1, TxReg0NODE istype 'reg, buffer'; " Transmit latch and " shift register "****************************************************************************** "* Tx Control Logic IN "****************************************************************************** TxWordLen3, TxWordLen2, TxWordLen1, TxWordLen0NODE istype 'reg, buffer'; " Counter, counts (on fast clock, " to gain 1/2 clock resolution) " transmission length TxWordEndNODE istype 'com'; " Terminal count, sets transmission " length. TxEn NODE istype 'reg, buffer'; " Transmit Enable. TxClkSnsNODE istype 'reg, buffer'; " transmit clock polarity "****************************************************************************** "* Rx Shift Register * "****************************************************************************** RxReg0NODE istype 'reg, buffer'; " receive shift register " and latch "****************************************************************************** "* Rx Control Logic * "****************************************************************************** DsdiEnNODE istype 'reg'; " enables dsdi towards "****************************************************************************** MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM AR Y * 77 Support Information "* ADI control & status register bits. * "****************************************************************************** StatusRequest~ DebugEntry~ DiagLoopBack~ DbgClkDivSel0 DbgClkDivSel1 InDebugMode TxError NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; NODE istype 'reg, buffer'; " DbgClk division select " sync. VFLSs, became pin " tx interrupted by MPC8XX " internal reset. "Status request "Debug enable after reset (L) "diagnostic loopback mode (L) "****************************************************************************** "* ##### * # # # #### # #### # # # ##### # # # # # ## # # # # # ## ## # # # # # # ##### # # # # # * * * * * * * * ###### # ##### #### # # # # # # ## # # # # ##### # # # # ##### * * * "* # "* # "* # "* # "* # "* "* PR # #### # # # # # # # # # # ## ## # # # ##### #### # # # EL ## ## # ###### # # # # ## ## # #### "* ###### "* # "* # "* # 78 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM MOTOROLA IN AR Y Support Information "* # "* # # # # # ###### # # # # # ###### ###### # # # # ##### # # # # * * * * ## # # # # ##### # # # # # # # # # # # #### # # # # # # # # # ## ## # # # # # # * * * * * "* ###### "* "* "* "* "* "* "* #### ###### # # # # ## ## # #### "****************************************************************************** H, L, X, Z = 1, 0, .X., .Z.; C, D, U = .C., .D., .U.; "****************************************************************************** "* Since all state machines operate at interface clock (IClk) there is no "* need to have DbgClk driven during simulation (it will double the number "* of vectors required). Therefore, an alternative clock generator was built "* with which the 1/2 clock is the 1'st in the chain. "* If not the original clock generator design is compiled, however simulation "* will not pass then. "****************************************************************************** "* SIMULATION = 1; "****************************************************************************** "****************************************************************************** "* Signal groups "****************************************************************************** AdsSel = [AdsSel2,AdsSel1,AdsSel0]; = [!AdsAddr2,!AdsAddr1,!AdsAddr0]; AdsAddr AdsRst Rst ClkOut DbgClkDiv DbgClkDivSel Cstr PD VFLS MOTOROLA PR = [AdsHardReset, AdsSoftReset]; = [PdaHardReset~, PdaSoftReset~]; = [Clk2]; = [DbgClkDivBy8, DbgClkDivBy4, DbgClkDivBy2]; = [DbgClkDivSel1, DbgClkDivSel0]; = [Cstr1, Cstr0]; = [PD7,PD6,PD5,PD4,PD3,PD2,PD1,PD0]; = [VFLS0, VFLS1]; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* This alternative clock is compiled in if the SIMULATION variable is defined. IN AR Y * 79 Support Information VflsP BndDly = [VflsP0,VflsP1]; = [BundleDelay1, BundleDelay0]; "compensation timer TxReg RxReg AdiCtrlReg = [TxReg7..TxReg0]; = [TxReg6,TxReg5,TxReg4,TxReg3,TxReg2,TxReg1,TxReg0,RxReg0]; = [DbgClkDivSel1, DbgClkDivSel0, StatusRequest~, DiagLoopBack~,DebugEntry~]; AdiStatReg = [PdaRst, TxError, InDebugMode, DbgClkDivSel1, DbgClkDivSel0, "bundle delay StatusRequest~, DiagLoopBack~, DebugEntry~]; TxWordLen PortEn = [TxWordLen3, TxWordLen2, TxWordLen1, TxWordLen0]; = [AdsSel2,AdsSel1,AdsSel0,!AdsAddr2,!AdsAddr1,!AdsAddr0, "****************************************************************************** "* Select Logic definitions "****************************************************************************** HOST_VCC_ACTIVE = 1; HOST_EN~_ACTIVE = 0; HOST_IS_ON = ((HstEn~==HOST_EN~_ACTIVE) & (HostVcc==HOST_VCC_ACTIVE)); BOARD_IS_SELECTED = 0; ADS_IS_SELECTED = (AdsSelect~.fb==BOARD_IS_SELECTED) ; "Data_Cntrl~ line levels. DATA = 1; CONTROL = !DATA; "****************************************************************************** "* Reset Logic definitions "****************************************************************************** ADS_HARD_RESET_ACTIVE ADS_SOFT_RESET_ACTIVE = 1; = 1; "****************************************************************************** "* Clock Logic definitions "****************************************************************************** SELECT_CHANGE_ALLOWED = (DbgClkDiv.fb == 0); DEBUG_CLOCK_DIV_BY_1 = (Cstr.fb == 0); DEBUG_CLOCK_DIV_BY_2 = (Cstr.fb == 1); DEBUG_CLOCK_DIV_BY_4 = (Cstr.fb == 2); 80 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM HOST_IS_OFF = !HOST_IS_ON; IN AR Y HostVcc,HstEn~]; MOTOROLA Support Information DEBUG_CLOCK_DIV_BY_8 = (Cstr.fb == 3); "****************************************************************************** "* AdsAck Logic definitions "****************************************************************************** BUNDLE_DELAY = 2; HOST_REQ_ACTIVE ADS_ACK_ACTIVE = 1; = 1; "The other state is - HOST_ACK_ACTIVE = 1; HOST_WRITE_ADI = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstReq.fb ==HOST_REQ_ACTIVE) & (AdsAck==!ADS_ACK_ACTIVE) & (HstAck==!HOST_ACK_ACTIVE) ); HOST_WRITE_ADI_CONTROL = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstReq.fb ==HOST_REQ_ACTIVE) & HOST_WRITE_ADI_DATA PR = 1; HOST_WRITE_COMPLETE "****************************************************************************** "* Control & Status register definitions "****************************************************************************** STATUS_REQUEST= 0; DEBUG_ENTRY= 0; DIAG_LOOP_BACK= 0; IN_DEBUG_MODE MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstReq.fb==HOST_REQ_ACTIVE) & (AdsAck==!ADS_ACK_ACTIVE) & (D_C~==DATA) & (S_D_C~.fb ==DATA) & (HstAck==!HOST_ACK_ACTIVE) ); = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstReq.fb==!HOST_REQ_ACTIVE) & (AdsAck==!ADS_ACK_ACTIVE) ); IM (AdsAck==!ADS_ACK_ACTIVE) & (D_C~==CONTROL) & (S_D_C~.fb == CONTROL) & (HstAck==!HOST_ACK_ACTIVE) ); IN AR Y !ADS_ACK_ACTIVE 81 Support Information TX_DONE_OK= 0; TX_INTERRUPTED = !TX_DONE_OK; FRZ_SELECTED = 0; IS_STATUS_REQUEST = (StatusRequest~.fb == STATUS_REQUEST); DEBUG_MODE_ENTRY = (DebugEntry~.fb == DEBUG_ENTRY); IN_DIAG_LOOP_BACK = (DiagLoopBack~.fb == DIAG_LOOP_BACK); IS_IN_DEBUG_MODE FRZ_IS_SELECTED = (InDebugMode.fb == IN_DEBUG_MODE); = (VflsFrz~ == FRZ_SELECTED); "****************************************************************************** "* DSDI_ENABLE Logic definitions "****************************************************************************** DSDI_ENABLED = 1; DSDI_DISABLED = 0; STATE_DSDI_ENABLED = (DsdiEn.fb == DSDI_ENABLED); "****************************************************************************** "* Tx enable state machine "****************************************************************************** TX_ENABLED = 1; TX_DISABLED = 0; STATE_TX_ENABLED = (TxEn.fb == TX_ENABLED); STATE_TX_DISABLED = (TxEn.fb == TX_DISABLED); TX_WORD_LENGTH "****************************************************************************** "* TxClkSns state machine "****************************************************************************** TX_ON_RISING = 0; TX_ON_FALLING = 1; STATE_TX_ON_RISING = (TxClkSns.fb == TX_ON_RISING); STATE_TX_ON_FALLING = (TxClkSns.fb == TX_ON_FALLING); "****************************************************************************** "* AdsReq machine definitions. 82 PR = 14; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL " In 1/2 IClk clocks IM IN MOTOROLA AR Y Support Information "****************************************************************************** ADS_REQ_ACTIVE = 1; "The other state is !ADS_REQ_ACTIVE HOST_READ_ADI = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstAck.fb==HOST_ACK_ACTIVE) & (AdsReq==ADS_REQ_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) ); HOST_READ_ADI_DATA = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstAck.fb==HOST_ACK_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) & (AdsReq==ADS_REQ_ACTIVE) & (D_C~==DATA) ); HOST_READ_ADI_CONTROL = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstAck.fb==HOST_ACK_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) & (AdsReq==ADS_REQ_ACTIVE) & (D_C~==CONTROL) ); "****************************************************************************** "* ADI Data Bus definitions "****************************************************************************** DATA_BUFFERS_ENABLE PR STATUS_WORD_ON_ADI_BUS READ_DATA_WORD_ON_ADI_BUS "****************************************************************************** "* Vfls / Frz select definitions MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (HstAck==HOST_ACK_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) ); = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (HstAck==HOST_ACK_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) & (D_C~==CONTROL) ); = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (HstAck==HOST_ACK_ACTIVE) & (HstReq==!HOST_REQ_ACTIVE) & (D_C~== DATA) ); IM ADS_SEND_STATUS = ( (AdsSelect~.fb==BOARD_IS_SELECTED) & (DS_HstReq.fb == !HOST_REQ_ACTIVE) & (D_C~==CONTROL) & (AdsAck==ADS_ACK_ACTIVE) & IS_STATUS_REQUEST ); IN AR Y 83 Support Information "****************************************************************************** CHIP_IN_SOCKET = 0; CHIP_IS_IN_SOCKET = (ChinS~ == CHIP_IN_SOCKET); "****************************************************************************** "* Equations, state diagrams. * "****************************************************************************** "* "* ####### "* # "* # "* ##### "* # "* # "* ####### "* #### # # # # # # ## # # # # # # # # # # # ## # # # # ##### # # # # # # # # # # # #### # # # # # # # # # ## # # # #### # * * * * * * * * * ###### # # # # ### # #### "****************************************************************************** "****************************************************************************** "* ADS selection indicator. At low state, when host accesses the ADS. IM "* AdsSelect. IN "****************************************************************************** equations !AdsSelect~ = HOST_IS_ON & (AdsSel==AdsAddr); EL "AdsAddr is already inverted "****************************************************************************** "* Internal Logic Reset. "****************************************************************************** equations PR PrimReset = HOST_IS_OFF # "internal logic reset ( (AdsHardReset == ADS_HARD_RESET_ACTIVE) & (AdsSoftReset ==ADS_SOFT_RESET_ACTIVE) & ADS_IS_SELECTED ); D_PrimReset = PrimReset.fb; DD_PrimReset = D_PrimReset.fb; Reset = PrimReset.fb & D_PrimReset.fb & DD_PrimReset.fb;" spike filter "****************************************************************************** 84 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y ## # # # #### ## ## # # # # #### #### * * MOTOROLA Support Information "* Reset MPC8XX. (Connected to MPC8XX hard and reset inputs) Asynchronous. * "****************************************************************************** equations !PdaHardReset~ = H; PdaHardReset~.oe = PdaHardResetEn; "open-drain PdaHardResetEn = ADS_IS_SELECTED & (AdsHardReset==ADS_HARD_RESET_ACTIVE); !PdaSoftReset~ = H; PdaSoftReset~.oe = PdaSoftResetEn; "needs to be open-drain PdaSoftResetEn = ADS_IS_SELECTED & (AdsSoftReset==ADS_SOFT_RESET_ACTIVE ); "****************************************************************************** "****************************************************************************** "* Clock generator. "* All i/f logic works on IClk, which is driven externally by the output "* of DbgClk divider. "* control a 4:1 mux, output of which drives IClk (externally). "* Since mux control may change on the fly, a protection logic by means of "* 2 bit register is provided, so that mux control is allowed to change "* only when all divider outputs are high which assures a falling edge prior "* to a rising edge. "* Clk2 is infact the source for DSCK and is available outside for debug "* purpose. "****************************************************************************** equations DbgClkDiv.clk = DbgClk; DbgClkDiv := DbgClkDiv.fb + 1; " free running counter. "****************************************************************************** "* Clock Safe Transition Register. (CSTR) "* The goal of this register is to provide safe clock transitions, i.e., that "* a trasition will not cause races over the clockout. E.g., in a transition "* between divide by 1 and divide by any bigger order, a possible race may "* occur since the divided outputs are delayed with respect to DbgClk. "* Therefore, a safe transition may be performed only when all clocks are LOW. "****************************************************************************** MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* The debug clock divider is a 3 bit free-running counter, outputs of which IN AR Y 85 Support Information equations Cstr.clk = DbgClk; "* Cstr.ar = Reset; when (SELECT_CHANGE_ALLOWED) then Cstr := DbgClkDivSel.fb; else Cstr := Cstr.fb; "****************************************************************************** "* Clock selector. "* Controlled by the CSTR. "****************************************************************************** equations DbgClkOut.oe = 1; when (DEBUG_CLOCK_DIV_BY_1) then DbgClkOut = DbgClk; else when (DEBUG_CLOCK_DIV_BY_2) then DbgClkOut = DbgClkDivBy2.fb; else when (DEBUG_CLOCK_DIV_BY_4) then DbgClkOut = DbgClkDivBy4.fb; else when (DEBUG_CLOCK_DIV_BY_8) then DbgClkOut = DbgClkDivBy8.fb; "****************************************************************************** "* Clk2. "* IClk divided by 2 . "****************************************************************************** equations Clk2.clk = IClk; ClkOut.oe = 3; ClkOut.ar = Reset; PR expired. Clk2 := !Clk2 & HOST_IS_ON; EL "divide by 2 "****************************************************************************** "* Bundle delay timer. This timer ensures data validity in the following casses: "* 1) Host write to adi. In that case AdsAck is ASSERTED only after that timer "* 86 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM MOTOROLA IN AR Y Support Information "* 2) Host read from adi. In that case AdsReq is NEGATED after that timer "* expired, ensuring enough time for data propgation over the bundle. "* The timer is async reset when both soft and hard reset is applied to the i/f. "* The timer is sync. reset a clock after it expires. "* Count starts when either HstReq or HstAck are detected asserted "* (after proper synchronization) "* The value upon which the terminal count is assereted, is in the control "* register. When the interface is reset by the host, this value defaults "* to its upper bound. Using the diagnostic loop-back mode this value "* may be re-established for optimal performance. (by means of test & error) "****************************************************************************** equations BndDly.ar = Reset; BndDly.clk = IClk; when ( ( (HOST_WRITE_ADI_CONTROL # HOST_READ_ADI_CONTROL ) # (HOST_WRITE_ADI_DATA # HOST_READ_ADI_DATA) & !PdaRst.fb) BndDly := BndDly.fb +1; else BndDly := 0; BndTmrExp = (BndDly.fb == BUNDLE_DELAY) & !AdsAck ; "delay field "active low. "****************************************************************************** "* AdsAck. "* Host write to ads ack. This state machine generates an automatic ADS_ACK, "* during a host to ADS write. "* When the host access the ADS data / control register, an automatic "* acknowledge is generated, after data has been latched into either the "* tx shift register or the control register. "* Acknowledge is released when the host removes its write control line. "* "* "* The machine steps through these states : "* 0 - !ADS_ACK_ACTIVE "* 1 - ADS_ACK_ACTIVE "****************************************************************************** equations AdsAck.clk = IClk; (HstReq) MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM & !BndTmrExp.fb) then IN AR Y 87 Support Information AdsAck.ar AdsAck.oe = Reset; = ADS_IS_SELECTED; S_HstReq.clk = IClk; DS_HstReq.clk = IClk; S_HstReq := HstReq; DS_HstReq := S_HstReq.fb & HstReq;"double synced S_D_C~.clk = IClk;" synchronizing D_C~ selector S_D_C~ := D_C~; state_diagram AdsAck state !ADS_ACK_ACTIVE: if ( (HOST_WRITE_ADI_CONTROL # (HOST_WRITE_ADI_DATA & !PdaRst.fb) ) ADS_ACK_ACTIVE else !ADS_ACK_ACTIVE; & BndTmrExp.fb) then state ADS_ACK_ACTIVE: !ADS_ACK_ACTIVE else ADS_ACK_ACTIVE; "****************************************************************************** "* Transmit Enable logic. "* Enables transmit of serial data over DSDI and generation of serial "* clock over DSCK. "* Transmission begins immediately after data written by the host is latched "* into the transmit shift register and ends after 7 shifts were made to the "* tx shift register. "* Termination is done using a 4 bit counter TxWordLength which has a terminal "* count (and reset) TxWordEnd. "****************************************************************************** equations state_diagram TxEn state TX_DISABLED: if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then TX_ENABLED 88 PR TxEn.ar = Reset; TxEn.clk = IClk;" to provide 1/2 clock resolution MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM if ( DS_HstReq.fb==!HOST_REQ_ACTIVE ) then IN MOTOROLA AR Y Support Information else TX_DISABLED; state TX_ENABLED: if(TxWordEnd # PdaRst.fb) then TX_DISABLED else TX_ENABLED; "****************************************************************************** "* Transmit Length Counter. This counter determines the length of transmission "* towards the MPC. The fast clock is used here to allow 1/2 clock resolution "* with the negation of TxEn, which enables DSCK outside. "****************************************************************************** equations TxWordLen.ar = Reset; TxWordLen.clk = IClk; TxWordEnd = (TxWordLen.fb == TX_WORD_LENGTH); when ( STATE_TX_ENABLED & !TxWordEnd & !PdaRst.fb) then else TxWordLen.d = 0; "****************************************************************************** "* TxClkSns - Transmit Clock Sense. "* Since Host req is synced acc to IClk and may be detected active when Clk2 is "* either '1' or '0', DSCK and the clock according to which DSDI is sent and "* DSDO is sampled should be changed. "* When TxClkSns is '0' - DSCK will be !Clk2 while transmit will be done "* according to Clk2 and recieve by !Clk2. "* When TxClkSns is '1' - DSCK will be Clk2 while transmit will be done "* according to !Clk2~ and recieve by Clk2. "****************************************************************************** equations state_diagram TxClkSns state TX_ON_RISING: if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & Clk2) then MOTOROLA PR TxClkSns.clk = IClk; TxClkSns.ar = Reset; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM TxWordLen.d = TxWordLen.fb + 1; IN 89 AR Y Support Information TX_ON_FALLING else TX_ON_RISING; state TX_ON_FALLING: if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & !Clk2) then TX_ON_RISING else TX_ON_FALLING; "****************************************************************************** "* Tx shift Register. "* 8 bits shift register which either shifts data out (MSB first) or holds "* its data. The edge (in Clk2 terms) upon which the above actions are taken, "* is determined by TxClkSns. The Tx shift register operates according to IClk. "* The Tx shift register is 1'st written by the host (data cycle) and along "* with write being acknowledged to the host data is shifted out via DSDI. "* "* In order of saving logic, the Tx shift register is shared with the Receive "* shift register, this, due to the fact that when a bit is shifted out a FF "* becomes available. Since the Tx shift register is shifted MSB first, its "* To provide a 1/2 DSCK hold time for DSDI, a single FF receive SR is used "* which is the source for the Tx shift register. (if 0 hold is required "* for DSDI this FF may be ommited) "****************************************************************************** equations TxReg.clk = IClk; TxReg.ar = Reset; PR else when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then [TxReg7..TxReg1] := [PD7..PD1].pin; " latching ADI data else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 # STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then [TxReg7..TxReg1] := [TxReg6..TxReg0].fb; " shifting out MSB 1'st. [TxReg7..TxReg1] := [TxReg7..TxReg1].fb; EL IM "* LSB FFs are grdualy becoming available for received data. when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then TxReg0 := PD0.pin; else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 # STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then 90 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN " Holding value. AR Y MOTOROLA Support Information TxReg0 := RxReg0.fb; else TxReg0 := TxReg0.fb; "****************************************************************************** "* Receive Shift Register. "* A single stage shift register used as a source for the Tx shift register. "* In normal mode the input for the Rx shift register is the MPC8XX's DSDO, while "* in diagnostic loopback mode, data is taken directly from the Tx shift "* serial output. "* "* The output of the Rx shift register is fed to the input of the Tx shift "* register. When transmission (and reception) is done the received data "* word is compossed of the Rx shift register (LSB) concatenated with the "* 7 LSBs of the Tx shift register. "* "* The edge (in Clk2 terms) upon which data is shifted in is determined by "* data is shifted Out from the Tx shift register on the Falling edge of "* DSCK while is shifted In to the Rx shift register on the Rising edge "* DSCK. (DSCK terms are constant in that regard). "****************************************************************************** equations RxReg0.clk = IClk; RxReg0.ar = Reset; PR RxReg0.d = DSDO; else "* AdsReq. when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 # STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & (!IN_DIAG_LOOP_BACK) then "shift in ext data else when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 # STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & IN_DIAG_LOOP_BACK then RxReg0.d = TxReg7.fb;" shift in from transmit reg RxReg0.d = RxReg0.fb;" hold value "****************************************************************************** "* Host from ads, read acknowledge. This state machine generates an automatic "* ADS read request from the host when either a byte of data is received in the MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* TxClkSns as with the Tx shift register but on opposite edges, i.e., IN AR Y 91 Support Information "* Rx shift register or the status request bit in the control register is "* active during a previous host write to the control register. "* When the host detectes AdsReq asserted, it assertes HstAck in return. HstAck "* double synchronized from the ADI port and delayed using the bundle delay "* compensation timer to negate AdsReq. When the host detects AdsReq negated "* it knows that data is valid to be read. After the host reads the data it "* negates HstAck. "* The machine steps through these states : "* 0 - !ADS_REQ_ACTIVE "* 1 - ADS_REQ_ACTIVE "****************************************************************************** equations AdsReq.clk AdsReq.ar AdsReq.oe = IClk; = Reset; = ADS_IS_SELECTED; S_HstAck.clk = IClk; DS_HstAck.clk = IClk; DS_HstAck := HstAck & S_HstAck;"double synced state_diagram AdsReq state !ADS_REQ_ACTIVE: if ( TxEn.fb & TxWordEnd ADS_SEND_STATUS) then" end of control write and status required ADS_REQ_ACTIVE else "****************************************************************************** "* ADI control register. "* The ADI control register is written upon host to ADI write with a "* D_C~ line is in control mode. It also may be read when StatusRequest~ bit "* is active. "* 92 PR else !ADS_REQ_ACTIVE; state ADS_REQ_ACTIVE: if ( HOST_READ_ADI & BndTmrExp.fb ) then !ADS_REQ_ACTIVE ADS_REQ_ACTIVE; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM S_HstAck := HstAck; #" end of data shift to MPC8XX IN MOTOROLA AR Y Support Information "* Control register bits description: "* "* DebugEntry~: (Bit 0). When this bit is active (L), the MPC8XX will enter debug "* "* "* "* mode immediately after reset, i.e., DSCK will be held high after the rising edge of SRESET*. When negated, DSCK will be held low after the rising edge of SRESET so the MPC8XX will start running instantly. "* DiagLoopBack~: (Bit 1). When active (L), the interface is in Diagnostic "* "* "* "* "* "* Loopback mode. I.e., the source for the Rx shift register is the output of the Tx shift register. During that mode, DSCK and DSDI are tri-stated, so no arbitrary data is sent to the debug port. When inactive, the interface is in normal mode, i.e., DSCK and DSDI are driven and the source of the Rx shift register is DSDO. "* StatusRequest~: (Bit 2). When active (L) any write to the control register "* "* "* "* will be followed by a status read cycle initiated by the debug port controller, i.e., AdsReq will be asserted after the write cycle ends. When inactive, a write to the control register will not be followed by a read from status register. "* "* "* "* "* "* 0 - by 1 1 - by 2 2 - by 4 3 - by 8 DbgClk input. Division factors are set as follows: "* Important!!! All bits wake up active (L) after reset. "* "****************************************************************************** equations "****************************************************************************** "* ADI Data Bus. "* The Adi data bus is driven towards the host when the host reads the i/f. MOTOROLA PR else AdiCtrlReg.clk = IClk; AdiCtrlReg.ar = Reset;"All active low. when ( HOST_WRITE_ADI_CONTROL & BndTmrExp.fb) then AdiCtrlReg.d = [PD4.pin, PD3.pin, PD2.pin, PD1.pin, PD0.pin]; AdiCtrlReg.d = AdiCtrlReg.fb; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* DbgClkDivSel(1:0) : (Bits 4,3). This field selects the division of the IN AR Y 93 Support Information "* When D_C~ line is high (data) the Rx shift register contents is driven. If "* D_C~ is low (control) the status register contents is driven. "* The status register contains all control register's bits (4:0) with the "* addition of the following: "* "* InDebugMode: (Bit 5). When this bit is active (H), the mpc is in debug mode, "* i.e., either Freeze or VFLS(0:1) lines are driven high. "* "* When mpc is not in socket, VflsP(0:1) coming from the debug port are selected. "* TxError: (Bit 6). When this bit is active (H), it signals that the MPC8XX was "* reset (internally) during data transmission. (i.e., data received "* during that trnasmission is corrupted). This bit is reset (L) when "* either happens: (1) - The interface is reset by the host (both "*AdsHardReset and AdsSoftReset are asserted (H) by the host "* while the board is selected). (2) - The host writes the interface with "* D_C~ signal low (control) and with data bit 6 high. (3) - a new data "* word is written to the Tx shift register. (I.e., error is not kept "*indefinitely). "* PdaRst: (Bit 7). When this bit is active (H), it means that either SRESET* "* this bit negates so that data may be wrriten to the debug port. "****************************************************************************** equations PDOe = DATA_BUFFERS_ENABLE ; PD.oe = PDOe; PR PD = RxReg.fb; "* Reset Status PdaRst.clk = IClk; when ( READ_DATA_WORD_ON_ADI_BUS) then elsewhen ( STATUS_WORD_ON_ADI_BUS ) then PD = [PdaRst.fb, TxError.fb, InDebugMode.fb, DbgClkDivSel1.fb, DbgClkDivSel0.fb, DiagLoopBack~.fb, DebugEntry~.fb ]; StatusRequest~.fb, "****************************************************************************** "****************************************************************************** PdaRst := (!PdaHardReset~ # !PdaSoftReset~) & (AdsSelect~.fb==BOARD_IS_SELECTED); " synchronized inside. "****************************************************************************** 94 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "*or HRESET* or both are driven by the MPC8XX. The host have to wait until IN AR Y MOTOROLA Support Information "* In debug Mode "****************************************************************************** InDebugMode.clk = IClk; when (FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then InDebugMode := Freeze; else when (!FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then InDebugMode := (VFLS0 & VFLS1); else when (!CHIP_IN_SOCKET) then InDebugMode := (VflsP0.pin & VflsP1.pin); "****************************************************************************** "* TxError. "* This bit of the status register is set ('1') when the MPC8XX internally resets "* during data transmission over the debug port. "* When this bit is writen '1' by the adi port (control) the status bit is "* cleared. Writing '0' has no influence on that bit. "****************************************************************************** equations TxError.clk = IClk; TxError.ar = Reset; state_diagram TxError state TX_DONE_OK: state TX_INTERRUPTED: if (HOST_WRITE_ADI_CONTROL & BndTmrExp.fb & PD6.pin # HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then TX_DONE_OK else TX_INTERRUPTED; "****************************************************************************** "* DSCK. "* MPC8XX debug port, gated serial clock. MOTOROLA PR TX_INTERRUPTED else TX_DONE_OK; if(STATE_TX_ENABLED & PdaRst.fb) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y 95 Support Information "****************************************************************************** equations DSCK.oe = ADS_IS_SELECTED; when ( ADS_IS_SELECTED & !PdaSoftReset~ ) then DSCK = H;"debug mode enable else when ( ADS_IS_SELECTED & !TxEn.fb & PdaSoftReset~ ) then DSCK = !DebugEntry~.fb;"debug mode direct entry else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_RISING) then DSCK = !Clk2;"debug port clock else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_FALLING) then DSCK = Clk2;"debug port inverted clock else when (!ADS_IS_SELECTED) then DSCK = H;"default value, infact X "****************************************************************************** "* DSDI. "* Debug Port Serial Data in. (from MPC8XX). "* To provide better hold time for DSDI from the last rising edge of DSCK, "****************************************************************************** equations DsdiEn.ar = Reset; DsdiEn.clk = IClk; state_diagram DsdiEn state DSDI_DISABLED: state DSDI_ENABLED: equations DSDI.oe = ADS_IS_SELECTED & !IN_DIAG_LOOP_BACK; "avoid junk driven on DSDI input "during diagnostic loop back mode. when (ADS_IS_SELECTED & !PdaSoftReset~) then DSDI = H; else when (ADS_IS_SELECTED & !STATE_DSDI_ENABLED & PdaSoftReset~ ) then 96 PR DSDI_ENABLED else DSDI_DISABLED; DSDI_DISABLED else DSDI_ENABLED; if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then if(STATE_TX_DISABLED # PdaRst.fb) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* a dedicated enable for DSDI is provided - DSDI_ENABLE. IN AR Y MOTOROLA Support Information DSDI = L; else when (ADS_IS_SELECTED & STATE_DSDI_ENABLED) then DSDI = TxReg7.fb; else DSDI = L; "****************************************************************************** "* Debug Port VFLS pins. "****************************************************************************** equations VflsP.oe = !ADS_IS_SELECTED; when (!FRZ_IS_SELECTED) then VflsP = [VFLS0,VFLS1]; else when (FRZ_IS_SELECTED) then VflsP = [Freeze,Freeze]; "* Run Led "****************************************************************************** Run.oe = H; !Run = IS_IN_DEBUG_MODE;"when 1 lits a led. end dbg_prt7 MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "****************************************************************************** IN AR Y 97 Support Information A*2 U11 - Board Control & Status Register "****************************************************************************** "* In this file (6): "* - Added board revision # at BCSR3: 0 ENG "* 1 - PILOT. "* - Flash Presence detect lines - added FlashPD(7:5). "* - Changed polarity of Power-On Reset (now active high) "* - DramEn becomes active-low to enhance debug-station support changes. "****************************************************************************** "* In this file (7): "* - Board revisiob code @ BCSR3 is changed to 2 - Rev A. "****************************************************************************** "* In this file (8): "* - Board revisiob code @ BCSR3 is changed to 3 - Rev B. "* - Added RS232En2~ for 2'nd RS232 port. "* In this file (9): "* - All status bits (except CntRegEnProtect~) are removed for external buffers. "* - Added address line A27 "* - Added BCSR2CS~ and BCSR3CS~ for external status registers. "* - Added controls on bcsr1: "* "* - SdramEn~ - PccVcc1~ "* - Added BCSR4 with following controls: "* "* "* "* "* "* "* "* - UsbUtpFethEn~ (bit 0) enables Usb or Utopia or Fast Ethernet ports - UsbSpeed (bit 1) Usb speed control ('1'- full speed) "****************************************************************************** "* In this file (10): "* - Added ethernet transceiver control signals to BCSR4: "* "* "* "* "* "* - ModemEne~ - Modem_Audio~ - EthLoop - TPFFLDL~ - TPSQEL~ (bit 8) sets the transceiver to internal loopback (H) (bit 9) sets the trans. to full-duplex mode. (L) (bit 10) allows for testing the colission ciruitry of the 68160. (bit 11) enables the modem tool with the MPC823FADSDB (bit 12) selects between modem / audio function for 98 PR - UsbVcc1 - UsbVcc0(bit 2) enables VCC for Usb channel (bit 3) reserved for possible 3.3V usb power - VideoOn~(bit 4) enables video transceiver - VideoExtClkEn (bit 5) enables ext 27Mhz clock for video encoder - VideoRst~(bit 6) resets the video encoder. - SignaLamp(bit 7) used for s/w signaling to user. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN "****************************************************************************** AR Y MOTOROLA Support Information "* modem tool with MPC823 daughter board. "****************************************************************************** module bcsr10 title 'MPC8XXFADS Board Control and Status Register' "****************************************************************************** "* Device declaration. * "****************************************************************************** U11 device 'mach220a'; "****************************************************************************** "* ####### "* # "* # "* ##### "* # "* # "* ####### # # * # # ##### # # # # # ###### # ##### # # ###### ##### # # # # # ## ## # # # # # # ## ## # # # # IN # # ## ## # ###### # # # # ##### # # # # "****************************************************************************** "****************************************************************************** "* Pins declaration. * "****************************************************************************** "* System i/f pins "****************************************************************************** SYSCLKPIN 15; RGPORInPIN ResetConf~PIN BrdContRegCs~PIN TA~ PIN R_W~ PIN 16; 50; A27 PIN A28 PIN A29 PIN D0 MOTOROLA PR 54; 45; 17; 20; 51; PIN 10; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL 49; IM AR Y ## # # # # # ###### # #### * * * * * * # # # #### # # #### 99 Support Information D1 D2 D3 D4 D5 D6 D7 D8 D9 PIN PIN PIN PIN PIN PIN PIN PIN PIN 11; 12; 13; 33; 14; 25; 24; 23; 22; 21; 29; 30; 31; 32; 9; D10 PIN D11 PIN D12 PIN D13 PIN D14 PIN D15 PIN "****************************************************************************** "* Board Control Pins. Read/Write. "****************************************************************************** DramEn~PIN EthEn~PIN 7 istype 'reg,buffer'; 6 istype 'reg,buffer'; InfRedEn~PIN 41 istype 'reg,buffer'; FlashCfgEn~PIN 37 istype 'reg,buffer'; CntRegEn~PIN 36 istype 'reg,buffer'; RS232En1~PIN 63 istype 'reg,buffer'; PccEn~PIN 40 istype 'reg,buffer'; EL PccVcc0PIN 65 istype 'reg,buffer'; PccVpp0PIN 59 istype 'reg,buffer'; PccVpp1PIN 66 istype 'reg,buffer'; HalfWord~PIN 58 istype 'reg,buffer'; RS232En2~PIN 64 istype 'reg,buffer'; SdramEn~PIN 56 istype 'reg,buffer'; PccVcc1PIN 57 istype 'reg,buffer'; PR EthLoop TPFLDL~ TPSQEL~ SignaLamp~PIN PIN 60 istype 'reg,buffer'; PIN 43 istype 'reg,buffer'; PIN 44 istype 'reg,buffer'; 4 istype 'reg,buffer'; UsbUtpFethEn~ PIN 67 istype 'reg,buffer'; UsbSpeedPIN 46 istype 'reg,buffer'; UsbVcc0PIN 3 istype 'reg,buffer'; 100 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM FlashEn~PIN 62 istype 'reg,buffer'; " flash enable. " dram enable " ethernet port enable " infra-red port enable " flash configuration enable " control register access enable " RS232 port 1 enable " PCMCIA port enable " PCMCIA operation voltage select 0 " PCMCIA programming voltage select " PCMCIA programming voltage select " 32/16 bit dram operation select " RS232 port 2 enable " sdram enable " PCMCIA operation voltage select 1 " status lamp for misc s/w visual signaling " Usb or Utopia or Fast ethernet port enable " Usb speed control " Usb VCC select 0 line IN " 68160 internal loop back " 68160 full-duplex " 68160 colission circuitry test. AR Y MOTOROLA Support Information UsbVcc1PIN 2 istype 'reg,buffer'; " Usb VCC select 1 line " Video encoder enable " Enable external clock gen for video encoder VideoOn~PIN 39 istype 'reg,buffer'; VideoExtClkEn PIN 38 istype 'reg,buffer'; VideoRst~PIN ModemEn~ Modem_Audio~ 5 istype 'reg,buffer'; " Video Encoder reset " modem tool enable for MPC823FADSDB " Modem / Audio functions select " for modem tool with MPC823 d/b. PIN 28 istype 'reg,buffer'; PIN 55 istype 'reg,buffer'; "****************************************************************************** "* Board Status Pins. Read only. "****************************************************************************** "* removed to external buffers "****************************************************************************** "* Board Status Registers Chip-Selects "****************************************************************************** Bcsr2Cs~PIN 47 istype 'com'; Bcsr3Cs~PIN 48 istype 'com'; "****************************************************************************** "* Auxiliary Pins. "****************************************************************************** "* "* "* "* "* "* "* ### # # # # # # ## ## # # # * # # # ##### # # # # # EL ###### # IM ##### # # # # # ## ## # # # ##### # # # # " Boot Disable "****************************************************************************** IN # # # ## # # # # ## ## # ###### # # # # ##### # # ## ## # PR ### ###### "****************************************************************************** "* System Hard Reset Configuration. "****************************************************************************** ERBNODE istype 'reg,buffer'; IP~NODE istype 'reg,buffer'; BDISNODE istype 'reg,buffer'; RSV2NODE istype 'reg,buffer'; BPS0, BPS1NODE istype 'reg,buffer'; RSV6NODE istype 'reg,buffer'; ISB0, " External Arbitration " Interrupt Prefix in MSR " reserved config bit 2 " Boot Port Size " reserved config bit 6 MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y # # # # # ###### # #### # #### # # * * * * * * #### 101 Support Information ISB1NODE istype 'reg,buffer'; DBGC0, DBGC1NODE istype 'reg,buffer'; DBPC0, DBPC1NODE istype 'reg,buffer'; RSV13 RSV14 RSV15 " Debug Port pins Config " reserved config bit 13 " reserved config bit 14 " reserved config bit 15 " Debug pins Config. " Internal Space Base NODE istype 'reg,buffer'; NODE istype 'reg,buffer'; NODE istype 'reg,buffer'; DataOeNODE istype 'com';" data bus output enable on read. "****************************************************************************** "* Control Register Enable Protection. "****************************************************************************** CntRegEnProtect~NODE istype 'reg,buffer'; "****************************************************************************** "* Control Register Write (space saving) Mach 10 required for 52Mhz Bcsr0Write~ NODE istype 'com'; Bcsr1Write~ NODE istype 'com'; Bcsr4Write~ NODE istype 'com'; "****************************************************************************** "* ##### # #### # # # # # # # # # # ## ## # # # # # # #### # #### # # # ##### # # # # # ## # # # # # ## ## # # # # # # ##### # # # # # * * * * * * * * "* # "* # "* # "* # "* # "* "* PR ## ## # ###### # # # # ## ## # ##### #### #### 102 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "****************************************************************************** IN AR Y MOTOROLA Support Information "* ###### "* # "* # "* # "* # "* # # # # # # ###### # ##### # # ###### #### # # # # # # # # # # # ###### ## # # # # ##### # # # # ##### * * * * * * * * ## # # # # ##### # # # # # # # # # # # #### # # # # # # # # # ## ## # # # # # # * ###### # # # # ##### # # # # "* ###### "* "* "* "* "* "* "* #### ###### # # # # ## ## # #### "****************************************************************************** H, L, X, Z = 1, 0, .X., .Z.; C, D, U = .C., .D., .U.; "****************************************************************************** "* SIMULATION = 1; "* SLOW_PLL_LOCK = 1; "* DRAM_8_BIT_OPERATION = 1; "****************************************************************************** "* Signal groups "****************************************************************************** Add = [A27,A29]; Data = [D0..D15]; ConfigReg = [ERB,IP~,RSV2,BDIS, BPS0,BPS1,RSV6,ISB0, ISB1,DBGC0,DBGC1,DBPC0, BPS = [BPS0,BPS1];" boot port size ISB = [ISB0,ISB1];" Initial Internal Space Base DBGC = [DBGC0,DBGC1];" Debug Pins Configuration DBPC = [DBPC0,DBPC1];" Debug port location ContReg = [FlashEn~, DramEn~,EthEn~,InfRedEn~,FlashCfgEn~, CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~, PccVcc0,PccVpp0,PccVpp1,HalfWord~, RS232En2~,SdramEn~,PccVcc1,EthLoop, MOTOROLA PR DBPC1,RSV13,RSV14,RSV15]; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y * * * * * 103 Support Information TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~, UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~, VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~]; ReadBcsr1 = [FlashEn~,DramEn~,EthEn~,InfRedEn~, FlashCfgEn~,CntRegEnProtect~.fb,CntRegEn~,RS232En1~, PccEn~,PccVcc0,PccVpp0,PccVpp1, HalfWord~,RS232En2~,SdramEn~,PccVcc1]; ReadBcsr4 = [EthLoop, TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~, UsbSpeed,UsbVcc0, UsbVcc1 ,VideoOn~, VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~]; DrivenContReg = [FlashEn~,DramEn~,EthEn~,InfRedEn~, FlashCfgEn~,CntRegEn~,RS232En1~,PccEn~, PccVcc0,PccVpp0,PccVpp1,HalfWord~, RS232En2~,SdramEn~,PccVcc1,EthLoop, TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~, VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~]; PccVcc = [PccVcc0,PccVcc1]; PccVpp = [PccVpp0,PccVpp1]; WideContReg = [FlashEn~, DramEn~,EthEn~,InfRedEn~,FlashCfgEn~, Bcsr2_3Cs~ = [Bcsr2Cs~,Bcsr3Cs~]; "****************************************************************************** "* Power On Reset definitions "****************************************************************************** FLASH_CFG_ENABLE = 0; K_A_PON_RESET_ACTIVE = 1; 104 PR CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~, PccVcc0,PccVpp0,PccVpp1,HalfWord~, RS232En2~,SdramEn~,PccVcc1,EthLoop, TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~, UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~, VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~]; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~, IN MOTOROLA AR Y Support Information RESET_CONFIG_ACTIVE = 0; "**** changed due to long lock delay of the pda *** 17,7,95 ****************** @ifndef SLOW_PLL_LOCK { KA_PON_RESET = (RGPORIn == K_A_PON_RESET_ACTIVE); } @ifdef SLOW_PLL_LOCK { PON_DEFAULT_ACTIVE = 0; KA_PON_RESET = (PonDefault~ == PON_DEFAULT_ACTIVE); } "*********** end of change *************** RESET_CONFIG_DRIVEN = ((ResetConf~ == RESET_CONFIG_ACTIVE) & "****************************************************************************** "* Register Access definitions "****************************************************************************** CONFIG_REG_ADD = 0; CONTROL_REG_1_ADD = 1; STATUS_REG2_ADD = 2; STATUS_REG3_ADD = 3; CONTROL_REG_4_ADD = 4; " MPC_WRITE_BCSR_0 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); " MPC_WRITE_BCSR_1 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~); MPC_WRITE_BCSR_3 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & A28 & A29 & !CntRegEn~); "MPC_WRITE_BCSR_4 = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~); BCSR_WRITE_ACTIVE = 0; MPC_WRITE_BCSR_0 = (Bcsr0Write~.fb == BCSR_WRITE_ACTIVE); MPC_WRITE_BCSR_1 = (Bcsr1Write~.fb == BCSR_WRITE_ACTIVE); MPC_WRITE_BCSR_4 = (Bcsr4Write~.fb == BCSR_WRITE_ACTIVE); MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (FlashCfgEn~ != FLASH_CFG_ENABLE)); IN AR Y 105 Support Information MPC_READ = (!BrdContRegCs~ & R_W~ & !CntRegEn~); MPC_READ_BCSR_0 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); MPC_READ_BCSR_1 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & A29 & !CntRegEn~); MPC_READ_BCSR_2 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & !A29 & !CntRegEn~); MPC_READ_BCSR_3 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & A29 & !CntRegEn~); MPC_READ_BCSR_4 = (!BrdContRegCs~ & R_W~ & A27 & !A28 & !A29 & !CntRegEn~); "****************************************************************************** "****************************************************************************** "* BCSR 0 definitions "****************************************************************************** "****************************************************************************** INTERNAL_ARBITRATION = 0; EXTERNAL_ARBITRATION = !INTERNAL_ARBITRATION; IP_AT_0xFFF00000 = 0;"active low IP_AT_0x00000000 = !IP_AT_0xFFF00000; RSV2_ACTIVE = 1; BOOT_DISABLE = 1; BOOT_ENABLE = !BOOT_DISABLE; BOOT_PORT_32 = 0; BOOT_PORT_8 = 1; BOOT_PORT_16 = 2; BOOT_PORT_RESERVED = 3; RSV6_ACTIVE = 1; INT_SPACE_BASE_0x00000000 = 0; INT_SPACE_BASE_0x00F00000 = 1; INT_SPACE_BASE_0xFF000000 = 2; INT_SPACE_BASE_0xFFF00000 = 3; DEBUG_PINS_PCMCIA_2 = 0; DEBUG_PINS_WATCH_POINTS = 1; DEBUG_PINS_RESREVED = 2; DEBUG_PINS_FOR_SHOW = 3; 106 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Support Information DEBUG_PORT_ON_JTAG = 0; DEBUG_PORT_NON_EXISTANT = 1; DEBUG_PORT_RESERVED = 2; DEBUG_PORT_ON_DEBUG_PINS = 3; RSV13_ACTIVE = 1; RSV14_ACTIVE = 1; RSV15_ACTIVE = 1; "*********************************************** "******* Power On Defaults Assignments ********* "*********************************************** ERB_PON_DEFAULT = INTERNAL_ARBITRATION; IP~_PON_DEFAULT = IP_AT_0x00000000; RSV2_PON_DEFAULT = !RSV2_ACTIVE; BDIS_PON_DEFAULT = BOOT_ENABLE; BPS_PON_DEFAULT = BOOT_PORT_32; RSV6_PON_DEFAULT = !RSV6_ACTIVE; ISB_PON_DEFAULT = INT_SPACE_BASE_0xFF000000; DBGC_PON_DEFAULT = DEBUG_PINS_PCMCIA_2; DBPC_PON_DEFAULT = DEBUG_PORT_ON_JTAG; RSV13_PON_DEFAULT = !RSV13_ACTIVE; RSV14_PON_DEFAULT = !RSV14_ACTIVE; RSV15_PON_DEFAULT = !RSV15_ACTIVE; "******************************************* "******* Data Bits Assignments ************* "******************************************* ERB_DATA_BIT = [D0]; IP~_DATA_BIT = [D1]; RSV2_DATA_BIT = [D2]; BDIS_DATA_BIT = [D3]; BPS_DATA_BIT = [D4,D5]; RSV6_DATA_BIT = [D6]; ISB_DATA_BIT = [D7,D8]; DBGC_DATA_BIT = [D9,D10]; DBPC_DATA_BIT = [D11,D12]; RSV13_DATA_BIT = [D13]; RSV14_DATA_BIT = [D14]; RSV15_DATA_BIT = [D15]; "****************************************************************************** MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 107 AR Y Support Information "****************************************************************************** "* BCSR 1 definitions. "****************************************************************************** "****************************************************************************** HALF_WORD = 0; ETH_ENABLED = 0; DRAM_ENABLED = 0; CONT_REG_ENABLE = 0; RS232_1_ENABLE = 0; RS232_2_ENABLE = 0; PCC_ENABLE = 0; PCC_VCC_CONT_0 = 0; PCC_VCC_CONT_1 = 1; PCC_VPP0 = 1; PCC_VPP1 = 1; FLASH_ENABLED = 0; INF_RED_ENABLE = 0; "* FLASH_CFG_ENABLE = 0; DRAM_5V = 0; DRAM_3V = !DRAM_5V; needed to be defined ealier CNT_REG_EN_PROTECT = 0; " inadvertant write protect SDRAM_ENABLED = 1; "*********************************************** "******* Power On Defaults Assignments ********* "*********************************************** FLASH_ENABLE_PON_DEFAULT = FLASH_ENABLED; FLASH_CFG_ENABLE_PON_DEFAULT = !FLASH_CFG_ENABLE; DRAM_ENABLE_PON_DEFAULT = DRAM_ENABLED; ETH_ENABLE_PON_DEFAULT = !ETH_ENABLED; CONT_REG_ENABLE_PON_DEFAULT = CONT_REG_ENABLE; RS232_1_ENABLE_PON_DEFAULT = !RS232_1_ENABLE; RS232_2_ENABLE_PON_DEFAULT = !RS232_2_ENABLE; PCC_ENABLE_PON_DEFAULT = !PCC_ENABLE; PCC_VCC_0_PON_DEFAULT = PCC_VCC_CONT_0; PCC_VCC_1_PON_DEFAULT = PCC_VCC_CONT_0; PCC_VPP0_PON_DEFAULT = PCC_VPP0; PCC_VPP1_PON_DEFAULT = PCC_VPP1; " T.S. as default INF_RED_ENABLE_PON_DEFAULT = !INF_RED_ENABLE; HALF_WORD_PON_DEFAULT = !HALF_WORD; SDRAM_ENABLE_PON_DEFAULT = SDRAM_ENABLED; CNT_REG_EN_PROTECT_PON_DEFAULT = CNT_REG_EN_PROTECT; "******************************************* 108 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN MOTOROLA AR Y Support Information "******* Data Bits Assignments ************* "******************************************* FLASH_ENABLE_DATA_BIT = [D0]; DRAM_ENABLE_DATA_BIT = [D1]; ETH_ENABLE_DATA_BIT = [D2]; INF_RED_ENABLE_DATA_BIT = [D3]; FLASH_CFG_ENABLE_DATA_BIT = [D4]; CNT_REG_EN_PROTECT_DATA_BIT = [D5]; CONT_REG_ENABLE_DATA_BIT = [D6]; RS232_1_ENABLE_DATA_BIT = [D7]; PCC_ENABLE_DATA_BIT = [D8]; PCC_VCC_0_DATA_BIT = [D9]; PCC_VPP0_DATA_BIT = [D10]; PCC_VPP1_DATA_BIT = [D11]; HALF_WORD_DATA_BIT = [D12]; RS232_2_ENABLE_DATA_BIT = [D13]; SDRAM_ENABLE_DATA_BIT = [D14]; PCC_VCC_1_DATA_BIT = [D15]; "****************************************************************************** "* BCSR 4 definitions. "****************************************************************************** "****************************************************************************** ETH_LOOP = 1; ETH_FULL_DUP = 0; ETH_CLSN_TEST = 0; SIGNAL_LAMP_ON = 0; USB_UTP_FETH_ENABLED = 0; USB_FULL_SPEED = 1; USB_VCC_CONT_0 = 0; VIDEO_ENABLED = 0; VIDEO_EXT_CLK_ENABLED = 1; VIDEO_RESET_ACTIVE = 0; MODEM_ENABLED_FOR_823 = 0; MODEM = 1; "*********************************************** "******* Power On Defaults Assignments ********* "*********************************************** ETH_LOOP_PON_DEFAULT = !ETH_LOOP; ETH_FULL_DUP_PON_DEFAULT = !ETH_FULL_DUP; ETH_CLSN_TEST_PON_DEFAULT = !ETH_CLSN_TEST; MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "****************************************************************************** IN AR Y 109 Support Information SIGNAL_LAMP_PON_DEFAULT = !SIGNAL_LAMP_ON; USB_UTP_FETH_EN_PON_DEFAULT = !USB_UTP_FETH_ENABLED; USB_SPEED_PON_DEFAULT = USB_FULL_SPEED; USB_VCC_0_CONT_PON_DEFAULT = !USB_VCC_CONT_0; USB_VCC_1_CONT_PON_DEFAULT = !USB_VCC_CONT_0; VIDEO_ENABLE_PON_DEFAULT = !VIDEO_ENABLED; VIDEO_EXT_CLK_EN_PON_DEFAULT = !VIDEO_EXT_CLK_ENABLED; VIDEO_RESET_PON_DEFAULT = !VIDEO_RESET_ACTIVE; MODEM_ENABLE_PON_DEFAULT = !MODEM_ENABLED_FOR_823; MODEM_FUNC_SEL_PON_DEFAULT = MODEM; "******************************************* "******* Data Bits Assignments ************* "******************************************* ETH_LOOP_DATA_BIT = [D0]; ETH_FULL_DUP_DATA_BIT = [D1]; ETH_CLSN_TEST_DATA_BIT = [D2]; SIGNAL_LAMP_DATA_BIT = [D3]; USB_UTP_FETH_EN_DATA_BIT = [D4]; USB_SPEED_DATA_BIT = [D5]; USB_VCC_0_DATA_BIT = [D6]; USB_VCC_1_DATA_BIT = [D7]; VIDEO_ENABLE_DATA_BIT = [D8]; VIDEO_EXT_CLK_EN_DATA_BIT = [D9]; VIDEO_RESET_DATA_BIT = [D10]; MODEM_ENABLE_DATA_BIT = [D11]; MODEM_FUNC_SEL_DATA_BIT = [D12]; "****************************************************************************** "* Equations, state diagrams. PR EL IM * * * ##### # # # # # # # # # # # #### # # # # # # # # # ## ## # # # # # # #### # #### # # # * * * * * * * # # ## ## # # # #### #### "****************************************************************************** "* "* ####### "* # "* # "* ##### "* # "* # "* ####### "* #### # # # # # # # # # # ## # # # # # # # # ## # ###### # # ### # #### "****************************************************************************** "* Configuration Register. "* Gets its default pon reset values which are driven to the data bus when "* during hard reset configuration. 110 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN MOTOROLA AR Y Support Information "* If other values are required, this register may be written with new values "* to become active for the next hard reset. "* The state machines are built in a way that its power on value is changed in "* one place - the declarations area. "****************************************************************************** equations @ifdef SLOW_PLL_LOCK { !PonDefault~ = !ResetConf~ # RGPORIn; } !Bcsr0Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); !Bcsr1Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~); !Bcsr4Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~); ConfigReg.clk = SYSCLK; state_diagram ERB state INTERNAL_ARBITRATION: if (MPC_WRITE_BCSR_0 & (ERB_DATA_BIT.pin == EXTERNAL_ARBITRATION) & (!KA_PON_RESET # (ERB_PON_DEFAULT != INTERNAL_ARBITRATION)) # state EXTERNAL_ARBITRATION: if (MPC_WRITE_BCSR_0 & (ERB_DATA_BIT.pin == INTERNAL_ARBITRATION) & (!KA_PON_RESET # (ERB_PON_DEFAULT != EXTERNAL_ARBITRATION)) # (KA_PON_RESET & (ERB_PON_DEFAULT == INTERNAL_ARBITRATION)) ) then INTERNAL_ARBITRATION else EXTERNAL_ARBITRATION; "****************************************************************************** state_diagram IP~ state IP_AT_0xFFF00000: MOTOROLA PR else (KA_PON_RESET & (ERB_PON_DEFAULT == EXTERNAL_ARBITRATION)) ) then EXTERNAL_ARBITRATION INTERNAL_ARBITRATION; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y 111 Support Information if (MPC_WRITE_BCSR_0 & (IP~_DATA_BIT.pin == IP_AT_0x00000000) & (!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0xFFF00000)) # (KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0x00000000)) ) then IP_AT_0x00000000 else IP_AT_0xFFF00000; state IP_AT_0x00000000: if (MPC_WRITE_BCSR_0 & (IP~_DATA_BIT.pin == IP_AT_0xFFF00000) & (!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0x00000000)) # (KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0xFFF00000)) ) then IP_AT_0xFFF00000 else IP_AT_0x00000000; "****************************************************************************** state_diagram RSV2 state !RSV2_ACTIVE: if (MPC_WRITE_BCSR_0 & (!KA_PON_RESET # (RSV2_PON_DEFAULT != !RSV2_ACTIVE)) # (KA_PON_RESET & (RSV2_PON_DEFAULT == RSV2_ACTIVE)) ) then RSV2_ACTIVE else !RSV2_ACTIVE; state RSV2_ACTIVE: if (MPC_WRITE_BCSR_0 & "****************************************************************************** state_diagram BDIS state BOOT_ENABLE: if (MPC_WRITE_BCSR_0 & (BDIS_DATA_BIT.pin == BOOT_DISABLE) & (!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_ENABLE)) # (KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_DISABLE)) ) then BOOT_DISABLE else 112 PR !RSV2_ACTIVE else RSV2_ACTIVE; (RSV2_DATA_BIT.pin == !RSV2_ACTIVE) & (!KA_PON_RESET # (RSV2_PON_DEFAULT != RSV2_ACTIVE)) # (KA_PON_RESET & (RSV2_PON_DEFAULT == !RSV2_ACTIVE)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (RSV2_DATA_BIT.pin == RSV2_ACTIVE) & IN MOTOROLA AR Y Support Information BOOT_ENABLE; state BOOT_DISABLE: if (MPC_WRITE_BCSR_0 & (BDIS_DATA_BIT.pin == BOOT_ENABLE) & (!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_DISABLE)) # (KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_ENABLE)) ) then BOOT_ENABLE else BOOT_DISABLE; "****************************************************************************** state_diagram BPS state BOOT_PORT_32: if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_8) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then BOOT_PORT_8 else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_16) & (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then BOOT_PORT_16 else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then BOOT_PORT_RESERVED state BOOT_PORT_8: MOTOROLA PR else BOOT_PORT_32; BOOT_PORT_32 BOOT_PORT_16 if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_32) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_16) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) & MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) # IN AR Y 113 Support Information (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then BOOT_PORT_RESERVED else BOOT_PORT_8; state BOOT_PORT_16: if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_32) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then BOOT_PORT_32 else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_8) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then BOOT_PORT_8 else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) # BOOT_PORT_RESERVED else BOOT_PORT_16; state BOOT_PORT_RESERVED: if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_32) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) # "****************************************************************************** 114 PR BOOT_PORT_32 BOOT_PORT_16 BOOT_PORT_8 else (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_16) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then else if (MPC_WRITE_BCSR_0 & (BPS_DATA_BIT.pin == BOOT_PORT_8) & (!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) # (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then BOOT_PORT_RESERVED; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then IN AR Y MOTOROLA Support Information state_diagram RSV6 state !RSV6_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV6_DATA_BIT.pin == RSV6_ACTIVE) & (!KA_PON_RESET # (RSV6_PON_DEFAULT != !RSV6_ACTIVE)) # (KA_PON_RESET & (RSV6_PON_DEFAULT == RSV6_ACTIVE)) ) then RSV6_ACTIVE else !RSV6_ACTIVE; state RSV2_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV6_DATA_BIT.pin == !RSV6_ACTIVE) & (!KA_PON_RESET # (RSV6_PON_DEFAULT != RSV6_ACTIVE)) # (KA_PON_RESET & (RSV6_PON_DEFAULT == !RSV6_ACTIVE)) ) then !RSV6_ACTIVE else RSV6_ACTIVE; "****************************************************************************** state_diagram ISB state INT_SPACE_BASE_0x00000000: if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then INT_SPACE_BASE_0x00F00000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) & state INT_SPACE_BASE_0x00F00000: if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) # MOTOROLA PR else (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then INT_SPACE_BASE_0xFF000000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then INT_SPACE_BASE_0xFFF00000 INT_SPACE_BASE_0x00000000; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y 115 Support Information (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then INT_SPACE_BASE_0x00000000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then INT_SPACE_BASE_0xFF000000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then INT_SPACE_BASE_0xFFF00000 else INT_SPACE_BASE_0x00F00000; state INT_SPACE_BASE_0xFF000000: if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) # INT_SPACE_BASE_0x00000000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then INT_SPACE_BASE_0x00F00000 else if (MPC_WRITE_BCSR_0 & state INT_SPACE_BASE_0xFFF00000: if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then INT_SPACE_BASE_0x00000000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) & 116 PR else (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then INT_SPACE_BASE_0xFFF00000 INT_SPACE_BASE_0xFF000000; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then IN AR Y MOTOROLA Support Information (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then INT_SPACE_BASE_0x00F00000 else if (MPC_WRITE_BCSR_0 & (ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) & (!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) # (KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then INT_SPACE_BASE_0xFF000000 else INT_SPACE_BASE_0xFFF00000; "****************************************************************************** state_diagram DBGC state DEBUG_PINS_PCMCIA_2: if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then DEBUG_PINS_WATCH_POINTS else if (MPC_WRITE_BCSR_0 & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then DEBUG_PINS_RESREVED else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then state DEBUG_PINS_WATCH_POINTS: if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then DEBUG_PINS_PCMCIA_2 else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then DEBUG_PINS_RESREVED MOTOROLA PR else DEBUG_PINS_FOR_SHOW DEBUG_PINS_PCMCIA_2; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) & IN AR Y 117 Support Information else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then DEBUG_PINS_FOR_SHOW else DEBUG_PINS_WATCH_POINTS; state DEBUG_PINS_RESREVED: if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then DEBUG_PINS_PCMCIA_2 else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then DEBUG_PINS_WATCH_POINTS else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then DEBUG_PINS_FOR_SHOW else DEBUG_PINS_RESREVED; state DEBUG_PINS_FOR_SHOW: 118 PR if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then DEBUG_PINS_PCMCIA_2 else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then DEBUG_PINS_WATCH_POINTS else if (MPC_WRITE_BCSR_0 & (DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) & (!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) # (KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then DEBUG_PINS_RESREVED MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y MOTOROLA Support Information else DEBUG_PINS_FOR_SHOW; "****************************************************************************** state_diagram DBPC state DEBUG_PORT_ON_JTAG: if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then DEBUG_PORT_NON_EXISTANT else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then DEBUG_PORT_RESERVED else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then else DEBUG_PORT_ON_JTAG; state DEBUG_PORT_NON_EXISTANT: if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) # MOTOROLA PR else (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then DEBUG_PORT_ON_JTAG else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then DEBUG_PORT_RESERVED else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then DEBUG_PORT_ON_DEBUG_PINS DEBUG_PORT_NON_EXISTANT; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM DEBUG_PORT_ON_DEBUG_PINS IN AR Y 119 Support Information state DEBUG_PORT_RESERVED: if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then DEBUG_PORT_ON_JTAG else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then DEBUG_PORT_NON_EXISTANT else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then DEBUG_PORT_ON_DEBUG_PINS else DEBUG_PORT_RESERVED; if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then DEBUG_PORT_ON_JTAG else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) & "****************************************************************************** state_diagram RSV13 state !RSV13_ACTIVE: if (MPC_WRITE_BCSR_0 & 120 PR else (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then DEBUG_PORT_NON_EXISTANT else if (MPC_WRITE_BCSR_0 & (DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) & (!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) # (KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then DEBUG_PORT_RESERVED DEBUG_PORT_ON_DEBUG_PINS; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM state DEBUG_PORT_ON_DEBUG_PINS: IN MOTOROLA AR Y Support Information (RSV13_DATA_BIT.pin == RSV13_ACTIVE) & (!KA_PON_RESET # (RSV13_PON_DEFAULT != !RSV13_ACTIVE)) # (KA_PON_RESET & (RSV13_PON_DEFAULT == RSV13_ACTIVE)) ) then RSV13_ACTIVE else !RSV13_ACTIVE; state RSV13_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV13_DATA_BIT.pin == !RSV13_ACTIVE) & (!KA_PON_RESET # (RSV13_PON_DEFAULT != RSV13_ACTIVE)) # (KA_PON_RESET & (RSV13_PON_DEFAULT == !RSV13_ACTIVE)) ) then !RSV13_ACTIVE else RSV13_ACTIVE; "****************************************************************************** state_diagram RSV14 state !RSV14_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV14_DATA_BIT.pin == RSV14_ACTIVE) & (KA_PON_RESET & (RSV14_PON_DEFAULT == RSV14_ACTIVE)) ) then RSV14_ACTIVE else !RSV14_ACTIVE; state RSV14_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV14_DATA_BIT.pin == !RSV14_ACTIVE) & "****************************************************************************** state_diagram RSV15 state !RSV15_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV15_DATA_BIT.pin == RSV15_ACTIVE) & (!KA_PON_RESET # (RSV15_PON_DEFAULT != !RSV15_ACTIVE)) # (KA_PON_RESET & (RSV15_PON_DEFAULT == RSV15_ACTIVE)) ) then RSV15_ACTIVE else !RSV15_ACTIVE; MOTOROLA PR !RSV14_ACTIVE else RSV14_ACTIVE; (!KA_PON_RESET # (RSV14_PON_DEFAULT != RSV14_ACTIVE)) # (KA_PON_RESET & (RSV14_PON_DEFAULT == !RSV14_ACTIVE)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (RSV14_PON_DEFAULT != !RSV14_ACTIVE)) # IN AR Y 121 Support Information state RSV15_ACTIVE: if (MPC_WRITE_BCSR_0 & (RSV15_DATA_BIT.pin == !RSV15_ACTIVE) & (!KA_PON_RESET # (RSV15_PON_DEFAULT != RSV15_ACTIVE)) # (KA_PON_RESET & (RSV15_PON_DEFAULT == !RSV15_ACTIVE)) ) then !RSV15_ACTIVE else RSV15_ACTIVE; "****************************************************************************** "****************************************************************************** "* BCSR 1 "****************************************************************************** "****************************************************************************** equations WideContReg.clk = SYSCLK; DrivenContReg.oe = ^hfffffff; state_diagram FlashEn~ state FLASH_ENABLED: if (MPC_WRITE_BCSR_1 & (FLASH_ENABLE_DATA_BIT.pin == !FLASH_ENABLED) & (!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != FLASH_ENABLED)) # (KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == !FLASH_ENABLED)) ) then !FLASH_ENABLED else FLASH_ENABLED; state !FLASH_ENABLED: "****************************************************************************** state_diagram DramEn~ state DRAM_ENABLED: if (MPC_WRITE_BCSR_1 & (DRAM_ENABLE_DATA_BIT.pin == !DRAM_ENABLED) & (!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != DRAM_ENABLED)) # (KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == !DRAM_ENABLED)) ) then 122 PR FLASH_ENABLED else !FLASH_ENABLED; if (MPC_WRITE_BCSR_1 & (FLASH_ENABLE_DATA_BIT.pin == FLASH_ENABLED) & (!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != !FLASH_ENABLED)) # (KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == FLASH_ENABLED)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN MOTOROLA AR Y Support Information !DRAM_ENABLED else DRAM_ENABLED; state !DRAM_ENABLED: if (MPC_WRITE_BCSR_1 & (DRAM_ENABLE_DATA_BIT.pin == DRAM_ENABLED) & (!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != !DRAM_ENABLED)) # (KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == DRAM_ENABLED)) ) then DRAM_ENABLED else !DRAM_ENABLED; "****************************************************************************** state_diagram EthEn~ state ETH_ENABLED: if (MPC_WRITE_BCSR_1 & (ETH_ENABLE_DATA_BIT.pin == !ETH_ENABLED) & (!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != ETH_ENABLED)) # (KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == !ETH_ENABLED)) ) then else ETH_ENABLED; state !ETH_ENABLED: if (MPC_WRITE_BCSR_1 & (ETH_ENABLE_DATA_BIT.pin == ETH_ENABLED) & (!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != !ETH_ENABLED)) # (KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == ETH_ENABLED)) ) then "****************************************************************************** state_diagram InfRedEn~ state INF_RED_ENABLE: if (MPC_WRITE_BCSR_1 & (INF_RED_ENABLE_DATA_BIT.pin == !INF_RED_ENABLE) & (!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != INF_RED_ENABLE)) # (KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == !INF_RED_ENABLE)) ) then !INF_RED_ENABLE else INF_RED_ENABLE; state !INF_RED_ENABLE: if (MPC_WRITE_BCSR_1 & MOTOROLA PR ETH_ENABLED else !ETH_ENABLED; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM !ETH_ENABLED IN AR Y 123 Support Information (INF_RED_ENABLE_DATA_BIT.pin == INF_RED_ENABLE) & (!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != !INF_RED_ENABLE)) # (KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == INF_RED_ENABLE)) ) then INF_RED_ENABLE else !INF_RED_ENABLE; "****************************************************************************** state_diagram FlashCfgEn~ state FLASH_CFG_ENABLE: if (MPC_WRITE_BCSR_1 & (FLASH_CFG_ENABLE_DATA_BIT.pin == !FLASH_CFG_ENABLE) & (!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != FLASH_CFG_ENABLE)) # (KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == !FLASH_CFG_ENABLE)) )then !FLASH_CFG_ENABLE else FLASH_CFG_ENABLE; state !FLASH_CFG_ENABLE: if (MPC_WRITE_BCSR_1 & (FLASH_CFG_ENABLE_DATA_BIT.pin == FLASH_CFG_ENABLE) & (KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == FLASH_CFG_ENABLE)) ) then FLASH_CFG_ENABLE else !FLASH_CFG_ENABLE; "****************************************************************************** "* To avoid in advertant write to the Control Register Enable bit, which might "* result in a need to re-power the board - protection logic is provided. "* In order of writing the Control Register Enable this bit in the status register "* must be negated. After any write to the control register, this bit asserts "* again (to protected mode) "****************************************************************************** equations CntRegEnProtect~.clk = SYSCLK; state_diagram CntRegEnProtect~ state CNT_REG_EN_PROTECT: if (MPC_WRITE_BCSR_3 & (CNT_REG_EN_PROTECT_DATA_BIT.pin == !CNT_REG_EN_PROTECT) & (!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != CNT_REG_EN_PROTECT)) # (KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == !CNT_REG_EN_PROTECT)) then !CNT_REG_EN_PROTECT 124 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != !FLASH_CFG_ENABLE)) # IN AR Y MOTOROLA Support Information else CNT_REG_EN_PROTECT; state !CNT_REG_EN_PROTECT: if (MPC_WRITE_BCSR_3 & (CNT_REG_EN_PROTECT_DATA_BIT.pin == CNT_REG_EN_PROTECT) & (!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != !CNT_REG_EN_PROTECT)) # (KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == CNT_REG_EN_PROTECT)) # MPC_WRITE_BCSR_1) then " any write to control reg 1 CNT_REG_EN_PROTECT else !CNT_REG_EN_PROTECT; "****************************************************************************** "* protected by CntRegEnProtect~ to prevent from inadvertant write "****************************************************************************** state_diagram CntRegEn~ state CONT_REG_ENABLE: if (MPC_WRITE_BCSR_1 & (CntRegEnProtect~.fb != CNT_REG_EN_PROTECT) & (CONT_REG_ENABLE_DATA_BIT.pin == !CONT_REG_ENABLE) & (!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != CONT_REG_ENABLE)) # !CONT_REG_ENABLE else CONT_REG_ENABLE; state !CONT_REG_ENABLE:" in fact not applicable if (MPC_WRITE_BCSR_1 & (CONT_REG_ENABLE_DATA_BIT.pin == CONT_REG_ENABLE) & (!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != !CONT_REG_ENABLE)) # "****************************************************************************** state_diagram RS232En1~ state RS232_1_ENABLE: if (MPC_WRITE_BCSR_1 & (RS232_1_ENABLE_DATA_BIT.pin == !RS232_1_ENABLE) & (!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != RS232_1_ENABLE)) # (KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == !RS232_1_ENABLE)) ) then !RS232_1_ENABLE else RS232_1_ENABLE; state !RS232_1_ENABLE: MOTOROLA PR CONT_REG_ENABLE else (KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == CONT_REG_ENABLE)) ) then !CONT_REG_ENABLE; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == !CONT_REG_ENABLE)) ) then IN AR Y 125 Support Information if (MPC_WRITE_BCSR_1 & (RS232_1_ENABLE_DATA_BIT.pin == RS232_1_ENABLE) & (!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != !RS232_1_ENABLE)) # (KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == RS232_1_ENABLE)) ) then RS232_1_ENABLE else !RS232_1_ENABLE; "****************************************************************************** state_diagram PccEn~ state PCC_ENABLE: if (MPC_WRITE_BCSR_1 & (PCC_ENABLE_DATA_BIT.pin == !PCC_ENABLE) & (!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != PCC_ENABLE)) # (KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == !PCC_ENABLE)) ) then !PCC_ENABLE else PCC_ENABLE; state !PCC_ENABLE: if (MPC_WRITE_BCSR_1 & (!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != !PCC_ENABLE)) # (KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == PCC_ENABLE)) ) then PCC_ENABLE else !PCC_ENABLE; "****************************************************************************** state_diagram PccVcc0 state PCC_VCC_CONT_0: state !PCC_VCC_CONT_0: if (MPC_WRITE_BCSR_1 & (PCC_VCC_0_DATA_BIT.pin == PCC_VCC_CONT_0) & (!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != !PCC_VCC_CONT_0)) # (KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == PCC_VCC_CONT_0)) ) then PCC_VCC_CONT_0 else 126 PR !PCC_VCC_CONT_0 else PCC_VCC_CONT_0; if (MPC_WRITE_BCSR_1 & (PCC_VCC_0_DATA_BIT.pin == !PCC_VCC_CONT_0) & (!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != PCC_VCC_CONT_0)) # (KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (PCC_ENABLE_DATA_BIT.pin == PCC_ENABLE) & IN MOTOROLA AR Y Support Information !PCC_VCC_CONT_0; "****************************************************************************** state_diagram PccVpp0 state PCC_VPP0: if (MPC_WRITE_BCSR_1 & (PCC_VPP0_DATA_BIT.pin == !PCC_VPP0) & (!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != PCC_VPP0)) # (KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == !PCC_VPP0)) ) then !PCC_VPP0 else PCC_VPP0; state !PCC_VPP0: if (MPC_WRITE_BCSR_1 & (PCC_VPP0_DATA_BIT.pin == PCC_VPP0) & (!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != !PCC_VPP0)) # (KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == PCC_VPP0)) ) then PCC_VPP0 else !PCC_VPP0; "****************************************************************************** state_diagram PccVpp1 state PCC_VPP1: if (MPC_WRITE_BCSR_1 & (PCC_VPP1_DATA_BIT.pin == !PCC_VPP1) & (!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != PCC_VPP1)) # (KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == !PCC_VPP1)) ) then state !PCC_VPP1: "****************************************************************************** state_diagram HalfWord~ state HALF_WORD: if (MPC_WRITE_BCSR_1 & MOTOROLA PR !PCC_VPP1 else PCC_VPP1; PCC_VPP1 else !PCC_VPP1; if (MPC_WRITE_BCSR_1 & (PCC_VPP1_DATA_BIT.pin == PCC_VPP1) & (!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != !PCC_VPP1)) # (KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == PCC_VPP1)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 127 AR Y Support Information (HALF_WORD_DATA_BIT.pin == !HALF_WORD) & (!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != HALF_WORD)) # (KA_PON_RESET & (HALF_WORD_PON_DEFAULT == !HALF_WORD)) ) then !HALF_WORD else HALF_WORD; state !HALF_WORD: if (MPC_WRITE_BCSR_1 & (HALF_WORD_DATA_BIT.pin == HALF_WORD) & (!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != !HALF_WORD)) # (KA_PON_RESET & (HALF_WORD_PON_DEFAULT == HALF_WORD)) ) then HALF_WORD else !HALF_WORD; "****************************************************************************** state_diagram RS232En2~ state RS232_2_ENABLE: if (MPC_WRITE_BCSR_1 & (RS232_2_ENABLE_DATA_BIT.pin == !RS232_2_ENABLE) & (KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == !RS232_2_ENABLE)) ) then !RS232_2_ENABLE else RS232_2_ENABLE; state !RS232_2_ENABLE: if (MPC_WRITE_BCSR_1 & (RS232_2_ENABLE_DATA_BIT.pin == RS232_2_ENABLE) & "****************************************************************************** state_diagram PccVcc1 state PCC_VCC_CONT_0: if (MPC_WRITE_BCSR_1 & (PCC_VCC_1_DATA_BIT.pin == !PCC_VCC_CONT_0) & (!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != PCC_VCC_CONT_0)) # (KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then !PCC_VCC_CONT_0 else PCC_VCC_CONT_0; 128 PR RS232_2_ENABLE else !RS232_2_ENABLE; (!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != !RS232_2_ENABLE)) # (KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != RS232_2_ENABLE)) # IN AR Y MOTOROLA Support Information state !PCC_VCC_CONT_0: if (MPC_WRITE_BCSR_1 & (PCC_VCC_1_DATA_BIT.pin == PCC_VCC_CONT_0) & (!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != !PCC_VCC_CONT_0)) # (KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == PCC_VCC_CONT_0)) ) then PCC_VCC_CONT_0 else !PCC_VCC_CONT_0; "****************************************************************************** state_diagram SdramEn~ state SDRAM_ENABLED: if (MPC_WRITE_BCSR_1 & (SDRAM_ENABLE_DATA_BIT.pin == !SDRAM_ENABLED) & (!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != SDRAM_ENABLED)) # (KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == !SDRAM_ENABLED)) ) then !SDRAM_ENABLED else SDRAM_ENABLED; state !SDRAM_ENABLED: if (MPC_WRITE_BCSR_1 & (SDRAM_ENABLE_DATA_BIT.pin == SDRAM_ENABLED) & (!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != !SDRAM_ENABLED)) # (KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == SDRAM_ENABLED)) ) then SDRAM_ENABLED else !SDRAM_ENABLED; "****************************************************************************** "****************************************************************************** "* BCSR4 State Machines "****************************************************************************** "****************************************************************************** state_diagram UsbUtpFethEn~ state USB_UTP_FETH_ENABLED: if (MPC_WRITE_BCSR_4 & (USB_UTP_FETH_EN_DATA_BIT.pin == !USB_UTP_FETH_ENABLED) & (!KA_PON_RESET # (USB_UTP_FETH_EN_PON_DEFAULT != USB_UTP_FETH_ENABLED)) # (KA_PON_RESET & (USB_UTP_FETH_EN_PON_DEFAULT == !USB_UTP_FETH_ENABLED)) ) then !USB_UTP_FETH_ENABLED else MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 129 AR Y Support Information USB_UTP_FETH_ENABLED; state !USB_UTP_FETH_ENABLED: if (MPC_WRITE_BCSR_4 & (USB_UTP_FETH_EN_DATA_BIT.pin == USB_UTP_FETH_ENABLED) & (!KA_PON_RESET # (USB_UTP_FETH_EN_PON_DEFAULT != !USB_UTP_FETH_ENABLED)) # (KA_PON_RESET & (USB_UTP_FETH_EN_PON_DEFAULT == USB_UTP_FETH_ENABLED)) )then USB_UTP_FETH_ENABLED else !USB_UTP_FETH_ENABLED; "****************************************************************************** state_diagram UsbSpeed state USB_FULL_SPEED: if (MPC_WRITE_BCSR_4 & (USB_SPEED_DATA_BIT.pin == !USB_FULL_SPEED) & (!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != USB_FULL_SPEED)) # (KA_PON_RESET & (USB_SPEED_PON_DEFAULT == !USB_FULL_SPEED)) ) then !USB_FULL_SPEED else USB_FULL_SPEED; state !USB_FULL_SPEED: if (MPC_WRITE_BCSR_4 & (USB_SPEED_DATA_BIT.pin == USB_FULL_SPEED) & (!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != !USB_FULL_SPEED)) # (KA_PON_RESET & (USB_SPEED_PON_DEFAULT == USB_FULL_SPEED)) ) then USB_FULL_SPEED else "****************************************************************************** state_diagram UsbVcc0 state USB_VCC_CONT_0: if (MPC_WRITE_BCSR_4 & (USB_VCC_0_DATA_BIT.pin == !USB_VCC_CONT_0) & (!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != USB_VCC_CONT_0)) # (KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then !USB_VCC_CONT_0 else USB_VCC_CONT_0; state !USB_VCC_CONT_0: if (MPC_WRITE_BCSR_4 & 130 PR !USB_FULL_SPEED; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y MOTOROLA Support Information (PCC_VCC_0_DATA_BIT.pin == PCC_VCC_CONT_0) & (!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) # (KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then USB_VCC_CONT_0 else !USB_VCC_CONT_0; "****************************************************************************** state_diagram UsbVcc1 state USB_VCC_CONT_0: if (MPC_WRITE_BCSR_4 & (USB_VCC_1_DATA_BIT.pin == !USB_VCC_CONT_0) & (!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != USB_VCC_CONT_0)) # (KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then !USB_VCC_CONT_0 else USB_VCC_CONT_0; state !USB_VCC_CONT_0: if (MPC_WRITE_BCSR_4 & (PCC_VCC_1_DATA_BIT.pin == PCC_VCC_CONT_0) & (KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then USB_VCC_CONT_0 else !USB_VCC_CONT_0; "****************************************************************************** state_diagram VideoOn~ state VIDEO_ENABLED: state !VIDEO_ENABLED: if (MPC_WRITE_BCSR_4 & (VIDEO_ENABLE_DATA_BIT.pin == VIDEO_ENABLED) & (!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != !VIDEO_ENABLED)) # (KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == VIDEO_ENABLED)) ) then VIDEO_ENABLED else MOTOROLA PR !VIDEO_ENABLED else VIDEO_ENABLED; if (MPC_WRITE_BCSR_4 & (VIDEO_ENABLE_DATA_BIT.pin == !VIDEO_ENABLED) & (!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != VIDEO_ENABLED)) # (KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == !VIDEO_ENABLED)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) # IN AR Y 131 Support Information !VIDEO_ENABLED; "****************************************************************************** state_diagram VideoExtClkEn state VIDEO_EXT_CLK_ENABLED: if (MPC_WRITE_BCSR_4 & (VIDEO_EXT_CLK_EN_DATA_BIT.pin == !VIDEO_EXT_CLK_ENABLED) & (!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != VIDEO_EXT_CLK_ENABLED)# (KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT ==!VIDEO_EXT_CLK_ENABLED)))then !VIDEO_EXT_CLK_ENABLED else VIDEO_EXT_CLK_ENABLED; state !VIDEO_EXT_CLK_ENABLED: if (MPC_WRITE_BCSR_4 & (VIDEO_EXT_CLK_EN_DATA_BIT.pin == VIDEO_EXT_CLK_ENABLED) & (!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != !VIDEO_EXT_CLK_ENABLED)) # (KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT == VIDEO_EXT_CLK_ENABLED)) ) then VIDEO_EXT_CLK_ENABLED else !VIDEO_EXT_CLK_ENABLED; "****************************************************************************** state_diagram VideoRst~ state VIDEO_RESET_ACTIVE: if (MPC_WRITE_BCSR_4 & (VIDEO_RESET_DATA_BIT.pin == !VIDEO_RESET_ACTIVE) & (!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != VIDEO_RESET_ACTIVE)) # (KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == !VIDEO_RESET_ACTIVE)) ) then state !VIDEO_RESET_ACTIVE: if (MPC_WRITE_BCSR_4 & (VIDEO_RESET_DATA_BIT.pin == VIDEO_RESET_ACTIVE) & (!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != !VIDEO_RESET_ACTIVE)) # (KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == VIDEO_RESET_ACTIVE)) ) then VIDEO_RESET_ACTIVE else !VIDEO_RESET_ACTIVE; "****************************************************************************** state_diagram SignaLamp~ state SIGNAL_LAMP_ON: if (MPC_WRITE_BCSR_4 & 132 PR else !VIDEO_RESET_ACTIVE VIDEO_RESET_ACTIVE; MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y MOTOROLA Support Information (SIGNAL_LAMP_DATA_BIT.pin == !SIGNAL_LAMP_ON) & (!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != SIGNAL_LAMP_ON)) # (KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then !SIGNAL_LAMP_ON else SIGNAL_LAMP_ON; state !SIGNAL_LAMP_ON: if (MPC_WRITE_BCSR_4 & (SIGNAL_LAMP_DATA_BIT.pin == SIGNAL_LAMP_ON) & (!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != !SIGNAL_LAMP_ON)) # (KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then SIGNAL_LAMP_ON else !SIGNAL_LAMP_ON; "****************************************************************************** state_diagram EthLoop state ETH_LOOP: if (MPC_WRITE_BCSR_4 & (ETH_LOOP_DATA_BIT.pin == !ETH_LOOP) & (KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == !ETH_LOOP)) ) then !ETH_LOOP else ETH_LOOP; state !ETH_LOOP: if (MPC_WRITE_BCSR_4 & (ETH_LOOP_DATA_BIT.pin == ETH_LOOP) & "****************************************************************************** state_diagram TPFLDL~ state ETH_FULL_DUP: if (MPC_WRITE_BCSR_4 & (ETH_FULL_DUP_DATA_BIT.pin == !ETH_FULL_DUP) & (!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != ETH_FULL_DUP)) # (KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == !ETH_FULL_DUP)) ) then !ETH_FULL_DUP else ETH_FULL_DUP; MOTOROLA PR ETH_LOOP else !ETH_LOOP; (!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != !ETH_LOOP)) # (KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == ETH_LOOP)) ) then MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM (!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != ETH_LOOP)) # IN AR Y 133 Support Information state !ETH_FULL_DUP: if (MPC_WRITE_BCSR_4 & (ETH_FULL_DUP_DATA_BIT.pin == ETH_FULL_DUP) & (!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != !ETH_FULL_DUP)) # (KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == ETH_FULL_DUP)) ) then ETH_FULL_DUP else !ETH_FULL_DUP; "****************************************************************************** state_diagram TPSQEL~ state ETH_CLSN_TEST: if (MPC_WRITE_BCSR_4 & (ETH_CLSN_TEST_DATA_BIT.pin == !ETH_CLSN_TEST) & (!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != ETH_CLSN_TEST)) # (KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == !ETH_CLSN_TEST)) ) then !ETH_CLSN_TEST else ETH_CLSN_TEST; state !ETH_CLSN_TEST: if (MPC_WRITE_BCSR_4 & (ETH_CLSN_TEST_DATA_BIT.pin == ETH_CLSN_TEST) & (!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != !ETH_CLSN_TEST)) # (KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == ETH_CLSN_TEST)) ) then ETH_CLSN_TEST else !ETH_CLSN_TEST; "****************************************************************************** state_diagram ModemEn~ state MODEM_ENABLED_FOR_823: if (MPC_WRITE_BCSR_4 & (MODEM_ENABLE_DATA_BIT.pin == !MODEM_ENABLED_FOR_823) & (!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != MODEM_ENABLED_FOR_823)) # (KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == !MODEM_ENABLED_FOR_823)) ) then !MODEM_ENABLED_FOR_823 else MODEM_ENABLED_FOR_823; state !MODEM_ENABLED_FOR_823: if (MPC_WRITE_BCSR_4 & (MODEM_ENABLE_DATA_BIT.pin == MODEM_ENABLED_FOR_823) & (!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != !MODEM_ENABLED_FOR_823)) # (KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == MODEM_ENABLED_FOR_823)) ) then MODEM_ENABLED_FOR_823 134 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN MOTOROLA AR Y Support Information else !MODEM_ENABLED_FOR_823; "****************************************************************************** state_diagram Modem_Audio~ state MODEM: if (MPC_WRITE_BCSR_4 & (MODEM_FUNC_SEL_DATA_BIT.pin == !MODEM) & (!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != MODEM)) # (KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == !MODEM)) ) then !MODEM else MODEM; state !MODEM: if (MPC_WRITE_BCSR_4 & (MODEM_FUNC_SEL_DATA_BIT.pin == MODEM) & (!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != !MODEM)) # (KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == MODEM)) ) then MODEM else !MODEM; "****************************************************************************** "****************************************************************************** " External Read Registers' Chip-Selects "****************************************************************************** "****************************************************************************** equations Bcsr2_3Cs~.oe = 3; !Bcsr2Cs~ = MPC_READ_BCSR_2; !Bcsr3Cs~ = MPC_READ_BCSR_3; "****************************************************************************** "****************************************************************************** "* Read Registers. "* All registers have read capabilty. "****************************************************************************** "****************************************************************************** equations DataOe = MPC_READ_BCSR_0 # MPC_READ_BCSR_1 # MPC_READ_BCSR_4 # MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y 135 Support Information RESET_CONFIG_DRIVEN; Data.oe = DataOe; " Data.oe = ^hffff; when (MPC_READ_BCSR_0 # RESET_CONFIG_DRIVEN) then Data = [ERB.fb,IP~.fb,RSV2.fb,BDIS.fb,BPS0.fb,BPS1.fb,RSV6.fb, ISB0.fb,ISB1.fb,DBGC0.fb,DBGC1.fb,DBPC0.fb,DBPC1.fb, RSV13.fb,RSV14.fb,RSV15.fb]; else when (MPC_READ_BCSR_1) then Data = ReadBcsr1; else when (MPC_READ_BCSR_4) then " " Speed,UsbVcc0, mEn~,Modem_Audio~,0,0,0]; Data = [UsbUtpFethEn~,UsbSpeed,UsbVcc0, UsbVcc1, VideoOn~,VideoExtClkEn, VideoRst~,SignaLamp~,EthLoop,TPFLDL~,TPSQEL~,Modem_Audio~,0,0,0,0]; Data = [EthLoop,TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,Usb end bcsr10 "****************************************************************************** 136 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN UsbVcc1, VideoOn~,VideoExtClkEn,VideoRst~,Mode- AR Y MOTOROLA Support Information A*3 U22 - Auxiliary Board Control "****************************************************************************** "****************************************************************************** "* In this file (5): "* 1) The use of BCLOSE~ is removed. This due to the assignment "* "* "* "* BCLOSE~ to GPL4A. In order of using of GPL4A bit in the upm to determine data sampling edge, GPL4A may not be used as a GPL. Therefore DramBankXCs~ must envelope the cycle so that data buffers remain open throughout the cycle. "* 2) Removed CS support for flash configuration. I.e., FlashCs1~ will not be "* "* "* "* asserted during hard reset. Flash configuration will be supported on silicon next revisions. data buffers will still open for flash configuration when hard reset asserted and flash configuration option bit, asserted. "* 3) Since Bclose~ is no longer available, the data buffers will open "* "* to provide data hold (0) on write cycles to flash, CSNT bit in the OR should be programmed active, while ACS == 00. "****************************************************************************** "* In This file (6), A12 and A11 are removed from the flash selection equation "* since they can select only a 1/2 Mbyte of flash rather then 2Mbyte selection "* needed. Therefore, only one bank of 2 Mbyte flash may be used (MCM29F020). "****************************************************************************** "* In this file (7): "* - Pon Reset Out is removed. Pon Reset is driven directly to MPC. "* - A9 and A10 replace A11 and A12 in flash bank selection "* - Optional BufClose~ is removed. "* - DramEn becomes active-low to support debug-station support changes. "* - Added F_PD(1:3) to support SMART Flash SIMMs. "* - Support for 32KHz crystal - renewed. "****************************************************************************** "* In this file (8): "* - Added protection against data contention for write cycles after "* "* "* "* Flash read cycle. This is achieved using a state-machine which identifies end of flash read and a chain of internal gates serving as a delay line. This kind of solution guaranties a fixed delay over the data buffer enable signal, that is, only after a flash read cycle. "****************************************************************************** "* In this file (9): MOTOROLA PR "* - Modck0 becomes Modck2 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL "* The rest of the CS are driven high constantly. IM IN "* asynchronously. I.e., driven directly by the various chip-selects. AR Y 137 Support Information "* - The addressing scheme of the flash is changed so that the bank does "* "* not occupy a space bigger than its real size. I.e. A9 and A10 use is conditioned with the module type. "****************************************************************************** " In this file (10): "* - A bug is fixed in Smart flash memories presence detect encoding: "* "* for SM732A1000A - F_PD == 5 (was 2) for SM732A2000 - F_PD == 4 (was 3) "****************************************************************************** "* In this file (11): "* - KAPORIn (power-on reset input) line is removed. It was unused previously. "* - Instead of the the above, F_PD4 input is added, so excact identification "* may be given to any flash memory. "* - Number of delay stages for flash turn-off time protection is decreased "* This to avoid possible problem in write to 0-w.s. memories. "****************************************************************************** "* In This file (12): "* - Added ATA support for PCMCIA. I.e., PccEvenEn~ and PccOddEn~ become "* identical, enabled by logic OR of CE1~ and CE2~ module brdctl12 title 'MPC821ADS Board Misc. Control Functions. Originated for MPC821ADS, Yair Liebman - (MSIL) - April 10, 1995' "****************************************************************************** "* Device declaration. PR EL IM ##### # # # # # ## ## # # # ##### # # # # "****************************************************************************** IN # # # ## # # # # ## ## # ###### # # # # "****************************************************************************** U22 device 'mach220a'; "****************************************************************************** "* ####### "* # "* # "* ##### "* # "* # "* ####### # # * # # ##### # # # # # ###### # ##### # # ###### # # # # # ###### # #### # #### # # * * * * * * ## ## # # # # "****************************************************************************** 138 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y * #### MOTOROLA Support Information "****************************************************************************** "* Pins declaration. * "****************************************************************************** "****************************************************************************** "* clock generator "****************************************************************************** SYSCLKPIN 50;" pda clkout "****************************************************************************** "* Dram Associated Pins. "****************************************************************************** A9 PIN 55; A10 PIN 39; A19 PIN 38; A20 PIN 2; A30 PIN 36;" pda address lines inputs (IN) SizeDetect1PIN 26; SizeDetect0PIN 20; " dram simm size detect lines (IN) HalfWord~PIN 51; " dram port width selection from control register: " '1' - 32 bit " '0' - 16 bit DramBank1Cs~PIN 45;" 1'st bank chip-select(IN, L) DramBank2Cs~PIN 46;" 2'nd bank chip-select (IN, L) DramEn~PIN 54;" Dram enable from control reg. (IN, H). Active " high to support power control. DramAdd10PIN 32 istype 'com'; DramAdd9PIN 33 istype 'com';" dram address lines Ras1~PIN 28 istype 'com'; Ras1DD~PIN 30 istype 'com'; Ras2~PIN 29 istype 'com'; Ras2DD~PIN 31 istype 'com';" dram RAS lines. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM R_W~ PIN 23; IN 139 AR Y Support Information "****************************************************************************** "* Flash Associated Pins. "****************************************************************************** F_PD1PIN 7; F_PD2PIN 65; F_PD3PIN 41; F_PD4PIN 25; FlashCs~ PIN 49;" flash bank chip-select FlashEn~PIN 15;" flash enable from control reg. FlashCs1~PIN 12 istype 'com';" Flash bank1 chip-select FlashCs2~PIN 22 istype 'com';" Flash bank2 chip-select FlashCs3~PIN 57 istype 'com';" Flash bank3 chip-select FlashCs4~PIN 24 istype 'com';" Flash bank4 chip-select FlashOe~PIN 58 istype 'com';" Flash output enable. "****************************************************************************** "****************************************************************************** ContRegCs~PIN 59;" control register cs from MPC8XX ContRegEn~PIN 56;" control register enable from control register. "****************************************************************************** "* Reset & Interrupt Logic Pins. "****************************************************************************** Rst0 Rst1 PR PIN 13; PIN 21; EL IM "* Control Register pins " connected to N.C. of " connected to N.O. of IN !RegPORIn~PIN 9; " Regular Power On Reset In. (H) HardReset~PIN 48 istype 'com'; SoftReset~PIN 40 istype 'com'; ResetConfig~PIN 67 istype 'com'; " Actual hard reset output (O.D.) " Actual soft reset output (O.D.) " Drives the RSTCONF* signal of the MPC8XX. DriveConfig~PIN 63 istype 'com';" Drives configuration data to the MPC8XX Abr0 PIN 10; Abr1 PIN 11; " connected to N.C. of " connected to N.O. of Abort P.B. Abort P.B. NMIEnNODE istype 'com'; " enables T.S. NMI pin 140 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y Reset P.B. Reset P.B. MOTOROLA Support Information NMI~ PIN 44 istype 'com'; " Actual NMI pin (O.D.) "****************************************************************************** "* Power On Reset Configuration Support "****************************************************************************** ModInPIN 64;" MODCK dip-switch Modck2PIN 60 istype 'com';" MODCK2 output Modck1PIN 66 istype 'com';" MODCK1 output ModckOeNODE istype 'com';" enables MODCKs towards MPC8XX during " Hard Reset. "****************************************************************************** "* Data Buffers Enables and Reset configuration support "****************************************************************************** TA~ PIN 6; TEA~ PIN 47; " transfer Acknowledge " Transfer Error Acknowledge. " register. PccEn~PIN 4; " PCMCIA channel enable from control reg. PccCE1~PIN 16; PccCE2~PIN 43; UpperHalfEn~PIN 3 istype 'com,invert'; LowerHalfEn~PIN 5 istype 'com,invert'; PR ### # # # # # ### # ## ## # # # * # # # EL " bits 0:15 data buffer enable " bits 16:31 data buffer enable " pcc upper byte data buffer enable " pcc lower byte data buffer enable ##### # # # # # ###### # ##### # # ###### ##### # # # # # ## ## # # # # # # ## # # # # # # # # # ###### # #### # #### # # PccEvenEn~PIN 14 istype 'com,invert'; PccOddEn~PIN 37 istype 'com,invert'; PccR_W~PIN 62 istype 'com';" pcmcia data buffers direction "****************************************************************************** "* "* "* "* "* "* "* IM ##### # # # # FlashCfgEn~PIN 17; " flash configuration enable from control IN ## ## # ###### # # # # ## ## # MOTOROLA MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y * * * * * * #### 141 Support Information "****************************************************************************** "****************************************************************************** "* Reset & Interrupt Logic Pins. "****************************************************************************** RstDeb1NODE istype 'com'; AbrDeb1NODE istype 'com'; " reset push button debouncer " abort push button debouncer HardResetEnNODE istype 'com'; SoftResetEnNODE istype 'com'; " enables T.S. hard reset pin " enables T.S. soft reset pin ConfigHold2, ConfigHold1, ConfigHold0node istype 'reg,buffer';" supplies data hold time for " hard reset configuration ConfigHoldEndnode istype 'com'; "****************************************************************************** "****************************************************************************** SyncHardReset~NODE istype 'reg,buffer'; DSyncHardReset~ " synchronized hard reset NODE istype 'reg,buffer';" double synchronized hard reset SyncTEA~NODE istype 'reg,buffer'; HoldOffConsidered NODE istype 'reg,buffer';" data drive hold-off state PR ##### # #### # # # ## EL " enable D_FlashOe~NODE istype 'com'; " delayed flash output enable DD_FlashOe~NODE istype 'com';" double delayed flash output TD_FlashOe~NODE istype 'com';" triple delayed flash output " enable " QD_FlashOe~NODE istype 'com'; " PD_FlashOe~NODE istype 'com'; quad delayed penta delayed KeepPinsConnected node istype 'com'; "****************************************************************************** "* * # # #### # ##### # ## # # # ## # # ##### # * * "* # "* # 142 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IM "* data buffers enable. " needed since TEA~ is O.D. IN " machine. AR Y MOTOROLA Support Information "* # "* # "* # "* "* "* ###### "* # "* # "* # "* # "* # # # # # # ###### # ##### # # ###### #### # # # # # # # # # # # ###### ## # # # # ##### # # # # ##### # # # # # # # ## # # # # #### # # # # # # # # # ## # # # # # # # # * * * * * * * * * * * * * * * * * * * ## ## # ###### # # # # ## ## # ##### #### #### ###### # # # # ##### # # # # "* ###### "* "* "* "* "* "* "* ## # # # # #### ##### # # # # # # # # # # # #### # # # # # # # # # ## ## # # # # # # ###### # # # # ## ## # #### H, L, X, Z = 1, 0, .X., .Z.; C, D, U = .C., .D., .U.; "****************************************************************************** "* SLOW_32K_LOCK = 1; "****************************************************************************** "* Signal groups "****************************************************************************** PdaAdd = [A9,A10,A19,A20,A30]; DramAdd = [DramAdd10,DramAdd9]; DramCS~ =[DramBank2Cs~,DramBank1Cs~]; RAS = [Ras1~,Ras1DD~,Ras2~,Ras2DD~]; SD = [SizeDetect1,SizeDetect0]; FlashCsOut = [FlashCs4~,FlashCs3~,FlashCs2~,FlashCs1~]; Reset = [HardReset~,SoftReset~]; ResetEn = [HardResetEn,SoftResetEn]; Rst = [Rst1,Rst0]; Abr = [Abr1,Abr0]; Debounce = [RstDeb1,AbrDeb1]; DramCs = [DramBank2Cs~,DramBank1Cs~]; Cs = [ContRegCs~,FlashCs~ ,DramBank1Cs~,DramBank2Cs~]; PccCs = [PccCE1~,PccCE2~]; MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "****************************************************************************** IN AR Y 143 Support Information LocDataBufEn = [UpperHalfEn~,LowerHalfEn~]; PccDataBufEn = [PccEvenEn~,PccOddEn~]; ModuleEn = [DramEn~,FlashEn~,PccEn~,ContRegEn~]; SyncReset = [SyncHardReset~,DSyncHardReset~]; RstCause = [Rst1,Rst0,Abr1,Abr0,RegPORIn~]; Stp = [TA~]; Modck = [Modck2, Modck1]; ConfigHold =[ConfigHold2, ConfigHold1, ConfigHold0]; F_PD = [F_PD4, F_PD3, F_PD2, F_PD1]; "****************************************************************************** "* Dram Declarations. "****************************************************************************** DRAM_ENABLE_ACTIVE = 0; DRAM_ENABLED = (DramEn~ == DRAM_ENABLE_ACTIVE); SIMM36100 = (SD == 0); SIMM36200 = (SD == 3); SIMM36400 = (SD == 2); SIMM36800 = (SD == 1); IS_HALF_WORD = (HalfWord~ == 0); "****************************************************************************** "* Flash Declarations. "****************************************************************************** FLASH_ENABLE_ACTIVE = 0; FLASH_ENABLED = (FlashEn~ == FLASH_ENABLE_ACTIVE); MCM29020 = (F_PD == 8); MCM29040 = (F_PD == 7); MCM29080 = (F_PD == 6); SM732A1000A = (F_PD == 5); SM732A2000 = (F_PD == 4); FLASH_BANK1 = ( (MCM29020 # SM732A1000A) # (MCM29040 & !A10) # (MCM29080 & !A9 & !A10) # (SM732A2000 & !A9) ); FLASH_BANK2 = ( (MCM29040 & A10) # 144 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Support Information (MCM29080 & !A9 & A10) # (SM732A2000 & A9) ); FLASH_BANK3 = (A9 & !A10 & MCM29080); FLASH_BANK4 = (A9 & A10 & MCM29080); "****************************************************************************** "* Reset Declarations. "****************************************************************************** KEEP_ALIVE_PON_RESET_ACTIVE = 0; REGULAR_PON_RESET_ACTIVE = 0; HARD_RESET_ACTIVE = 0; SOFT_RESET_ACTIVE = 0; HARD_CONFIG_HOLD_VALUE = 4; DRIVE_MODCK_TO_PDA = (HardReset~ == HARD_RESET_ACTIVE);" have modck stable REGULAR_POWER_ON_RESET = (RegPORIn~ == REGULAR_PON_RESET_ACTIVE); HARD_RESET_ASSERTED = (SyncHardReset~.fb == HARD_RESET_ACTIVE); HARD_RESET_NEGATES = ( (SyncHardReset~.fb != HARD_RESET_ACTIVE ) & (DSyncHardReset~.fb == HARD_RESET_ACTIVE)); "****************************************************************************** "* data buffers enable. "****************************************************************************** BUFFER_DISABLED = 1; BUFFER_ENABLED = !BUFFER_DISABLED; CONTROL_REG_ENABLE_ACTIVE = 0; FLASH_CONFIG_ENABLED_ACTIVE = 0; PCMCIA_ENABLE_ACTIVE = 0; GPL_ACTIVE = 0; MOTOROLA PR " detecting hard reset negation MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM " during hard reset. IN AR Y 145 Support Information TEA_ASSERTS = (!TEA~ & SyncTEA~.fb);" first clock of TEA~ asserted CONTROL_REG_ENABLED = (ContRegEn~ == CONTROL_REG_ENABLE_ACTIVE); FLASH_CONFIGURATION_ENABLED = (FlashCfgEn~ == FLASH_CONFIG_ENABLED_ACTIVE); PCC_ENABLED = (PccEn~ == PCMCIA_ENABLE_ACTIVE); NO_HOLD_OFF = 0; HOLD_OFF_CONSIDERED = 1; STATE_HOLD_OFF_CONSIDERED = (HoldOffConsidered.fb == HOLD_OFF_CONSIDERED); STATE_NO_HOLD_OFF = (HoldOffConsidered.fb == NO_HOLD_OFF); END_OF_FLASH_READ = !TA~ & !FlashCs~ & R_W~;" end of flash read cycle. END_OF_OTHER_CYCLE = (!TA~ & FlashCs~ # " another access or !TA~ & !FlashCs~ & !R_W~); " flash write HOLD_OFF_PERIOD = (!R_W~ & !TD_FlashOe~.fb); "****************************************************************************** "* Equations, state diagrams. * "****************************************************************************** "* "* ####### "* # "* # * * # # # # # ## # # # # ##### # # # # # # # # # # # #### # # # # # # # # # ## ## # # # # # # #### # #### # # # * * * * * * * "* ##### "* # "* # PR #### # # # # # # # # # # # ## # EL ###### # # # # #### IM ## ## # #### #### "* HOLD_OFF_PERIOD = (!R_W~ & !PD_FlashOe~.fb); "* ####### "* ### # "****************************************************************************** "* Reset Logic "****************************************************************************** equations Reset.oe = ResetEn; 146 MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN MOTOROLA AR Y Support Information Reset = 0;" open drain RstDeb1 = !( Rst1 & (!( RstDeb1.fb & Rst0) ) ); " Reset push-button debouncer AbrDeb1 = !( Abr1 & (!( AbrDeb1.fb & Abr0) ) ); " Abort push-button debouncer HardResetEn = RstDeb1.fb & AbrDeb1.fb " both buttons are depressed; # REGULAR_POWER_ON_RESET; SoftResetEn = RstDeb1.fb & !AbrDeb1.fb;" only reset button depressed "****************************************************************************** "* Power On reset configuration "****************************************************************************** equations Modck.oe = ModckOe; ModckOe = DRIVE_MODCK_TO_PDA; Modck2 = L; @ifndef SLOW_32K_LOCK { Modck2 = ModIn;" support for 1:513 (32KHz crystal) or Modck1 = ModIn;" 1:5 (5MHz clock gen.) via CLK4IN } @ifdef SLOW_32K_LOCK { Modck2 = !ModIn;" support for 1:1 or 1:5 from CLK4IN only Modck1 = H;" no support for 32K oscillator. } "****************************************************************************** "* Hard reset configuration "****************************************************************************** equations ResetConfig~.oe = H; DriveConfig~.oe = H; MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 147 AR Y Support Information "* Configuration hold counter. Since the rise time of the HARD RESET signal "* is relatively slow, there is a need to provide a hold time for reset "* configuration. ConfigHold.clk = SYSCLK; when (SyncHardReset~.fb & !ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb +1; else when (SyncHardReset~.fb & ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb; else when (!SyncHardReset~.fb) then ConfigHold := 0; ConfigHoldEnd = (ConfigHold.fb == HARD_CONFIG_HOLD_VALUE); " terminal count !ResetConfig~ = !HardReset~;" drives RSTCONF~ to MPC8XX !DriveConfig~ = !ConfigHoldEnd.fb; " drives configuration data on the bus. "****************************************************************************** "* NMI generation "****************************************************************************** NMI~.oe = NMIEn; NMI~ = 0;" O.D. NMIEn = !RstDeb1.fb & AbrDeb1.fb;" only abort button depressed "****************************************************************************** "* local data buffers enable "****************************************************************************** equations SyncHardReset~.clk = SYSCLK; DSyncHardReset~.clk = SYSCLK; SyncHardReset~ := HardReset~; DSyncHardReset~ := SyncHardReset~.fb; SyncTEA~.clk = SYSCLK; SyncTEA~ := TEA~; LocDataBufEn.oe = 3; 148 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA equations IN AR Y Support Information !UpperHalfEn~ = (!DramBank1Cs~ & DRAM_ENABLED # !DramBank2Cs~ & (SIMM36200 # SIMM36800) & DRAM_ENABLED # !FlashCs~ & FLASH_ENABLED # !ContRegCs~ & CONTROL_REG_ENABLED # !PccCE1~ & PCC_ENABLED # !PccCE2~ & PCC_ENABLED # !ConfigHoldEnd.fb) & (STATE_HOLD_OFF_CONSIDERED & (!HOLD_OFF_PERIOD) # STATE_NO_HOLD_OFF); !LowerHalfEn~ = (!DramBank1Cs~ & DRAM_ENABLED & !IS_HALF_WORD # !DramBank2Cs~ & (SIMM36200 # SIMM36800) & !IS_HALF_WORD & DRAM_ENABLED # !FlashCs~ & FLASH_ENABLED # !ConfigHoldEnd.fb & FLASH_CONFIGURATION_ENABLED) & (STATE_HOLD_OFF_CONSIDERED & !HOLD_OFF_PERIOD # STATE_NO_HOLD_OFF); "****************************************************************************** "****************************************************************************** equations HoldOffConsidered.clk = SYSCLK; D_FlashOe~ = FlashOe~; DD_FlashOe~ = D_FlashOe~.fb; TD_FlashOe~ = DD_FlashOe~.fb; "* QD_FlashOe~ = TD_FlashOe~.fb; "* PD_FlashOe~ = QD_FlashOe~.fb; @ifdef DEBUG { equations HoldOffConsidered := HOLD_OFF_CONSIDERED; } @ifndef DEBUG { state_diagram HoldOffConsidered state NO_HOLD_OFF: MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* local data buffers disable (data contention protection) IN AR Y 149 Support Information if (END_OF_FLASH_READ & DSyncHardReset~.fb) then HOLD_OFF_CONSIDERED else NO_HOLD_OFF; state HOLD_OFF_CONSIDERED: if (END_OF_OTHER_CYCLE # !DSyncHardReset~.fb) then NO_HOLD_OFF else HOLD_OFF_CONSIDERED; } "****************************************************************************** "* pcc data buffers enable "****************************************************************************** equations PccDataBufEn.oe = 3; (STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD # STATE_NO_HOLD_OFF); !PccOddEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED & (STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD # STATE_NO_HOLD_OFF); "****************************************************************************** "* pcc data buffers direction "****************************************************************************** equations PccR_W~.oe = H; PccR_W~ = R_W~; "****************************************************************************** "* Dram Address lines. "* These lines are conencted to the dram high order address lines A9 and A10 "* (if available). These lines change value according to the dram size and "* port size. "* The dram size is encoded from the presence detect lines (see definitions "* above) and the port size is determined by the control register. 150 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM !PccEvenEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED & IN AR Y MOTOROLA Support Information "****************************************************************************** equations DramAdd.oe = 3; when (!IS_HALF_WORD # IS_HALF_WORD & (SIMM36400 # SIMM36800)) then DramAdd9 = A20; else DramAdd9 = A30; when ( (SIMM36400 # SIMM36800) & !IS_HALF_WORD) then DramAdd10 = A19; else when ( (SIMM36400 # SIMM36800) & IS_HALF_WORD) then DramAdd10 = A30; else DramAdd10 = 0; "****************************************************************************** "* RAS generation. "* load and to allow 16 bit operation. When working with 16 bit port size, "* the double drive RAS signals are disabled. "****************************************************************************** equations RAS.oe = ^hf; !Ras1~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ENABLED; !Ras2~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ENABLED & (SIMM36200 # SIMM36800); !Ras1DD~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ENABLED; !Ras2DD~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ENABLED & (SIMM36200 # SIMM36800); "****************************************************************************** "* Flash Chip Select "****************************************************************************** equations FlashCsOut.oe = ^hf; !FlashCs1~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK1; !FlashCs2~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK2 ; MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM "* Since the dram simm requires RAS signals to be split due to high capacitive IN AR Y 151 Support Information !FlashCs3~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK3 ; !FlashCs4~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK4 ; FlashOe~.oe = H; !FlashOe~ = FLASH_ENABLED & R_W~; "****************************************************************************** "* Auxiliary functions "****************************************************************************** equations KeepPinsConnected = TA~ ; end brdctl12 "****************************************************************************** 152 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Support Information APPENDIX B - ADI I/F The ADI parallel port supplies parallel link from the MPC8XXFADS to various host computers. This port is connected via a 37 line cable to a special board called ADI (Application Development Interface) installed in the host computer. Four versions of the ADI board are available to support connection to IBM-PC/XT/AT, MAC II, VMEbus computers and SUN-4 SPARC stations. It is possible to connect the MPC281ADS board to these computers provided that the appropriate software drivers are installed on them. Each MPC281ADS can have 8 possible slave addresses set for its ADI port, enabling up to 8 MPC281ADS boards to be connected to the same ADI board. FIGURE A-1 ADI Port Connector Gnd Gnd Gnd Gnd Gnd Gnd (+ 12 v) N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ Gnd Gnd Gnd PD0 PD2 PD4 PD6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC281ADS. B*1 The ADI port on the MPC281ADS was slightly modified to generate either hard reset or soft reset. This feature was added to comply with the MPC's reset mechanism. In the list below, the directions 'I', 'O', and 'I/O' are relative to the MPC8XXFADS board. (I.E. 'I' means input to the MPC8XXFADS) MOTOROLA PR * ADI Port Signal Description NOTE: Since the ADI was originated for the DSP56001ADS some of its signals throughout the boards it was used with, were designated with the prefix "ADS". This convention is kept with this design also. ADS_SEL(0:2) - 'I' MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL N.C. D_C~ HST_ACK ADS_SRESET ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK N.C. N.C. N.C. N.C. PD1 PD3 PD5 PD7 IM IN AR Y The ADI port connector is a 37 pin, male, D type connector. The connection between the MPC281ADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE A-1 below shows the pin configuration of the connector. 153 Support Information These three input lines determine the slave address of the MPC8XXFADS being accessed by the host computer. Up to 8 boards can be addressed by one ADI board. * ADS_SRESET - 'I' This input line is used to generate Soft Reset for the MPC. When an ads is selected and this line is asserted by the host computer, Soft Reset will be generated to the MPC along with the Soft Reset configuration applied during that sequence. * HOST_ENABLE~ - 'I' This line is always driven low by the ADI board. When an ADI is connected to the MPC8XXFADS, this signals enabled the operation of the debug port controller. Otherwise the debug port controller is disabled and its outputs are tri-stated. * ADS_HRESET - 'I' When a host is connected, this line is used in conjunction with the addressing lines to generate a Hard Reset to the MPC8XXFADS board. When this signal is driven in conjunction with the ADS_SRESET signal, the ADI I/F state machines and registers are reset. * HOST_REQ -'I' This signal initiates a host to MPC8XXFADS write cycle. * ADS_ACK - 'O' This signal is the MPC8XXFADS response to the HOST_REQ signal, indicating that the board has detected the assertion of HOST_REQ. * ADS_REQ - 'O' This signal initiates an MPC8XXFADS to host write cycle. * HST_ACK - 'I' This signal serves as the host's response to the ADS_REQ signal. * HOST_VCC - 'I' (three lines) These lines are power lines from the host computer. In the MPC8XXFADS, these lines are used by the hardware to determine if the host computer is powered on. * PD(0:7) - 'I/O' These eight I/O lines are the parallel data bus. This bus is used to transmit and receive data from the host computer. 154 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN AR Y MOTOROLA Support Information APPENDIX C - ADI Installation C*1 INTRODUCTION This appendix describes the hardware installation of the ADI board into various host computers. The installation instructions cover the following host computers: 1) 2) IBM-PC/XT/AT SUN - 4 (SBus interface) C*2 IBM-PC/XT/AT to MPC8XXFADS Interface C*2*1 MOTOROLA PR Refer to the appropriate Installation and Setup manual of the IBM-PC/XT/AT computer for instructions on removing the computer cover. The ADI board address block should be configured at a free I/O address space in the computer. The address must be unique and it must not fall within the address range of another card installed in the computer. The ADI board address block can be configured to start at one of the three following addresses: * $100 - This address is unassigned in the IBM-PC * $200 - This address is usually used for the game port * $300 - This address is defined as a prototype port The ADI board is factory configured for address decoding at 100-102 hex in the IBM-PC/XT/AT I/O address map. These are undefined peripheral addresses. MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE IBM-PC/XT/AT COMPUTER, TURN THE POWER OFF AND REMOVE THE POWER CORD. ADI Installation in IBM-PC/XT/AT AR Y The ADI board should be installed in one of the IBM-PC/XT/AT motherboard system expansion slots. A single ADI can control up to eight MPC8XXFADS boards. The ADI address in the computer is configured to be at I/O memory addresses 100-102 (hex), but it may be reconfigured for an alternate address space. 155 Support Information FIGURE A-1 Physical Location of jumper JG1 and JG2 JG1 JG2 NOTE: Jumper JG2 should be left unconnected. FIGURE A-2 JG1 Configuration Options To properly install the ADI board, position its front bottom corner in the plastic card guide channel at the front of the IBM-PC/XT/AT chassis. Keeping the top of the ADI board level and any ribbon cables out of the way, lower the board until its connectors are aligned with the computer expansion slot connectors. Using evenly distributed pressure, press the ADI board straight down until it seats in the expansion slot. Secure the ADI board to the computer chassis using the bracket retaining screw. Refer to the computer Installation and Setup manual for instructions on reinstalling the computer cover. C*3 The ADI board should be installed in one of the SBus expansion slots in the Sun-4 SPARCstation computer. A single ADI can control up to eight MPC8XXFADS boards. 156 PR 0 hex EL IM 100 hex The following figure shows the required jumper connection for each address configuration. Address 0 hex is not recommended, and its usage might cause problems. IN 200 hex SUN-4 to MPC8XXFADS Interface MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y 300 hex MOTOROLA Support Information C*3*1 CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE SUN-4 COMPUTER, TURN THE POWER OFF AND REMOVE THE POWER CORD. ADI Installation in the SUN-4 FIGURE A-3 ADI board for SBus Following is a summary of the Instructions in the Sun manual: 1. Turn off power to the system, but keep the power cord plugged in. Be sure to save all open files and then the following steps should shut down your system: * hostname% /bin/su * Password: mypasswd * hostname# /usr/etc/halt * wait for the following messages. Syncing file systems... done Halted Program Terminated Type b(boot), c(continue), n(new command mode) * When these messages appear, you can safely turn off the power to the system unit. 2. Open the system unit. Be sure to attach a grounding strap to your wrist and to the metal casing of the power supply. Follow the instructions supplied with your system to gain access to the SBus slots. 3. Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel of the system unit. Note that the ADI board is a slave only board and thus will function in any available SBus slot. 4. Slide the ADI board at an angle into the back panel of the system unit. Make sure that the mounting plate on the ADI board hooks into the holes on the back panel of the system unit. MOTOROLA PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 157 ADI Connector AR Y SBus Connector There are no jumper options on the ADI board for the Sun-4 computer. The ADI board can be inserted into any available SBus expansion slot on the motherboard. Refer to the appropriate Installation and Setup manual for the Sun-4 computer for instructions on removing the computer cover and installing the board in an expansion slot. Support Information 5. Push the ADI board against the back panel and align the connector with its mate and gently press the corners of the board to seat the connector firmly. 6. Close the system unit. 7. Connect the 37 pin interface flat cable to the ADI board and secure. 8. Turn power on to the system unit and check for proper operation. 158 PR MPC8XXFADS Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y 10/97 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. General Information 1 - General Information 1*1 Introduction This document is the operation guide for the MPC8XXFADS Daughter Board for the MPC860Tnamed the MPC860TFADSDB. The daughter board holds the evaluated MPC860T along with some necessary logic, which is required to be in the nearest vicinity of the MPC860T as well as peripherals, that are dedicated to the MPC860T and are not required for any other member of the MPC8XX family. The daughter board has 2 sets of matching connectors - on the printA side and on the componentB side. Those on the print side, connect to a matching set found on the MPC8XXFADS while those on the component side, are to serve hardware expansion via a dedicated adaptor. In addition, a set of logic analyzer connector is featured matching the new high density HP16500 logic analyzer adaptors, this to provide fast connection to logic analyzer while saving on board's space and reducing EMI. 1*2 * * * * * * * * * * Abbreviations' List 1*3 * * * * Related Documentation MPC860T User's Manual. ADI Board Specification. MPC8XXFADS Engineering Specification Level One's LXT970 Data Sheet. May be obtained from http://www.level1/ds/970.html A. Board's bottom. B. Board's top. C. Not to be mistaken for the M683XX Family Ads MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 1 PR EL FADSC - the MPC8XXFADS, to which this board connects. UPM - User Programmable Machine GPCM - General Purpose Chip-select Machine GPL - General Purpose Line (associated with the UPM) DB - Daughter Board the MPC860TFADSDB, the subject of this document. MPC860T - MPC860 + Fast Ethernet Controller. BSCR - Board Control & Status Register. ZIF - Zero Input Force BGA - Ball Grid Array Spec - engineering Specification Document. IM IN AR Y General Information 1*4 SPECIFICATIONS TABLE 1-1. 860TFADSBD Specifications CHARACTERISTICS SPECIFICATIONS MPC860T @ 50 MHz 0OC - 30OC -25OC to 85OC 5% to 90% (non-condensing) 5.87" (149 mm) 4.37" (111 mm) 0.063" (1.6 mm) The MPC860TFADSDB specifications are given in TABLE 1-1. Microprocessor Operating temperature Storage temperature Relative humidity Dimensions: Length Width Thickness 1*5 MPC860T-FADSDB Features t t MPC860T running upto 50 MHz On-Board Fast Ethernet Level One LXT970, with shutdown option over Twisted pair (Ethernet 100Base TX). 5 Dip Switches for the LXT970 power up configuration. Option, for Fast Ethernet over Fiber Optics (Ethernet 100Base FX). Selectable KAPWR source: 3.3V or externally supplied Selectable VDDL source: 3.3V or 2V Selectable clock source: 32768Hz crystal resonator or 4A MHz Clock generator. On-Board Expansion connectors, including all MPC pins and MPC8XXFADS control / status signals. On-Board High Density Logic Analyzer connectors, supporting fast connection to HP 16500 logic analyzer (AMP Mictor). t t t t t t A. May be easily changed to any 3.3V powered oscillator oscillating in 3 - 5 MHz frequency range. 2 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA PR t EL IM IN AR Y General Information FIGURE 1-1 MPC860T-FADSDB Block Diagram Logic Analyzer Conn. MOTHER BOARD & EXPANSION CONN. LXT970 Fast Ethernet Transceiver MOTOROLA PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN CLOCKS Option Optical Tranceiver AR Y MPC860T RJ45 Connector 3 Hardware Preparation and Installation 2 - Hardware Preparation and Installation 2*1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MPC860TFADSDB. 2*2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier's agent to be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment. CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY; STATIC DISCHARGE CAN DAMAGE CIRCUITS. 2*3 HARDWARE PREPARATION 4 PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL To select the desired configuration and ensure proper operation of the MPC860TFADSDB board, changes of the jumpers settings may be required before installation. The location of the switches, LEDs, and connectors is illustrated in FIGURE 2-1 "MPC860TFADSDB Top Side Part Location diagram" on page 5. The board has been factory tested and is shipped with Dip-Switch settings as described in the following paragraphs. Parameters can be changed for the following conditions: * Clock generator. * Power-On Reset Source. * MPC Keep Alive Power Source * MPC Internal Logic Supply Source * LXT970 power up configuration. IM IN AR Y MOTOROLA Hardware Preparation and Installation FIGURE 2-1 MPC860TFADSDB Top Side Part Location diagram IM 2*3*1 Clock Generator Replacement - U1 MOTOROLA PR 1) 2) When replacing U1 with another clock generator it should be noticed that there are 2 supply level available at U1: 5V supply at pin 14. 3.3V supply available at pin 11. MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IN HALO 5 AR Y Hardware Preparation and Installation FIGURE 2-2 U1 Power Sources 1 14 5V 11 3.3V GND 7 U1 8 WARNING As there are differences between MPC revisions regarding the functionality of the Power-On Reset logic, it is therefore necessary to select different sources for Power-ON reset generation. J1 on the MPC860TFADSDB is used to select Power-On Reset source: when a jumper is placed between positions 1 - 2 of J1, Power-On reset to the MPC is generated by the Keep-Alive power rail. I.e., When KAPWR goes below 2.005V - Power-On reset is generated. When a jumper is place between position 2 - 3 of J1, Power-On reset to the MPC is generated from the MAIN 3.3V power rail. I.e, when the MAIN 3.3V power rail goes below 2.805V Power-On reset is generated. 6 PR 2*3*2 Power-On Reset Source Selection MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Since the MPC clock input is NOT 5V TOLERANT, any clock generator inserted to U1, MUST HAVE 3.3V compatible output. If a 5V output clock generator is inserted to U1, PERMANENT DAMAGE might be inflicted to the MPC. IM IF A 14 Pin Form-Factor, 3.3V Clock Generator is inserted to U1, PERMANENT DAMAGE Might Be Inflicted To The Device. WARNING IN From looking at FIGURE 2-2 "U1 Power Sources" above, we see that 5V (with 3.3V output only!) oscillator may be used with 14 pins only form-factor while 3.3V oscillators may be used with 8 pins only form-factor. AR Y MOTOROLA Hardware Preparation and Installation FIGURE 2-3 Power-On Reset Source Selection J1 1 1 J1 KA Power Rail 2*3*3 VDDL Source Selection MAIN Power Rail J3 serves as a selector for VDDL - MPC internal logic supply. When a jumper is placed between positions 1 - 2 of J3, VDDL is supplied with 3.3V. When a jumper is placed between positions 2 - 3 of J3, VDDL is supplied by 2V power source. The jumper on J3 is factory set between positions 1 - 2 to supply 3.3 to VDDL. J3 1 EL VDDL - 3.3V 2*3*4 Keep Alive Power Source Selection A. E.g., a battery. MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 7 PR J2 selects the Keep Alive power source of the MPC. When a jumper is placed between positions 1 2 of J2, the Keep Alive power is fed from the main 3.3V bus. When an external power sourceA is to be connected to the Keep Alive power rail, it should be connected between positions 2 (the positive pole) and position 3 (GND) of J2. IM VDDL - 2V IN J3 1 FIGURE 2-4 VDDL Source Selection AR Y Hardware Preparation and Installation FIGURE 2-5 Keep Alive Power Source Selection J2 3.3V KAPWR GND KAPWR From 3.3V J2 3.3V 1 1 + Ext. Power Supply KAPWR GND KAPWR From Ext. Power Supply 2*3*5 LXT970 Power Up HW Configuration MF0 MF1 MF2 MF3 DS1 Default Configuration. 2*4 The MPC860TFADSDB should be plugged into the MPC8XXFADS Mother Board. This should be done when the FADS is disconnected from any power supply. The 860TDB should be placed over the mother board connectors in a way that the mother board connectors of the 860TDB, PM1 - PM4 match the daughter connectors of the FADS and than pressed gently into position. The connectors are arranged in a non symmetrical form, so miss-insertion is inhibited. 8 PR INSTALLATION INSTRUCTIONS MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL ON 1 2 IM 3 4 IN MF4 5 The LXT970 can be configure for power up by 9 pins 5 of them are connected to the LXT970 through DS1 (DS1 is a 16 pin contain 8 dip switches) they are the HW configuration pins. The pins MF0 - MF4 can configure the following options: MF0 enables the autonegotiation, if DS1(1) is OFF it enable the autonegotiation MF1 selects DTE or Repeater, if DS1(2) is ON it enable the DTE mode. MF2 selects symbol (5B) or Nibble (4B) if DS1(3) is ON Nibble (4B) is selected. MF3 enables scrambler operation, if DS1(4) is ON the scrambler operation is enabled. MF4 select the output possibility options, twisted pair or the fiber optic. AR Y 6 7 8 MOTOROLA OPERATING INSTRUCTIONS 3 - OPERATING INSTRUCTIONS 3*1 3*2 3*2*1 INTRODUCTION CONTROLS AND INDICATORS GND Bridges This chapter provides necessary information to use the MPC860TFADSDB The MPC860TFADSDB has in addition to the switches a few indicators - described below:. There are 4 GND bridges on the MPC860TFADSDB. They are meant to assist general measurements and logic-analyzer connection. Warning The GND bridges on board, physically resemble J4. Do not mistake J4 to be a GND jumper, otherwise, permanent damage might be inflicted to the MPC860TFADSDB and or to the MPC8XXFADS. When connecting to a GND bridge, use only INSULATED GND clips. Failure in doing so, might result in permanent damage to the MPC860TFADSDB. 3*2*2 3*2*3 3*2*4 3*2*5 3.3V Indicator - LD1 Receive Led - LD2 The yellow 3.3V led LD1 indicates that the 3.3V power bus is powered from the MPC8XXFADS. When the yellow LD4 is light, the fast ethernet receive is in process, for 10M or for 100M. Transmit Led - LD3 Link Led - LD4 When the yellow LD5 is light, the fast ethernet transmit is in process, for 10M or for 100M. When the yellow LD6 is light, during the 100Mbps operation indicates scrambler lock and receipt of valid idle codes. During 10Mbps operation, indicates link valid status. 3*2*6 When the yellow LD7 is light, in the default mode it indicates a collision. However this led is a programmable led and it can indicate other definitions. For a programing options see configuration register, register 19 in the LXT970 user guide. 3*2*7 When the Speed Led is light it indicates that the LXT970 operate in 100Mbps. When this led is off and the led on indication is on so the ethernet speed is 10M. Note the 10M ethernet means 10M operating through the MII bus. 3*2*8 When the yellow Fast - Ethernet-ON indicator led LD2 is lit, it designates that the LXT970 transceiver is enabled for the Fast - Ethernet operation. When it is darkened, the LXT970 is tri-stated and the MII pins output from the LXT970 are in three-state. these pins with the input to the LXT970 pins may be used for any alternate function. See also TABLE 4-23. "BCSR4 Description" on page 57 of the MPC8XXFADS User's Manual. MOTOROLA PR Collision Led - LD5 Speed Led- LD6 Fast - Ethernet - On Indicator - LD7 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN Warning AR Y 9 OPERATING INSTRUCTIONS 3*3 MEMORY MAP The memory map is identical to all daughter boards, therefore described in the MPC8XXFADS User's Manual - section 3*3 "MEMORY MAP" on page 16. 3*4 MPC Registers' Programming See 3*4 "MPC Registers' Programming" on page 10 of the MPC8XXFADS User's Manual. 10 PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Functional Description 4 - Functional Description In this chapter the various modules combining the MPC860TFADSDB are described to their design details. 4*1 Reset & Reset - Configuration 1) Power-On ResetA 2) Hard Reset 3) Soft Reset There are 3 reset sources for the MPC: 4*1*1 1) 2) Power-On Reset The keep alive power bus The MAIN power bus. The Power - On Reset on the MPC860T-FADSB is generated out of 2 alternative power buses: Selection between the 2 options is done by means of jumper. When PORESET* is asserted to the MPC, the Power-On reset configuration is made available to MPC. See 4*1*6*1 "Power - On Reset Configuration" on page 29 of MPC8XXFADS User's Manual. 4*1*2 1) 2) 3) 4) Hard Reset When the open-drain signal Hard Reset is asserted, Hard reset configuration is driven on the data bus by logic on the motherboard. See 4*1*6*2 "Hard Reset Configuration" on page 29 on MPC8XXFADS User's Manual. 4*1*3 1) 2) Soft Reset is generated to the MPC860T by the following sources: The debug port controller located on the motherboard Manual Soft Reset generated on the motherboard A. In fact generated on the daughter board. MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 11 PR Soft Reset Hard Reset is generated to the MPC860T by the following sources: The MAIN power-on reset Manual Hard Reset generated on the mother board The debug port Hard reset and by MPC860T's internal sources. EL When option (2) above is selected, the power-on reset is generated by a dedicated voltage detector made by Seiko the S-8052ANY-NH-X with detection voltage range of 2.595V to 2.805V. During MAIN 3.3V bus power-on or when there is a voltage drop of that input into the above range Power-On Reset is generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec. The MAIN power on reset also generates power-on reset to all logic located on the motherboard. IM IN When option (1) above is selected, the power-on reset is generated by a dedicated voltage detector made by Seiko the S-8051HN-CD-X with detection voltage range of 1.795 to 2.005V. During keep alive power-on or when there is a voltage drop of that input into the above range Power-On Reset is generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec. AR Y Functional Description 3) and by MPC860T internal sources. When Soft reset is generated to the MPC860T, Soft Reset configuration is made available to the MPC by logic residing over the motherboard. See 4*1*6*3 "Soft Reset Configuration" on page 29 on MPC8XXFADS User's Manual. 4*2 Interrupts Two external interrupts are applied to the MPC via its interrupt controller the ABORT (NMI), which is generated by a push-button & logic residing over the motherboard, and the other on is the IRQ2 which is the interrupt of the LXT970 Fast Ethernet Tranceiver. Although most of clock generator logic is found on this board, it is documented within the motherboard User's Manual, since, it is common to all daughter boards. See 4*3 "Clock Generator" on page 30 of the MPC8XXFADS User's Manual. 4*4 Fast Ethernet Support TABLE 4-1. MF0 - MF4 Function Description Pins EL FUNCTION Auto-negotiation Repiter/DTE mode Nibble 4B/Symbol 5B Scrambler Operation Select TX or FX The 860TDB has on-board full support for 802.3 Media Independent Interface (MII), made by the Level One LXT970 device, the connection between the LXT970 and the line can be made by twisted pair RJ45 connector or by fiber optic connector which is an optional only. The LXT970 used in the 860TDB has the following features: it is a IEEE 802.3 Compatible which is a 10BASE-T and 100BASE-TX using a single RJ45 connector. It support an auto-negotiation via Fast Link Pulse (FLP) exchange and parallel detection for legacy 10BASE-T and 100BASE-TX systems. MII interface, 100BASE-FX fiber optic capable, configurable through the MII serial port, it can be DTE repeater or switch application. The LXT970 has several control pins that can configure the mode of operation these pins are separated to two pins groups the WH control pins and the SW control pins, the HW control pins are the MF(0:4) connected to the DS1, the SW control pins are the TRSTE, FDE and CFG(0:1) which are controlled via the BCSR4 register. The following tables illustrate the LXT970 configuration options. IM Disable DTE Enable 100TX PR PIN NAME DS1 ON CONDITION IN MF0 MF1 MF2 MF3 MF4 Nibble 4B The following table describe the SW control pins controlled via the BCSR4 register which is on the mother board 12 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y DS1 OFF CONDITION Enable Repeater Symbol 5B Disable 100FX 4*3 Clock Generator Default Enable DTE Nibble 4B Enable 100TX MOTOROLA Functional Description TABLE 4-2. BCSR4 The control pins for the LXT970 BIT 4 MNEMONIC UUFEN~ FUNCTION When this signal is active (LOW) it enable the LXT970 device. This signal connected to the TRSTE signal of the LXT970. In DTE mode when this pin is high the LXT970 isolate it self from the MII data interface. In repeater mode when it is high the LXT970 tree state the MII output pins. Fast Ethernet CFG0 signal When the LXT970 is in auto negotiation a low to high transition in this pin cause an auto negotiate to re-start. When auto negotiation is disabled this input selects operating speed bit 0.13 When this pin is high the 100Mbps is selected 0.13 = 1. When this pin is low the 10Mbps is selected 0.13 = 0. Full Duplex Enable when auto negotiation is enable the FDE pin of the LXT970 determine full duplex advertisement capability in combination with MF4 and CFG1. See the LXT970 documentation. When auto negotiation is disable the FDE pin of the LXT970 effects full duplex and determines the value of bit 0.8 Duplex Mode. When this pin is high Full Duplex in Enable. 0.8 = 1. When this pin is low Full Duplex is Disable 0.8 = 0. PON DEF 1 ATT. R,W AR Y 1 1 1 1 5 FETHCFG0 R,W 6 FETHFDE R,W IN 10 FETHRST~ Fast Ethernet Reset. When this pin active (LOW) signal is being asserted the Fast ethernet tranceiver is being reset. EL IM 9 FETHCFG1 Fast Ethernet CFG1 signal When the LXT970 is in auto negotiation this pin determines operating speed advertisement capability in combination with MF4. see See the LXT970 documentation. When auto negotiation is disabled this input enables 10Mbps link test function and directly affects bit 19.8. When this pin is high, 10Mbps link test is disabled 19.8 = 1. When this pin is low, 10Mbps link test is enabled 19.8 = 0. R,W R,W The Fast Ethernet transceiver support two physical interfaces: t t . 4*5 Most BCSR control signals and some of BCSR's status signals are available on the motherboard connectors and on the expansion connectors. The BCSR control most of the functions available on the MPC860TDB and on the MPC8XXFADS. See 4*11 "Board Control & Status Register - BCSR" on page 45 of MPC8XXFADS User's Manual. MOTOROLA PR RJ45 8pin connector for the twisted pair use this connector is mounted on the board. Fiber Optic multi mode tranceiver not mounted on the board, it is an optional. The board design for the HP HFBR-5103 or HFBR-5105. Board Control & Status Register - BCSR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 13 Support Information 5 - Support Information In this chapter all information needed for support, maintenance and connectivity to the MPC860TFADSDB is provided. 5*1 1) 2) 3) 4) 5) 6) Interconnect Signals P1, P2, P3, P4, P5, P6 and P8 - Logic Analyzer connectors P9 RJ45 connector for the Fast Ethernet. PM1, PM2, PM3 and PM4 - Mother Board Connectors PX1, PX2, PX3 & PX4 - Expansion Connectors U3 Fiber Optic Tranceiver (Connector not mounted on the board). The MPC860TFADSDB interconnects with external devices via the following set of connectors: MPC8XXFADS's P8 - Serial Ports' Expansion ConnectorA 5*1*1 P1, P2, P3, P4, P5, P6 and P8 - Logic Analyzer Connectors A. This connector is located on the Mother Board. It is documented here since its contents depends on the Daughter Board. 14 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA PR EL IM IN These connectors are 38 pin, receptacle MICTOR connectors made by AMP. Each connector connects to a dedicated adaptor for HP 16500 series of logic analyzer, which interconnects to two 16 bit pods Since all the signals that appear on these connectors appear also on the mother-board connectors and on the expansion connectors, they are described there. AR Y Support Information TABLE 5-1 P1 Interconnect Signals Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 N.C. GND TS~ TS~ F_CS~ BCSRCS~ DRMCS1~ DRMCS2~ SDRMCS~ CS5~ CS6~ CS7~ N.C. R_W~ Signal Name Pin # 2 4 6 8 10 12 14 16 18 20 22 24 N.C. N.C. TA~ TA~ Signal Name IM REG_A~ TSIZE1 EL BURST~ TEA~ SPKROUT PR Pin # 1 3 5 7 9 11 13 15 17 19 TABLE 5-1 P2 - Interconnect Signals Signal Name N.C. GND NC ALE_A CE1A~ CE2A~ BWAITA~ BB~ BR~ BWP MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN VF0 VF1 26 28 30 32 34 36 38 VF2 WAIT_B~ RESETA POE_A~ MODCK1 MODCK2 EXTCLK Pin # 2 4 6 8 10 12 14 16 18 20 N.C. N.C. AR Y VFLS0 VFLS1 AT0 AT1 AT2 AT3 Signal Name BSWE0~ BSWE0~ BSWE1~ BSWE2~ BSWE3~ WE0~ WE1~ WE2~ 15 Support Information TABLE 5-1 P2 - Interconnect Signals Pin # 21 23 25 27 29 31 33 35 37 Signal Name BCD2~ BCD1~ BG~ BI~ BRDY BADDR28 BADDR29 BADDR30 AS~ Pin # 22 24 26 28 30 32 34 36 38 Signal Name WE3~ DRM_W~ EDOOE~ GPL2~ GPL3~ TABLE 5-2. P3 - Interconnect Signals 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 N.C. GND TEA~ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 IM EL PR 16 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 2 N.C. 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # Signal Name Pin # AR Y GPL4B~ GPL5A~ GPL5B~ GPL4A~ Signal Name MOTOROLA Support Information TABLE 5-3. P5 - Interconnect Signals Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 N.C. GND MIITCLK UUFEN~ FETHFDE FETHCFG1 FETHCFG0 FETHRST~ BVS1 BVS2 BBVD1 BBVD2 RSTCNF~ TEXP Signal Name Pin # 2 4 6 8 10 12 14 16 18 20 22 24 N.C. Signal Name DSDI IM HRESET~ SRESET~ PORST~ EL R_PORI~ MIITCLK PR Pin # 1 3 5 7 9 11 13 15 17 19 TABLE 5-4. P6 - Interconnect Signals Signal Name N.C. GND N.C. PB14 PB15 PB16 PB17 PB18 E_TENA RSRXD2 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 26 FRZ 28 30 32 34 36 38 DP0 DP1 DP2 DP3 V3.3 Pin # 2 4 6 8 10 12 14 16 18 20 N.C. N.C. AR Y DSCK DSDO TMS TRST~ NMI~ IRQ1~ IRQ2~ IRQ3~ BINPAK~ Signal Name SYSCLK SYSCLK PB30 PB31 PC4 PC5 PC6 PC7 17 Support Information TABLE 5-4. P6 - Interconnect Signals Pin # 21 23 25 27 29 31 33 35 37 Signal Name RSTXD2 RSDTR2~ RSDTR1~ RSRXD1 RSTXD1 PB26 PB27 PB28 PB29 Pin # 22 24 26 28 30 32 34 36 38 PC8 PC9 Signal Name E_RENA E_CLSN PC12 TABLE 5-5. P4 - Interconnect Signals 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 N.C. GND N.C. PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 IRDTXD IRDRXD ETHTX ETHRXS IM EL PR 18 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN 2 N.C. 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Pin # Signal Name Pin # AR Y PC14 MIICOL N.C. PC13. Signal Name MIIRXCLK MIIRXD3 MIIRXD2 MIIRXD1 MIIMDC MIITXER MIIRXD0 MIITXD0 MIIRXCLK MIIRXER MIIRXDV MIITXD3 MIITXD2 MIITXD1 MIICRS MIIMDIO MIITXEN MOTOROLA Support Information TABLE 5-6. P8 - Interconnect Signals Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 N.C. GND N.C. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Signal Name Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 N.C. N.C. N.C. D16 D17 Signal Name IM Pin No. 1 2 3 4 5 6 TPOTPO+ TPI+ TPI- EL 5*1*2 P9 & U3 - Fast Ethernet Connector The 823FADSDB supports both types of connectors for fast ethernet RJ45 (P3) and fiber optic tranceiver (it is not mounted on the board) U3. The signals of P9 are described in TABLE 5-7. "P9 Interconnect Signal" below: PR TABLE 5-7. P9 Interconnect Signal Signal Name COMMON_O COMMON_O MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE IN D24 D25 D26 D27 D28 D29 D30 D31 AR Y D19 D20 D21 D22 D23 D18 19 Support Information TABLE 5-7. P9 Interconnect Signal Pin No. 7 8 Signal Name COMMON_I COMMON_I 5*1*3 P7 - LCD Panel Connector Interconnect Signals TABLE 5-8. P7 Interconnect Signals Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LOE GND HSYNC GND VSYNC GND I/O - Signal Name SHIFT_C GND Attribute I/O LCD Shift Clock. PR LD0 GND LD1 GND LD2 GND LD3 GND LD4 GND 20 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL . I/O I/O I/O I/O I/O I/O - I/O IM Output Enable for TFT displays or Passive panels LCD_AC~ signal. Display Line beginning mark. New Frame beginning mark. LCD Data Line 0. LCD Data Line 1. LCD Data Line 2. LCD Data Line 3. LCD Data Line 4. IN MOTOROLA AR Y Description The LCD Panel connector is a 40 pin (2 X 20) header connector, which is compatible with the LCD panel connector, existed on the MPC821ADS To allow convenient migration for MPC821 users, the signal are assigned in a way that allows for panels that were connected to the MPC821ADS, to be connected directly. The signals of P7 are described in TABLE 5-8. "P7 Interconnect Signals" below: Support Information TABLE 5-8. P7 Interconnect Signals Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 N.C. VCC N.C. VCC N.C. VCC I/O O I/O O LD5 GND LD6 GND LD7 GND LD8 GND N.C. Signal Name Attribute I/O I/O I/O I/O LCD Data Line 8. LCD Data Line 7. LCD Data Line 6. LCD Data Line 5. Description Pin is cut to allow 30 pin connector insertion. Mux'ed on PB31. The MSB for the LCD data word. 5V supply. I/O O 5*1*4 PM1 - PM4, Mother Board Connectors MOTOROLA PR These connectors which connect to their mates on the motherboard (hence their name) are 140 pin inter-board, mail connectors made by Molex. These connectors are arranged in a quadratic shape, this to provide the shortest PCB routes as possible. As can be seen from their mechanical assembly shown in FIGURE 5-1 "Motherboard Connectors Mechanical Assembly" below - the connectors are not set in a perfect symmetric shape, this, to prevent the possibility of daughter-board's miss-insertion. MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM 5V supply. 5V supply. Mux'ed on PB19. The middle of the additional 3 LCD data bits. Mux'ed on PB17. The LSB of the additional 3 LCD data bits. IN AR Y 21 Support Information FIGURE 5-1 Motherboard Connectors Mechanical AssemblyA B PM1 1 13.68 11.14 71.12 1 1 PM2 46.3 PM3 PM4 17.49 1 93.98 The motherboard connectors's signals are described in TABLE 5-9. "PM1 Interconnect Signals" on page 23. , TABLE 5-10. "PM2 Interconnect Signals" on page 28. TABLE 5-11. "PM3 Interconnect Signals" on page 36 and TABLE 5-12. "PM4 Interconnect Signals" on page 43.TABLE 5-13. "PX1 - A. Top View (from Component side) B. All measures are in mm. 22 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA PR EL IM IN 30.19 AR Y Support Information PM1 Interconnect Signals' Differences" on page 49 TABLE 5-9. PM1 Interconnect Signals Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 BB~ VCC DRM_W~ VCC TEA~ VCC BR~ VCC BURST~ VCC GPL4A~ VCC TA~ VCC TS~ VCC GPL5B~ VCC BG~ X,L I/O, L I/O,L Signal Name Attribute I/O, L I,L I/O, L, O.D. Description MPC's Bus Busy signal. Pulled - up on the FADS. MPC's GPL0~ lines used as R/W~ signal for the DRAM simm or as A10 line for the SDRAM. Transfer Error Acknowledge. Pulled-up, not driven on board. MPC's Bus Request signal. Pulled - up on the FADS, but otherwise unused. MPC's Burst indication. Pulled - up on the FADS, but otherwise unused. I/O, L PR VCC GPL4B~ VCC R_W~ VCC BCSRCS~ VCC 26 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, L O, L I/O, L O, L I/O, L I/O, L O IM 5V Bus. UPMA general purpose line 4. Not used on the FADS. MPC's transfer Acknowledge signal. Indicates end of bus cycle, used with FADS logic. MPC's Transfer Start indication. Pulled - up, but otherwise unused on the FADS. General Purpose Line 5 of UPMB. Not used on the FADS. MPC's Bus grant signal. Pulled - up on the FADS, but otherwise unused. General Purpose Line 4 of UPMB. Not used on the FADS. MPC's Read/Write~ indication. Pulled - up on the FADS and used by FADS logic. In fact CS1~ of the MPC. Used as chip-select for the BCSRs. Pulled - up. When BCSR is removed from the local map, may be used off-board via the daughter-board's expansion connectors. IN AR Y 5V Bus. 23 Support Information TABLE 5-9. PM1 Interconnect Signals Pin No. 27 28 29 30 31 32 33 34 35 36 37 Signal Name GPL5A~ VCC BI~ N.C. CS7~ GND CS5~ GND CE1A~ GND F_CS~ Attribute X,L O I/O,L - Description UPMA general purpose line 5. Not used on the FADS. 5V Bus. MPC's Burst Inhibit input. Pulled - up, but otherwise unused on the FADS. Not Connected. Reserved. - FADS Ground plane. MPC's Chip Select line 5. Unused on the FADS. I, L PC-Card Enable 1 for PCMCIA slot A. Enables the EVEN address bytes. Used by on-board PCMCIA port. I/O, L In fact MPC's chip-select line 0. Used as chip-select for the Flash Simm. Pulled - up. When the Flash is disabled via BCSR, may be used off-board via the daughter-board's expansion connectors. 39 40 41 42 43 CS6~ GND CE2A~ GND DRMCS2~ 44 45 PR GND DRMCS1~ GND SDRMCS~ GND GPL3~ GND 46 47 48 49 50 24 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, L I/O, L I/O, L I/O, L I, L IM - 38 GND MPC's Chip Select line 6. Unused on the FADS. PC-Card Enable 2 for PCMCIA slot A. Enables the ODD address bytes. Used by on-board PCMCIA port. In fact MPC's chip-select line 3. Used as chip-select line for the 2'nd bank of the Dram Simm. Pulled - up. When the Dram is disabled via BCSR or when a single-bank Dram Simm is being used - may be used off-board via the daughter board's expansion connectors. In fact MPC's chip-select line 2. Used as chip-select line for the 1'st bank of the Dram Simm. Pulled - up. When the Dram is disabled via BCSR - may be used off-board via the daughter board's expansion connectors. In fact MPC's chip-select line 4. Used as chip-select for the Synchronous Dram. Pulled - up. When the SDRAM is disabled via BCSR, may be used off-board via the daughter board UPMA or UPMB general purpose line 3. Used as WR~ signal for the SDRAM. IN AR Y MOTOROLA Support Information TABLE 5-9. PM1 Interconnect Signals Pin No. 51 52 53 54 55 Signal Name GPL2~ GND WE3~ GND WE2~ Attribute I, L Description General Purpose Line 2 for UPMA or UPMB. Used with the SDRAM, as a CAS~ signal. I, L GPCM Write Enable 3 or PCMCIA WE~. Selects the LSB within a word for the Flash Simm or qualifies Writes for the PC-Card. I, L GPCM Write Enable 2 or PCMCIA OE~. Selects the offset 2 Byte within a word for the Flash Simm or open data buffers for read from PC-Card. 56 57 GND WE1~ I, L GPCM Write Enable1 or PCMCIA I/O Write. Used to qualify write cycles to the Flash memory and as I/O Write for the PCMCIA channel. 59 60 61 62 63 64 65 BS2A~ GND WE0~ GND SPARE1 GND EDOOE~ I, L Byte Select 2 for UPMA. Selects offset 2 bytes within Word. Used for Dram access. I, L 66 67 68 69 70 71 72 73 74 PR GND BS0A~ GND BS3A~ GND A31 GND BS1A~ GND MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I,L I, L I, L I, T.S. I, L I,O, L IM GPCM Write Enable 0 or PCMCIA I/O Read. Used to qualify write cycles to the Flash memory and as I/O Reads from PC-Card. MPC spare line 1. Pulled - up but otherwise unused on the FADS. In fact UPMA or UPMB General Purpose Line 1. Used for Output Enable with EDO Dram simms, which have this input (most of them don't). Used also as RAS signal for the SDRAM. Byte Select 0 from UPMA. Selects offset 0 Bytes within a word. Used as one of the CAS~ lines for Dram access. Byte Select 3 from UPMA. Selects offset 3 Bytes within a word. Used as one of the CAS~ lines for Dram access. MPC's Address line 31. Byte Select 1 from UPMA. Selects offset 1 Bytes within a word. Used as one of the CAS~ lines for Dram access. IN 58 GND AR Y 25 Support Information TABLE 5-9. PM1 Interconnect Signals Pin No. 75 Signal Name TSIZ1 Attribute x, T.S. Description Transfer Size 1. Used in conjunction with TSIZ0 to indicate the number of bytes remaining in an operand transfer. Not used on the FADS. 76 77 GND REG_A~ I, T.S., L In fact TSIZ0/REG~. Transfer Size 0 or PCMCIA slot A REG~. Used with the PCMCIA port as Attribute memory select or I/O space select. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 GND A30 GND A21 GND A20 GND A7 GND A15 GND A14 GND A13 GND A6 I, T.S. I, T.S. I, T.S. I, T.S. MPC's Address line 30. MPC's Address line 21. MPC's Address line 20. MPC's Address line 7. I, T.S. PR GND A12 GND A11 GND A19 GND A9 GND A18 GND 26 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. IM MPC's Address line 15. MPC's Address line 14. MPC's Address line 13. MPC's Address line 6. MPC's Address line 12. MPC's Address line 11. MPC's Address line 19. MPC's Address line 9. MPC's Address line 18. IN MOTOROLA AR Y Support Information TABLE 5-9. PM1 Interconnect Signals Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 A10 GND A17 GND A16 GND A8 GND A29 GND A27 GND A28 GND A26 GND A25 GND A24 GND A22 I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. MPC's Address line 16. I, T.S. MPC's Address line 17. Signal Name Attribute I, T.S. MPC's Address line 10. Description MPC's Address line 8. MPC's Address line 29. MPC's Address line 27. MPC's Address line 28. I, T.S. PR GND A3 GND A23 GND A4 GND A2 GND A5 GND A1 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. I, T.S. IM MPC's Address line 26. MPC's Address line 25. MPC's Address line 24. MPC's Address line 22. MPC's Address line 3. Not used on the FADS. MPC's Address line 23. MPC's Address line 4. Not used on the FADS. MPC's Address line 2. Not used on the FADS. MPC's Address line 5. Not used on the FADS. MPC's Address line 1. Not used on the FADS. IN 27 AR Y Support Information TABLE 5-9. PM1 Interconnect Signals Pin No. 138 139 140 Signal Name GND A0 GND Attribute Description I, T.S. MPC's Address line 0. Not used on the FADS. TABLE 5-10. PM2 Interconnect Signals 1 2 3 4 5 6 7 V12 O 10V output from voltage doubler. Used to switch TMOS gates on both mother and daughter boards. Should not be used for any other purpose. N.C. DSDI I/O 8 9 10 GND DSCK 11 PR DSDO GND AT2 GND 12 13 14 15 28 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O I I/O IM DSDI/TDI. Debug Port Serial Data Input or JTAG port serial Data Input. Used on the FADS as debug port serial data, driven by the debug-port controller. If the ADI bundle is not connected to the FADS, may be driven by external debug / JTAGa port controller. DSCK/TCK. Debug Port Serial Clock input or JTAG port serial clock input. Used on the FADS as debug port serial clock, driven by the debug-port controller. If the ADI bundle is not connected to the FADS, may be driven by an external debug / JTAGa port controller. DSDO/TDO. Debug Port Serial Data Output or JTAG port Data Output. Used on the FADS as debug port serial data. If the ADI bundle is not connected to the FADS, may be used by an external debug / JTAGa port controllers. IP_B2/IOIS16~/AT2. PCMCIA slot B Input Port 2 or PCMCIA 16 bit I/O capability indication or Address Type 2. For MPC823 or MPC850 daughter boards - configured as IP_B2/IOIS16~. For all other daughter boards, configured as AT2, but may be configured to alternate function as no use is done with AT2 on the FADS. IN AR Y Pin No. Signal Name Attribute Description MOTOROLA Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 16 VF2 Signal Name Attribute I/O Description IP_B3/IWP2/VF2. PCMCIA slot B Input Port 3 or Instruction Watch-Point 2 or Visible Instruction Queue Flushes Status 2. For MPC823 or MPC850 daughter boards - configured as IP_B3. For all other daughter boards, configured as VF2, but may be configured to alternate function as no use is done with VF2 on the FADS. 17 18 GND 19 20 21 22 23 24 GND IRQ3~ GND FRZ I/O, L IRQ3~/CR~. MPC's interrupt request 3 or Cancel Reservation. Pulled - up but otherwise not used on the FADS. I, X 25 26 27 28 29 30 GND IRQ2~ GND PR AT3 GND SPARE4 GND 31 32 33 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, L I/O I/O IM Freeze / IRQ6~. MPC debug state indication or Interrupt request line 6. Used by the debug port controller as debug state indication. May be configured to alternate function provided that VFLS(0:1) function as VFLS and J1 is moved to position 1-2. RSV~/IRQ2~. Reservation or Interrupt Request 2. Pulled - up but otherwise unused on the FADS. IP_B7/PTR/AT3. PCMCIA slot B Input Port 7 or Program Trace (instruction fetch indication or Address Type 3. For MPC823 or MPC850 daughter boards - configured as IP_B7. For all other daughter boards, configured as AT3, but may be configured to alternate function as no use is done with AT3 on the FADS. MPC's spare line 4. Pulled - up but otherwise unused on the FADS. IN AR Y VF0 I/O IP_B4/LWP0/VF0. PCMCIA slot B Input Port 4 or Data WatchPoint 0 or Visible Instruction Queue Flushes Status 0. For MPC823 or MPC850 daughter boards - configured as IP_B4. For all other daughter boards, configured as VF0, but may be configured to alternate function as no use is done with VF0 on the FADS. 29 Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 34 Signal Name VFLS0 Attribute I/O Description IP_B0/IWP0/VFLS0. PCMCIA slot B Input Port 0 or Instruction Watchpoint 0 or Visible history Flushes Status 0. For the MPC823 or MPC850 daughter boards, configured as IP_B0. For all other daughter boards - configured as VFLS0. May be configured to any alternate function. Indicates in conjunction with VFLS1, the number of instructions flushed from the core's history buffer. Indicates also whether the MPC is in debug mode. If not using the debug port, may be configured for alternate function. 36 SPKROUT I, X KR~/IRQ4~/SPKROUT. Kill Reservation input or Interrupt Request 4 input or PCMCIA Speaker Output. Configured on the FADS as SPKROUT. May be configured to alternate function. 37 38 GND VFLS1 I/O 39 40 41 42 GND VF1 43 44 PR GND AT1 GND AT0 GND POE_A~ 45 46 47 48 30 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I I, L IM IP_B1/IWP1/VFLS1. PCMCIA slot B Input Port 1 or Instruction Watchpoint 1 or Visible history Flushes Status 1. For the MPC823 or MPC850 daughter boards, configured as IP_B1. For all other daughter boards - configured as VFLS0. May be configured. Indicates in conjunction with VFLS1, the number of instructions flushed from the core's history buffer. Indicates also whether the MPC is in debug mode. If not using the debug port, may be configured for alternate function. IP_B5/LWP1/VF1. PCMCIA slot B Input Port 5 or Load/Store Watch-Point 1 or Visible Instruction Queue Flushes Status 1. For MPC823 or MPC850 configured as IP_B5, for all other daughter boards configured as VF1. May be configured to any alternate function as no use is done with it on the FADS. ALE_B/DSCK/AT1. Address Latch Enable for PCMCIA slot B or Debug Serial Clock or Address Type 1. For MPC823 or MPC850 daughter boards configured as ALE_B for all other daughter boards configured as AT1. Not used on the FADS. May be configured to any alternate function. IP_B6/DSDI/AT0. Input Port B 6 or Debug Serial Data Input or Address Type 0. Configured on the as AT0. May be used for alternate function. In fact OP1 of the PCMCIA I/F. Enables address buffers towards the PC-Card. IN AR Y 35 GND MOTOROLA Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 49 50 51 52 BADDR30 I/O,X Burst Address Line 30. Dedicated for external master support. Used to generate Burst address during external master burst cycles. Pulled - up but otherwise unused on the FADS. Signal Name GND Attribute Description 53 54 55 56 GND ALE_A GND BADDR29 I/O,X I, H Address Latch Enable for PCMCIA slot A. Latches address in external latches at the beginning of access to a PC-Card. Burst Address Line 29. Dedicated for external master support. Used to generate Burst address during external master burst cycles. Pulled - up but otherwise unused on the FADS. 57 58 GND AS~ I/O, L 59 60 GND MODCK1 I/O 61 62 63 64 65 66 GND RESETA GND PR BADDR28 GND TEXP GND WAIT_B~ GND 67 68 69 70 71 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I,H I/O,X X,X I/O, L IM Asynchronous external master Address Strobe signal. When asserted (L) by the external master, the MPC recognizes an asynchronous cycle in progress. Pulled - up but otherwise unused on the FADS. OP2/MODCK1/STS~. PCMCIA Output Port 2 or Mode Clock 1 input or Special Transfer Start output. Used at Power-On reset as MODCK1. For MPC823 or MPC850 daughter boards configured afterwards as a OP2 for all other daughter boards configured afterwards as STS~. PC-Card reset signal. Burst Address Line 28. Dedicated for external master support. Used to generate Burst address during external master burst cycles. Pulled - up but otherwise unused on the FADS. MPC Timer Expired. Not used on the FADS. This signal is PCMCIA slot B wait signal. Pulled-up but otherwise not used on the FADS. IN AR Y 31 Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 72 Signal Name MODCK2 Attribute I/O Description OP3/MODCK2/DSDO. PCMCIA Output Port 3 or Mode Clock 2 input or Special Transfer Start output. Used at Power-On reset as MODCK2 and configured afterwards as a OP3. May be used with alternate function. 73 74 GND 76 77 78 79 80 81 82 83 84 85 86 N.C. GND SRESET~ GND PORST~ GND HRESET~ GND RSTCNF~ I/O, L, O.D. MPC Soft Reset. Driven by on-board logic and may be driven by off-board logic with Open-Drain gate only. X, L Power On reset for the MPC. Not used on the FADS, generated on the daughter boards I/O, L, O.D. 87 88 GND R_PORI~ PR GND BWAITA~ GND BWP 89 90 91 92 93 94 32 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O, L O, L O, L O, H IM MPC Hard Reset. Driven by on-board logic and may be driven by off-board logic with Open-Drain gate only. Hard Reset Configuration output. Driven during Hard Reset to the daughter board to signal the MPC that it should sample Hard Reset configuration from the data bus. Main battery power-on reset. Generated as a result of main 3.3V bus going through power up or power-down. Drives on-board logic as well either HARD-RESET or Power-On reset to the MPC. Buffered PCMCIA slot A WAIT signal. Used to prolong cycles to slow PC-Cards. In case of MPC823 or MPC850 daughter boards, connected to WAIT_B~ signal of the MPC. Buffered PCMCIA slot A Write Protect. In fact IP_A2/IOIS16A~. Used as PC-card write protect indication or as 16 bit I/O capability indication for PCMCIA slot A. In case of MPC823 or MPC850 daughter boards, connected to IP_B2 signal of the MPC. IN AR Y 75 MOTOROLA Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 95 96 Signal Name GND BVS1 Attribute Description O,X Buffered PCMCIA slot A Voltage Sense 1. In fact IP_A0. Used in conjunction with BVS2 to determine the operation voltage of a PCMCIA card. In case of MPC823 or MPC850 daughter boards, connected to IP_B0 signal of the MPC. 97 98 GND 99 100 101 102 GND 104 BVS2 O, X 105 106 GND BCD1~ 107 108 PR GND MODIN GND BBVD1 GND BCD2~ GND 109 110 111 112 113 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O, L O, X O, X O, L IM 103 GND Buffered PCMCIA slot A Voltage Sense 2. In fact IP_A1. Used in conjunction with BVS1 to determine the operation voltage of a PCMCIA card. In case of MPC823 or MPC850 daughter boards, connected to IP_B1 signal of the MPC. Buffered PCMCIA slot A Card Detect 1. In fact IP_A4. Input Port 4 of PCMCIA slot A. Used as Card Detect indication in conjunction with BCD2~. In case of MPC823 or MPC850 daughter boards, connected to IP_B4 signal of the MPC. This signal selects between clock generator and the 32768 Hz crystal as clock sources for the MPC. Its is driven by DS2/4. See 2*3*2 "Clock Source Selection "on page 7. In the motherboard documentations. Buffered PCMCIA slot A Battery Voltage Detect 1. In fact IP_A6. Used in conjunction with BBVD2 to determine the battery status of a PC-Card. In case of MPC823 or MPC850 daughter boards, connected to IP_B6 signal of the MPC. Buffered PCMCIA slot A Card Detect 2. In fact IP_A3. Input Port 3 of PCMCIA slot A. Used as Card Detect indication in conjunction with BCD1~. In case of MPC823 or MPC850 daughter boards, connected to IP_B3 signal of the MPC. IN DP3 I/O, X DP3/IRQ6~. Data Parity line 3 or Interrupt Request 6. May generate and receive parity data for D(24:31) bits connected to the DRAM SIMM. May also be configured as IRQ6~ input for the MPC. AR Y BRDY O, H Buffered PCMCIA slot A Ready signal. In fact IP_A7. Used as PCMCIA port A Card Ready indication. In case of MPC823 or MPC850 daughter boards, connected to IP_B7 signal of the MPC. 33 Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 114 Signal Name BBVD2 Attribute O, X Description Buffered PCMCIA slot A Battery Voltage Detect 2. In fact IP_A5. Used in conjunction with BBVD1 to determine the battery status of a PC-Card. In case of MPC823 or MPC850 daughter boards, connected to IP_B5 signal of the MPC. 115 116 GND 118 DP0 I/O DP0/IRQ3~. Data Parity line 0 or Interrupt Request 3. May generate and receive parity data for D(0:7) bits connected to the DRAM SIMM. May not be configured as IRQ3~. 119 120 V3.3 DP2 I/O DP2/IRQ5~. Data Parity line 2 or Interrupt Request 5. May generate and receive parity data for D(16:23) bits connected to the DRAM SIMM. May not be configured as IRQ5~. 121 122 V3.3 DP1 I/O 123 124 125 126 127 128 129 130 131 132 133 134 V3.3 N.C. V3.3 IRQ1~ V3.3 SPARE3 V3.3 PR IRQ7~ V3.3 N.C. V3.3 NMI~ V3.3 N.C. V3.3 135 136 137 34 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, L I/O, X I/O, L I/O, L IM DP1/IRQ4~. Data Parity line1 or Interrupt Request 4. May generate and receive parity data for D(8:15) bits connected to the DRAM SIMM. May not be configured as IRQ4~. Interrupt Request 1.Pulled-up but otherwise not used on the FADS. MPC's spare line 3. Pulled - up but otherwise unused on the FADS. Interrupt Request 7. The lowest priority interrupt request line. Pulled - up but otherwise not used on the FADS. Non-Makable Interrupt. In fact IRQ0~ of the MPC. Driven by onboard logic by O.D. gate. Pulled - up. May be driven off-board by O.D. gate only. IN AR Y 117 N.C. MOTOROLA Support Information TABLE 5-10. PM2 Interconnect Signals Pin No. 138 139 140 N.C. V3.3 N.C. Signal Name Attribute Description a. Be aware that TRST~ is connected to GND with a zero ohm resistor. MOTOROLA PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN 35 AR Y Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 1 2 3 4 UUFEN~ O, L Signal Name ETHRX GND Attribute O, X Description Ethernet port Receive Data. When the ethernet port is disabled via BCSR1 - tri-stated. Appears also at P8. When this signal is active (LOW) it enable the LXT970 device. This signal connected to the TRSTE signal of the LXT970. In DTE mode when this pin is high the LXT970 isolate it self from the MII data interface. In repeater mode when it is high the LXT970 tree state the MII output pins. Ethernet Port Transmit Data. Appears also at P8. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ETHTX GND I, X PC9 IRDRXD GND IRDTXD GND X, X O, X MPC's PI/O C 9 pin. Appears also at P8 but otherwise unused on the FADS. InfraRed Port Receive Data. When the I/R port is disabled via BCSR1 - tri-stated. Appears also at P8. I, X PC8 PA11 GND PR PA10 GND PC7 PA9 GND PA8 GND PC13 36 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X I/O, X I/O, X I/O, X I/O, X I/O, X I/O, X IM InfraRed Port Transmit Data. Appears also at P8. MPC PI/O port C 8. Appears also at P8 but otherwise unused. MPC PI/O port A 11. Appears also at P8 but otherwise unused. MPC PI/O port A 10. Appears also at P8 but otherwise unused. MPC PI/O port C 7. Appears also at P8 but otherwise unused. MPC PI/O port A 9. Appears also at P8 but otherwise unused. MPC PI/O port A 9. Appears also at P8 but otherwise unused. MPC PI/O port C 13. Appears also at P8 but otherwise unused. IN AR Y MOTOROLA Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 27 28 29 30 31 32 FETHCFG0 O, X Signal Name ETHTCK GND ETHRCK GND Attribute O, X Description Ethernet port Transmit Clock. When the ethernet port is disabled via BCSR1 - tri-stated. Appears also at P8. O, X Ethernet port Receive Clock. When the ethernet port is disabled via BCSR1 - tri-stated. Appears also at P8. Fast Ethernet CFG0 signal When the LXT970 is in auto negotiation a low to high transition in this pin cause an auto negotiate to re-start. When auto negotiation is disabled this input selects operating speed bit 0.13 When this pin is high the 100Mbps is selected 0.13 = 1. When this pin is low the 10Mbps is selected 0.13 = 0. 34 BINPAK~ I/O PCMCIA port Input Port Acknowledge. In fact PC15/DREQ1~/ RTS1~/L1ST1. When the PCMCIA port is disabled via BCSR1, may be used off-board for any alternate function. MPC PI/O port B 30. Appears also at P8 but otherwise unused. 35 36 37 38 PB30 GND PB29 RSTXD1 I/O, X I/O, X I, X 39 RSRXD1 40 PR RSDTR1~ GND RSTXD2 RSRXD2 RSDTR2~ PC14 GND 41 42 43 44 45 46 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O, X O, L I, X O, X O, L I/O, X IM MPC PI/O port B 29. Appears also at P8 but otherwise unused. RS232 Port 1 Transmit Data. When RS232 port 1 is disabled via BCSR1, may be used for any alternate function. Appears also at P8. RS232 Port 1 Receive Data. When RS232 port 1 is disabled via BCSR1 - tri-stated and may be used for any alternate function. Appears also at P8. RS232 port 1 DTR~ signal. When RS232 port 1 is disabled via BCSR1 - tri-stated and may be used for any alternate function. Appears also at P8. RS232 Port 2 Transmit Data. When RS232 port 2 is disabled via BCSR1, may be used for any alternate function. Appears also at P8. RS232 Port 2 Receive Data. When RS232 port 2 is disabled via BCSR1 - tri-stated and may be used for any alternate function. Appears also at P8. RS232 port 2 DTR~ signal. When RS232 port 2 is disabled via BCSR1 - tri-stated and may be used for any alternate function. Appears also at P8. MPC PI/O port C 14. Appears also at P8 but otherwise unused. IN 33 PB31 I/O, X MPC PI/O port B 31. Appears also at P8 but otherwise unused. AR Y 37 Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 PA4 E_CLSN I/O, X I/O, H PA5 GND I/O, X PB27 PB28 GND PC12 PB26 GND I/O, X I/O, X I/O, X I/O, X MPC PI/O port B 27. Appears also at P8 but otherwise unused. MPC PI/O port B 28. Appears also at P8 but otherwise unused. N.C. GND Signal Name Attribute Description MPC PI/O port C 12. Appears also at P8 but otherwise unused. MPC PI/O port C 26. Appears also at P8 but otherwise unused. MPC PI/O port A 5. Appears also at P8 but otherwise unused. MPC PI/O port A 4. Appears also at P8 but otherwise unused. Ethernet Port Collision indication signal. Connected to the SCC's CTS~ signal. When the ethernet port is disabled via BCSR1, may be used off-board for any alternate function. Ethernet Receive Enable. Connected to the SCC's CD~ signal. Active when there is network activity. When the ethernet port is disabled via BCSR1, may be used off-board for any alternate function. MPC spare line 2. Pulled - up but otherwise unused on the FADS. 62 E_RENA I/O, H 63 64 65 66 67 68 69 70 71 72 73 74 75 SPARE2 VDOEN~ GND PR SYSCLK GND PA3 GND PA2 PB17 38 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X O, L I, X I/O, X I/O, X I/O, X IM Applies only for MPC823 daughter board. Video Encoder Enable Indication. Generated by BCSR4. Not USED IN THE 860TDB System Clock. In fact the CLKOUT of the MPC. MPC PI/O port A 3. Appears also at P8 but otherwise unused. MPC PI/O port A 2. Appears also at P8 but otherwise unused. MPC PI/O port B 17. Appears also at P8 but otherwise unused. IN AR Y MOTOROLA Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 76 77 Signal Name PB18 E_TENA Attribute I/O, X I/O, H Description MPC PI/O port B 18. Appears also at P8 but otherwise unused. Ethernet port Transmit Enable. Connected to the SCC's RTS~ signal. When active, transmit is enabled via the MC68160 EEST. When the ethernet port is disabled via BCSR1, may be used offboard for any alternate function. 78 79 80 81 82 GND ETHEN~ O, L Ethernet Port Enable. Connected to BCSR1. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. 83 84 N.C. IRD_EN~ O, L Infra-Red Enable. Connected to BCSR1. See TABLE 4-10. "BCSR1 Description" on page 49.In the motherboard documentations. MPC PI/O port A 1. Appears also at P8 but otherwise unused. 85 86 87 88 89 90 91 92 93 94 PA1 GND I/O, X N.C. PA0 GND PR PB16 TRST~ PB15 RS_EN1~ PB14 PC4 PC5 PC6 GND TMS 95 96 97 98 99 100 101 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X I/O, X I/O, X O, L I/O, X O, L I/O, X I/O, X I/O, X I/O, X IM MPC PI/O port A 0. Appears also at P8 but otherwise unused. JTAG port Test Mode Select input. Used to select test through the JTAG port. Pulled-up but otherwise not used on the FADS. MPC PI/O port B 16. Appears also at P8 but otherwise unused. JTAG port Reset. Pulled down with a zero ohm resistor, so that the JTAG logic is constantly reset. Otherwise unused on the FADS. MPC PI/O port B 15. Appears also at P8 but otherwise unused. RS232 port 1 Enable. Connected to BCSR1. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. MPC PI/O port B 14. Appears also at P8 but otherwise unused. MPC PI/O port C 4. Appears also at P8 but otherwise unused. MPC PI/O port C 5. Appears also at P8 but otherwise unused. MPC PI/O port C 6. Appears also at P8 but otherwise unused. IN AR Y N.C. 39 Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 102 Signal Name RS_EN2~ Attribute O, L Description RS232 port 1 Enable. Connected to BCSR1. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentation. MPC821's or MPC823's PD3/SHIFT/CLK or MPC860s' PD3/ RRJECT4~. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as Video Clock input. 103 SHIFT_C I/O, X 104 105 106 GND HSYNC I/O, X MPC821's or MPC823's PD4/LOAD/HSYNC or MPC860s' PD4/ RRJECT3~. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as HSYNC for the video encoder. 108 109 110 GND LOE I/O, X 111 112 FETHRST~ PR FETHCFG1 LD0 LD1 113 114 40 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O, L O, H I/O, X IM MPC821's or MPC823's PD6/LCD_AC/LOE or MPC860s' PD6/ RTS4~. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On the MPC823 daughter board used also as BLANK~ signal for the video encoder. Fast Ethernet Reset. When this pin active (LOW) signal is being asserted the Fast ethernet tranceiver is being reset. Fast Ethernet CFG1 signal When the LXT970 is in auto negotiation this pin determines operating speed advertisement capability in combination with MF4. see See the LXT970 documentation. When auto negotiation is disabled this input enables 10Mbps link test function and directly affects bit 19.8. When this pin is high, 10Mbps link test is disabled 19.8 = 1. When this pin is low, 10Mbps link test is enabled 19.8 = 0. MPC821's or MPC823's PD7/LD0 or MPC860s' PD7/RTS3~. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 7. MPC821's or MPC PD8/LD1 or MPC860s' PD8/TXD4. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 6. IN 107 VSYNC I/O, X MPC821's or MPC823's PD5/FRAME/VSYNC or MPC860s' PD5/ RRJECT2~. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as FIELD signal for the video encoder. AR Y MOTOROLA Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 115 LD2 Signal Name Attribute I/O, X Description MPC821's or MPC823's PD9/LD2 or MPC860s' PD9/RXD4. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 5. MPC821's or MPC823's PD10/LD3 or MPC860s' PD10/TXD3. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 4. MPC821's or MPC823's PD11/LD4 or MPC860s' PD11/RXD3. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 3. MPC821's or MPC823's PD12/LD5 or MPC860s' PD12/ L1RSYNCB. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 2. MPC821's or MPC823's PD13/LD6 or MPC860s' PD13/ L1TSYNCB. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 1. MPC821's or MPC823's PD14/LD7 or MPC860s' PD14/ L1RSYNCA. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. On MPC823 daughter board used as video data 0. MPC821's or MPC823's PD15/LD8 or MPC860s' PD15/ L1TSYNCA. Not used on the FADS. Appears also at P8. On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector. 116 LD3 I/O, X 117 LD4 I/O, X 118 LD5 I/O 119 LD6 I/O, X 120 LD7 I/O, X 121 LD8 122 123 124 PR GND ETHLOOP TPFLDL~ TPSQEL~ MDM_AUD~ 125 126 127 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X O, H O, L O, L O, L IM Ethernet Transceiver Diagnostic Loop-Back Control. Generated by BCSR4. See TABLE 4-23. "BCSR4 Description" on page 57. In the motherboard documentations. Twisted Pair Full Duplex. Allows for full-duplex operation over the Ethernet Twisted-Pair channel. See TABLE 4-23. "BCSR4 Description" on page 57. In the motherboard documentations. Twisted Pair Signal Quality Error Test Enable. See TABLE 4-23. "BCSR4 Description" on page 57. In the motherboard documentations. Applies only for MPC823 daughter board. Selects between the Data / Voice paths of the MPC821 Modem Tool. See TABLE 423. "BCSR4 Description" on page 57. In the motherboard documentations. IN AR Y 41 Support Information TABLE 5-11. PM3 Interconnect Signals Pin No. 128 Signal Name MODEMEN~ Attribute O, L Description Applies only for MPC823 daughter board. Enables the MPC821 Modem Tool as well as a multiplexer for data / voice signals on the MPC823 daughter board. See TABLE 4-23. "BCSR4 Description" on page 57. In the motherboard documentations. 129 130 131 132 133 134 135 136 137 138 139 140 N.C. GND VCC 42 PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y N.C. Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D27 GND D26 GND D25 GND D24 GND I/O, X Signal Name GND D31 GND D30 GND D29 GND D28 GND Attribute Description I/O, X MPC's Data line 31. I/O, X MPC's Data line 30. I/O, X MPC's Data line 29. I/O, X MPC's Data line28. MPC's Data line 27. I/O, X I/O, X PR D23 GND D22 GND D21 GND D20 GND MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X I/O, X I/O, X I/O, X I/O, X IM MPC's Data line 26. MPC's Data line 25. MPC's Data line 24. MPC's Data line 23. MPC's Data line 22. MPC's Data line 21. MPC's Data line 20. IN 43 AR Y Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 D7 GND D6 I/O, X MPC's Data line 6. I/O, X MPC's Data line 7. D11 D15 GND D14 GND D13 GND D12 GND I/O, X I/O, X I/O, X D19 GND D18 GND D17 GND D16 GND I/O, X I/O, X MPC's Data line 17. I/O, X MPC's Data line 18. Signal Name Attribute I/O, X MPC's Data line 191. Description MPC's Data line 16. MPC's Data line 15. MPC's Data line 14. I/O, X PR GND D10 GND D9 GND D8 GND 44 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X I/O, X I/O, X I/O, X IM MPC's Data line 13. MPC's Data line 12. MPC's Data line 11. MPC's Data line 10. MPC's Data line 9. MPC's Data line 8. IN MOTOROLA AR Y Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 DRMH_W~ D3 GND D2 GND D1 GND D0 GND I/O, X I/O, X MPC's Data line 1. I/O, X MPC's Data line 2. I/O, X MPC's Data line 3. Signal Name GND D5 GND D4 GND Attribute Description I/O, X MPC's Data line 5. I/O, X MPC's Data line 4. MPC's Data line 0. O, L 82 DRAMEN~ 83 PR FCFGEN~ F_EN~ SDRAMEN BCSREN~ 84 85 86 MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL O, L O, L O, L O, H O, L IM Dram Half Word. Sets the Dram to 16 bit data bus width. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. Dram Enable. Enables Dram to the FADS memory map. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. Flash Configuration Enable. Allows for Hard Reset Configuration to be obtained from the Flash memory provided that this option is supported by the MPC. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. Flash Enable. Enables the Flash memory to the FADS memory map. See TABLE 4-10. "BCSR1 Description" on page 49 In the motherboard documentations. Sdram Enable. Enables the Synchronous Dram to the FADS memory map. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. BCSR Enable. Enables the BCSR to the FADS memory map. See TABLE 4-10. "BCSR1 Description" on page 49. In the motherboard documentations. IN 45 AR Y Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 87 Signal Name FETHFDE Attribute O, X Description Full Duplex Enable when auto negotiation is enable the FDE pin of the LXT970 determine full duplex advertisement capability in combination with MF4 and CFG1. See than LXT970 documentation. When auto negotiation is disable the FDE pin of the LXT970 effects full duplex and determines the value of bit 0.8 Duplex Mode. When this pin is high Full Duplex in Enable. 0.8 = 1. When this pin is low Full Duplex is Disable 0.8 = 0. PC- Card Enable. Enables the PC-Card to be accessed by the FADS. External Tool Identification 0. Connected to BCSR2. See 4*11*4 "BCSR2 - Board Control / Status Register - 2" on page 51.In the motherboard documentations. Signaling Lamp. Used for misc. s/w signaling purpose. See 88 89 PCCEN~ EXTOLI0 O, L I/O, X 90 SGLAMP~ O, L TABLE 4-23. "BCSR4 Description" on page 57. In the 91 EXTOLI2 I/O, X External Tool Identification 2. Connected to BCSR2. See 4*11*4 "BCSR2 - Board Control / Status Register - 2" on page 51.In the motherboard documentations. Applies only for MPC823DB. Reserved Signal for USB Power. See TABLE 4-23. "BCSR4 Description" on page 57. In the motherboard documentations. 92 USBVCC1 O, X 93 DBREV0 I, X 94 EXTOLI1 95 PR DBREV2 EXTOLI3 BCSR3R1 DBREV1 DBID1 BCSR3R0 96 97 98 99 100 46 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O, X I, X I/O, X I/O, X I/O, X I/O, X I/O, X IM Daughter Board Revision Code Signal 0. The MSB of the D/B revision Code. See TABLE 4-13. "BCSR2 Description" on page 52. In the motherboard documentations. External Tool Identification 1. Connected to BCSR2. See 4*11*4 "BCSR2 - Board Control / Status Register - 2" on page 51. In the motherboard documentations. Daughter Board Revision Code Signal 2. The LMSB of the D/B revision Code. See TABLE 4-13. "BCSR2 Description" on page 52. In the motherboard documentations. External Tool Identification 3. Connected to BCSR2. See 4*11*4 "BCSR2 - Board Control / Status Register - 2" on page 51. In the motherboard documentations. Reserved signal 1 in BCSR3. See TABLE 4-19. "BCSR3 Description" on page 55. In the motherboard documentations. Daughter Board Revision Code Signal 1. See TABLE 4-13. "BCSR2 Description" on page 52. In the motherboard documentations. Daughter Board ID Code 1. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. Reserved signal 0 in BCSR3. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. IN motherboard documentations. AR Y MOTOROLA Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 101 Signal Name DBID3 Attribute I/O, X Description Daughter Board ID Code 3. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. Daughter Board ID Code 0. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. Daughter Board ID Code 5. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. Daughter Board ID Code 2. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. Reserved signal 13 in BCSR3. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. 102 DBID0 I/O, X 103 DBID5 I/O, X 104 DBID2 I/O, X 105 106 BCSR3R13 DBID4 I/O, X I/O, X 107 CHINS~ I/O, L 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 GND N.C. GND MOTOROLA PR N.C. GND N.C. GND N.C. MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM Chip In Socket. When this signal is active (low), FADS logic is noticed that the evaluated MPC8XX resides in its socket. If inactive, either the MPC is out of socket or a daughter board is not connected, in which case the FADS becomes a debug station. IN Daughter Board ID Code 4. Part of the field which designates the type of daughter board connected. See TABLE 4-19. "BCSR3 Description" on page 55 In the motherboard documentations. AR Y 47 Support Information TABLE 5-12. PM4 Interconnect Signals Pin No. 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 GND N.C. GND N.C. GND N.C. GND N.C. Signal Name GND Attribute Description 5*1*5 PX1 - PX4 Hardware Expansion Connectors 48 PR These connectors are receptacle inter-board connectors made by Molex. They are identical to those exist on the MPC8XXFADS mother board. Their mechanical assembly is similar as well and is shown in FIGURE 5-2 "Expansion Connectors Mechanical Assembly" below: MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Support Information FIGURE 5-2 Expansion Connectors Mechanical Assembly PX1 1 13.28 10.74 71.12 1 1 PX4 17.09 1 IN 93.98 TABLE 5-13. PX1 - PM1 Interconnect Signals' Differences Pin No. Signal Name Attribute Description Pin No. 76 PR TABLE 5-14. PX2 - PM2 Interconnect Signals' Differences Signal Name Attribute O, X EL Attribute IM In principle, the expansion connectors are identical in signals assignment to the mother boards connectors. However, there is a difference mainly between PM3 and PX3, resulting from the difference between the various members of the 8XX family. Therefore, in the following tables only the differences are documented per each connector pair - PM1 - PX1... No Difference EXTCLK External Clock. 4MHz clock generator output, the input clock to the MPC. TABLE 5-15. PX3 - PM3 Interconnect Signals' Differences Pin No. Signal Name Description No Difference MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y 29.79 Description PX2 47.1 PX3 49 Support Information TABLE 5-16. PX4 - PM4 Interconnect Signals' Differences Pin No. Signal Name Attribute No Difference Description 5*1*6 MPC8XXFADS's P8 - Serial Ports' Expansion Connector 50 PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y P8 is a 96 pin, 900, DIN 41612 connector, which allows for convenient expansion of the MPC's serial ports. Although this connector resides on the mother board it is documented here, this, since it's signal assignment is unique per each MPC8XX. For the 860SAR this connector is the connector which through it the user will operate the 860SAR-PHY board. In the 860SAR-PHY board this connector called P13. Support Information Note: The contents of TABLE 5-17. "P13 - Interconnect Signals" below, might conflict with MPC8XXFADS's schematic page 14. This since, that the schematic page is named in MPC821/860 terms. In such case, this table overrides! TABLE 5-17. P13 - Interconnect Signals Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 Signal Name ETHRX ETHTX IRDRXD IRDTXD LD4 LD3 LD2 LD1 ETHTCK ETHRCK N.C. PA4 N.C. L1RCLKB N.C. Attribute I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Ethernet port receive data. See PM3(1) Ethernet Port transmit data. See PM3(5,11,42) IrDA port receive data. See PM3(9). IrDA port transmit data. See PM3(5,11,42) Also VD3. See PM3(117) Also VD2. See PM3(116) Also VD1. See PM3(115) Also VD0. See PM3(114) I/O - PR VCC PA9 L1RXDB PA9 L1RXDA GND GND IRQ7~ FRZ ETHEN~ N.C. MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O I/O I/O I/O I/O I, L I/O O - I/O IM Ethernet port transmit clock. See PM3(27). Ethernet port receive clock. See PM3(29) BRGCLK2/TOUT2/CLK4/PA[4]. See PM3(60) See PM3(74). See PM3(15,21). See PM3(17). See PM3(21). See PM3(23) See PM2(130) See PM2(24). See PM3(82) IN AR Y 51 Support Information TABLE 5-17. P13 - Interconnect Signals Pin No. A28 A29 A30 A31 A32 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 Signal Name IRQ2~ IRQ1~ NMI~ RS_EN1~ GND LCD_A PB30 PB29 PB28 I2CDAT I2CCLK RSTXD1 RSRXD1 RSDTR1~ RSDTR2~ TXD2. RSRXD2 E_TENA LCD_B LCD_C PB16 N.C. N.C. Attribute I, L I, L I, L O,L RSV/IRQ2~. See PM2(26). See PM2(126). See PM2(134). See PM3(96). Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O See PM3(35). See PM3(37). See PM3(51). PB27/I2CDAT. See PM3(50). PB26/I2CCLK. See PM3(54). See PM3(38). See PM3(39). See PM3(40). See PM3(44). See PM3(5,11,42). See PM3(43) See PM3(77). PB19/LCD_B. See PM3(76). PB17/LCD_C. See PM3(75). See PM3(93). PR GND BINPAK~ PC14 PC13 PC12 E_CLSN E_RENA USBRXP USBRXN USBTXP 52 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IM See PM3(34). See PM3(45). See PM3(26). See PM3(53). See PM3(61). See PM3(62). PC11/USBRXP. See PM3(8). PC10/USBRXN. See PM3(14). PC7/USBTXP. See PM3(20). IN MOTOROLA AR Y I/O LCD_A/PB31. See PM3(33). Support Information TABLE 5-17. P13 - Interconnect Signals Pin No. B29 B30 B31 B32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 GND VD7 VD6 VD5 VD4 RS_EN2~ GND O, L See PM3(102). Signal Name L1RSYNCB PC5 L1RSYNCA GND VCC Attribute I/O I/O I/O See PM3(100). See PM3(99). See PM3(98). Description PR FIELD BLANK~ VCC HRESET~ SRESET~ N.C. VCC VDOCLK VPPIN MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL I/O I/O I/O I/O I/O I/O I/O, L I/O, L I/O I/O IM See PM3(121). See PM3(120). See PM3(119). See PM3(118). See PM3(113). See PM3(110). See PM2(84). See PM2(80). Not Connected See PM3(103) +12V input for PCMCIA flash programming. Parallel to P7 of the MPC8XXFADS. IN 53 AR Y Support Information TABLE 5-17. P13 - Interconnect Signals Pin No. C30 C31 C32 Signal Name HSYNC GND VSYNC Attribute I/O I/O See PM3(107). See PM3(106). Description 54 PR MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM MOTOROLA IN AR Y Support Information 5*2 MPC860TFADSDB Part List In this section the MPC860TFADSDB bill of material is listed according to their reference designation. TABLE 5-18. MPC860TFADSDB Part List Reference Designation C5 C6 C7 C8 C9 C10 C11 C12 C14 C15 C16 C17 C19 C20 C22 C23 C24 C25 C28 C29 C32 C37 C38 C39 C40 C43 C47 C48 C49 C52 C53 C2 C3 C4 C31 C33 C34 C36 C51 C13 C30 C35 C18 C21 C26 C27 C1 C44 C45 C46 C41 C42 C50 D1 DS1 Part Description Capacitor 0.1F,16V, 10%, SMD 0603, Ceramic Manufacturer AVX Part # 0603YC104KAT20 Capacitor 10F, 20V, 10%, SMD Size C, Tantalum Capacitor 100F, 10V, 10%, SMD Size D, Tantalum Capacitor 1F, 25V, 10%, SMD Size A, Tantalum Capacitor 10pF, 50V 10%, COG, SMD 1206, Ceramic Capacitor 5000pF, 50V, SMD 1206, Ceramic Capacitor 0.68F, 20V, SMD, Size A, Tantalum 10%, IN AVX AVX 10%, SIEMENS VTRAMON AVX AVX Motorola BOURNS PRECIDIP BOURNS FAIR-RITE SIEMENS AMP KCC SAMTEC IM Cap 0.01F 50V 10% NPO 1206 EL Diode SMD Dip Switch Ferrite bid SMD Cap 18pF 50V COG 1206 SMD CER T/R Cap 1nF2KV X7R 1210 SMD CER CAP T/R PR H1 H2 H3 J1 J2 J3 J4 J5 L1 Gnd Bridge, Gold Plated Jumper Header, 3 Pole with Fabricated Jumper Jumper, Soldered. Inductor 8.2 mHy L2 L3 L4 L5 L6 L7 LD1 LD2 LD3 LD4 LD5 LD6 LD7 P1 P2 P4 P5 P6 P8 P9 P3 P7 Led Green SMD Connector 38 pin, Receptacle MICTOR. RJ_45 8PIN CONNECTOR Connector Header, 40 pin, Dual In-line, SMD MOTOROLA MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y SIEMENS SIEMENS SIEMENS LL4004G 90HBW08S PT12133 2743021447 LG-T679-C0 2-767004-2 90015-8P8C B45196-H4475-K20 B45196-H2107-K10 B45196-H5105-K10 AV12065A100KAT00J AV12065C 502K A700J B45196-E4684-K9 VJ1210A103KXAT 12065A180JAT 1210B102K202NT 999-11-112-10 TSM-115-04-S-DV 55 Support Information TABLE 5-18. MPC860TFADSDB Part List Reference Designation PM1 PM2 PM3 PM4 PX1 PX2 PX3 PX4 R11 R4 R5 R6 R42 R43 R13 R7 R8 R9 R10 R12 R15 R17 R18 R19 R20 R28 R29 R14 R16 (Not populated) R34 R33 R1 R21 R22 R23 R24 R25 R2 R3 R36 R37 R26 R30 Part Description Connector Inter-board, 7mm Height, 140 pin, Plug, SMD Connector Inter-board 140 pin, Receptacle, SMD Resistor 124 K, 5%, SMD 1206, 1/8W Resistor 75 , 5%, SMD 1206, 1/ 8W Resistor 4.7 K, 5%, SMD 1206, 1/8W Resistor 47 K, 1%, SMD 1206, 1/8W Resistor 200 K, 5%, SMD 1206, 1/8W Resistor 20 M, 5%, SMD 1206, 1/8W Resistor 0 , SMD 1206, 1/8W Resistor 0 , SMD 1206, 1/8W Resistor 143 , 5%, SMD 1206, 1/ 8W Manufacturer MOLEX MOLEX RODERSTEIN DRALORIC Part # 53481-1409 52760-1409 D25 124K FCS CR1206 100 75RJ IN IM EL Resistor 50, 8W Resistor 243 , 1%, SMD 1206, 1/ 8W Resistor 330 , 5%, SMD 1206, 1/ 8W DALE DRALORIK DRALORIK PR Resistor 191 , 1%, SMD 1206, 1/ 8W Resistor 22.1K,1%, SMD 1206, 1/8W Resistor 100 , 1%, SMD 1206, 1/ 8W 1%, SMD 1206, 1/ R31 R38 R39 R40 R41 R46 R47 R48 R32 R 35 R44 R45 RN1 RN2 RN3 RN5 RN6 RN4 Resistor 69.8 , 1%, SMD 1206, 1/8W Resistor Network 75 , 5%, 8 resistors, 16 pin. Resistor Network 1K, 5%, 8 resistors, 16 pin. Resistor Network 4.7K, 5%, 8 resistors, 14 pin. 56 MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y BOURNS KYOCERA CR32 473JT RODERSTEIN RODERSTEIN TYOHM TYOHM RODERSTEIN RODERSTEIN D25 020MJS DALE BOURNS BOURNS DALE CR1206 JW 472E D25 200K FCS RMC 1206 0E 1% RMC 1206 0E 1% D25 143R FCS D25 243R FCS 1002G43300J D25-22K1SCS D25-100RFCS 4816P 001 750J D OMC 1401 472 SOMC1603-102GTR MOTOROLA Support Information TABLE 5-18. MPC860TFADSDB Part List Reference Designation T1S U1 U2 Part Description Transistor TMOS, Dual, 3A 4 MHz Clock generator. 3.3V, CMOS levels. MPC860T, 19 X 19, 357 pin BGA. Manufacturer Motorola MGR-Tech Motorola Part # MMDF3N03HD MH14FAD 3.3V 4.00MHz MPC860 or MPC860SAR or MPC860T HFBR-5103 or HFBR-5105 U4 U5 U6 U7 U8 Y1 Y2 F-ETHERNET TRANCEIVER LAN Magnetics Quad Low Voltage CMOS AND Gate. Voltage level detector. Range 1.795V to 2.005V. O.D. output. IN CTS PD Variable Output Voltage regulator. 25Mhz CRYSTAL IM EL PR MOTOROLA Crystal resonator, 32.768 KHz, Frequency tolerance 30 ppm, Drive-level - 10W Max, Shunt capacitance - 2pF Max., Load capacitance - 12.5pF Max., Equivalent Series Resistance 35 K Max. 14 pin PC Socket 361 pin 19 X 19 BGA ZIF Socket MPC860TFADS Daughter Board Design Specification--Rev 0.1 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE AR Y LENELONE LXT970 HALO TG-223506 74LCX08D Motorola Seiko Motorola LM317MDT CTX093 RALTRON 110-93-314 ENPLUS U3 OPTICAL TRANCEIVER This device is not mounted on the board. if the user wants to use fiber optic he should populate it. HP S-8051HN-CD-X RSM-200-32.768 KHZ BGA357(441)-1.27-01 57 |
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