View MAX5773-MAX5775_990483.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3686; Rev 0; 5/05
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
General Description
The MAX5773/MAX5774/MAX5775 32-channel, 14-bit, voltage-output, digital-to-analog converters (DACs) are ideal for applications requiring a high number of programmable voltages. The MAX5773/MAX5774/ MAX5775 can be programmed to calibrate the 14-bit input data word for gain and offset errors before updating the DAC output. An SPITM-/QSPITM-/MICROWIRETM- or DSP-compatible serial interface controls the MAX5773/MAX5774/ MAX5775. Each DAC channel has its own input, gain, and offset register. These three registers pass data through one of the two multiplier accumulator units (MACs), resulting in a voltage output corrected for gain and offset error. Each DAC channel has a doublebuffered input structure to minimize the digital-noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. The DAC outputs update independently or simultaneously with a single software or hardware command. The MAX5773/MAX5774/MAX5775 also provide a digital output (DOUT) that allows for readback or daisy chaining of multiple devices. All DAC outputs are buffered and drive 10k in parallel with 100pF. The MAX5773 has a 0 to +10V output range; the MAX5774 has a -2.5V to +7.5V output range; and the MAX5775 has a -5V to +5V output range. The MAX5773/MAX5774/MAX5775 are available in a 68-pin, 10mm x 10mm, TQFN package and a 64-pin, 12mm x 12mm, TQFP package. The MAX5773/ MAX5774/MAX5775 are specified over the 0C to +85C temperature range. Refer to the MAX5753/MAX5754/ MAX5755 data sheet for similar 14-bit, 32-channel DACs without offset and gain calibration. Guaranteed Monotonic to 14 Bits 32 Individual DACs in a 10mm x 10mm, 68-Pin TQFN Package or 12mm x 12mm, 64-Pin TQFP Package Output Voltage Ranges 0 to +10V (MAX5773) -2.5V to +7.5V (MAX5774) -5V to +5V (MAX5775) Buffered Voltage Outputs Drive 10k || 100pF Glitch-Free Power-Up SPI/QSPI/MICROWIRE- and DSP-Compatible 33MHz Serial Interface
Features
Offset and Gain Correction for Each DAC Channel
MAX5773/MAX5774/MAX5775
Ordering Information
PART MAX5773UTK* MAX5773UCB* MAX5774UTK MAX5774UCB MAX5775UTK* MAX5775UCB* PIN-PACKAGE 68 TQFN-EP** 64 TQFP 68 TQFN-EP** 64 TQFP 68 TQFN-EP** 64 TQFP OUTPUT VOLTAGE RANGE (V) 0 to +10 0 to +10 -2.5 to +7.5 -2.5 to +7.5 -5 to +5 -5 to +5 PKG CODE T6800-3 C64-12 T6800-3 C64-12 T6800-3 C64-12
Note: All devices are specified over the 0C to +85C temperature range. *Future product--contact factory for availability. **EP = Exposed paddle.
Pin Configurations
OUT23 OUT22 OUT21 OUT19 OUT18 OUT26 OUT25 OUT24 OUT20 OUT17 AGND AVCC OUT16
TOP VIEW
N.C.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS
N.C.
32 VSS 31 AVDD 30 REF 29 REFGND 28 GS1 27 RESET 26 LDAC 25 DGND 24 DVDD 23 DIN 22 SCLK 21 DOUT 20 CS 19 DSP 18 GS2 17 DGND
Applications
Automatic Test Systems Optical Router Controls Industrial Process Controls Arbitrary Function Generators Avionics Equipment Minimum Component Count Analog Systems Digital Offset/Gain Adjustment
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
N.C. 49 OUT27 50 OUT28 51 OUT29 52 OUT30 53 OUT31 54 AVCC 55 REFGND 56 AVDD 57 OUT15 58 OUT14 59 OUT13 60 OUT12 61 OUT11 62 OUT10 63 N.C. 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MAX5773 MAX5774 MAX5775
I.C.
AVCC
VSS
OUT6
OUT5
OUT4
AGND
OUT9
OUT8
OUT7
OUT3
OUT2
OUT1
OUT0
TQFP
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
DVDD
N.C.
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
ABSOLUTE MAXIMUM RATINGS
AVCC to VSS, AGND, DGND, REFGND ..................-0.3V to +12V VSS to AGND, DGND................................................-6V to +0.3V AVDD to AGND, DGND, REFGND ............................-0.3V to +6V DVDD to AGND, DGND, REFGND .........................-0.3V to AVDD AGND to DGND.....................................................-0.3V to +0.3V REF to AGND, DGND, REFGND ....-0.3V to the lower of (AVDD + 0.3V) and +6V REFGND to AGND.................................................-0.3V to +0.3V Digital Inputs to AGND, DGND, REFGND .............-0.3V to the lower of (DVDD + 0.3V) and +6V DOUT to DGND .....-0.3V to the lower of (DVDD + 0.3V) and +6V OUT_ to VSS..........-0.3V to the lower of (AVCC +0.3V) and +12V GS1, GS2 to AGND .....................................................-1V to +1V GS1, GS2 to VSS.......................................................-0.3V to +6V Maximum Current into REF...............................................10mA Maximum Current into Any Other Pin ...............................50mA Maximum Power Dissipation (TA = +70C) 68-Pin TQFN (derate 50.0mW/C above +70C) .............4.0W 64-Pin TQFP (derate 25.0mW/C above +70C)..............2.0W Operating Temperature Range ..............................0C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5773 (0 to +10V Output Voltage Range)
(AVCC = +10.5V to +11V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS1 = GS2 = 0, VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity Differential Nonlinearity Offset Error (Without Digital Calibration) Offset Error (with Digital Calibration) Gain Error (Without Digital Calibration) Gain Error (with Digital Calibration) Gain Temperature Coefficient DC Crosstalk Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output-Noise Spectral Density at 1kHz (Note 5) Major carry transition (Note 6) Full-scale code tS VSS = -0.5V, AVCC = +10V (Note 4) Full-scale change to 0.5 LSB N INL DNL VOS VOS-CAL (Note 2) Guaranteed monotonic VSS = -0.5V, AVCC = +10V (Note 3) VSS = -0.5V, AVCC = +10V (Note 3) 8 300 0.1 0.05 20 50 20 1 5 120 25 250 250 0.5 14 1 4 1 40 Bits LSB LSB mV V %FSR %FSR ppm FSR/C V s V/s nV-s nV-s nV-s nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (fSCLK = 20MHz)
2
_______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5773 (0 to +10V Output Voltage Range)(continued)
(AVCC = +10.5V to +11V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS1 = GS2 = 0, VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output-Voltage Range Resistive Load to Ground Capacitive Load to Ground DC-Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUTS (GS1 and GS2) Input-Voltage Range Ground-Sense Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range VREF Referred to REFGND DIGITAL INPUTS (CS, SCLK, DIN, LDAC, RESET, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage AVDD DVDD VOL VOH IL COUT 10 ISINK = 1mA ISOURCE = 0.2mA 0.8 x DVDD 10 0.4 V V A pF VIH VIL CIN IIN Digital inputs = 0 or DVDD 10 1 +2.7V DVDD + 3.6V +3.6V < DVDD +5.25V 0.7 x DVDD 2.4 0.8 V pF A V 1 2.900 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -0.5V Relative to AGND -0.5 0.995 70 1.000 +0.5 1.005 V V/V k -5 0.1 +5 mA SYMBOL CONDITIONS VSS = -0.5V, AVCC = +10.5V (Note 1) MIN 0 10 50 100 TYP MAX 10 UNITS V k pF
MAX5773/MAX5774/MAX5775
ANALOG OUTPUTS (OUT0 to OUT31)
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC VSS AVCC - VSS 4.75 2.7 10 -0.5 11 0 11 5.25 AVDD V V V V V
_______________________________________________________________________________________
3
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
ELECTRICAL CHARACTERISTICS--MAX5773 (0 to +10V Output Voltage Range)(continued)
(AVCC = +10.5V to +11V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS1 = GS2 = 0, VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Analog Supply Current SYMBOL AIDD CONDITIONS VOUT0 through VOUT31 = 0 Software shutdown DVDD = +5V, VIH = DVDD, VIL = 0, fSCLK = 20MHz, continuous writethrough Digital Supply Current DIDD DVDD = +5V, VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz, continuous writethrough Software shutdown Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AICC VOUT0 through VOUT31 = 0 Software shutdown VSS = -0.5V VOUT0 through VOUT31 = 0 Software shutdown PSRR MIN TYP 10 10 2.5 5.0 75 4 20 -4 -20 -95 -10 10 3.5 mA 6.5 nA mA A mA A dB MAX 15 UNITS mA A
ISS
ELECTRICAL CHARACTERISTICS--MAX5774 (-2.5V to +7.5V Output Voltage Range)
(AVCC = +7.75V to +8.25V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 1000h. VREF = +3.0V, RL = , CL= 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity Differential Nonlinearity Offset Error (Without Digital Calibration) Offset Error (with Digital Calibration) Gain Error (Without Digital Calibration) Gain Error (with Digital Calibration) Gain Temperature Coefficient DC Crosstalk Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough (Note 5) tS VSS = -3.25V, AVCC = +7.75V (Note 4) Full-scale change to 0.5 LSB N INL DNL VOS VOS-CAL (Note 2) Guaranteed monotonic VSS = -3.25V, AVCC = +7.75V (Note 3) VSS = -3.25V, AVCC = +7.75V (Note 3) 8 300 0.1 0.05 20 50 20 1 5 250 0.5 14 1 4 1 40 Bits LSB LSB mV V %FSR %FSR ppm FSR/C V s V/s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (fSCLK = 20MHz)
4
_______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5774 (-2.5V to +7.5V Output Voltage Range) (continued)
(AVCC = +7.75V to +8.25V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 1000h. VREF = +3.0V, RL = , CL= 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output-Noise Spectral Density at 1kHz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range Resistive Load to Ground Capacitive Load to Ground DC Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUTS (GS1 and GS2) Input-Voltage Range Ground-Sense Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range VREF Referred to REFGND DIGITAL INPUTS (CS, SCLK, DIN, LDAC, RESET, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance Output-Amplifier Positive Supply Voltage VOL VOH IL COUT 10 ISINK = 1mA ISOURCE = 0.2mA 0.8 x DVDD 10 0.4 V V A pF VIH VIL CIN IIN Digital inputs = 0 or DVDD 10 1 +2.7V DVDD +3.6V +3.6V < DVDD +5.25V 0.7 x DVDD 2.4 0.8 V pF A V 1 2.900 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -2.75V Relative to AGND -0.5 0.993 70 1.000 +0.5 1.005 V V/V k -5 0.1 +5 mA VSS = -2.75V, AVCC = +7.75V (Note 1) -2.5 10 50 100 +7.5 V k pF SYMBOL (Note 6) Full-scale code CONDITIONS Major carry transition MIN TYP 120 25 250 MAX UNITS nV-s nV-s nV/Hz
MAX5773/MAX5774/MAX5775
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC 7.50 8.25 V
_______________________________________________________________________________________
5
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
ELECTRICAL CHARACTERISTICS--MAX5774 (-2.5V to +7.5V Output Voltage Range) (continued)
(AVCC = +7.75V to +8.25V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 1000h. VREF = +3.0V, RL = , CL= 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current AVDD DVDD AIDD VOUT0 through VOUT31 = 0 Software shutdown DVDD = +5V,VIH = DVDD, VIL = 0, fSCLK = 20MHz, continuous writethrough Digital Supply Current DIDD DVDD = +5V,VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz, continuous writethrough Software shutdown Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AICC ISS PSRR VOUT0 through VOUT31 = 0 Software shutdown VSS = -2.75V VOUT0 through VOUT31 = 0 Software shutdown SYMBOL VSS AVCC - VSS 4.75 2.7 10 10 2.0 4.5 75 4 20 -4 -20 -95 -10 8 3.0 mA 6.0 nA mA A mA A dB CONDITIONS MIN -3.25 TYP MAX -2.50 11 5.25 AVDD 15 UNITS V V V V mA A
ELECTRICAL CHARACTERISTICS--MAX5775 (-5V to +5V Output Voltage Range)
(AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 2000h. VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity Differential Nonlinearity Offset Error (Without Digital Calibration) Offset Error (with Digital Calibration) Gain Error (Without Digital Calibration) Gain Error (with Digital Calibration) Gain Temperature Coefficient N INL DNL VOS VOS-CAL (Note 2) Guaranteed monotonic VSS = -5.25V, AVCC = +5.25V (Note 3) VSS = -5.25V, AVCC = +5.25V (Note 3) 8 300 0.1 0.05 20 0.5 14 1 4 1 40 Bits LSB LSB mV V %FSR %FSR ppm FSR/C SYMBOL CONDITIONS MIN TYP MAX UNITS
6
_______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5775 (-5V to +5V Output Voltage Range) (continued)
(AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 2000h. VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC Crosstalk Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output-Noise Spectral Density at 1kHz ANALOG OUTPUTS (OUT0 to OUT31) Output-Voltage Range Resistive Load to Ground Capacitive Load to Ground DC Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUTS (GS1 and GS2) Input-Voltage Range Ground-Sense Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range VREF Referred to REFGND DIGITAL INPUTS (CS, SCLK, DIN, LDAC, RESET, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High VOL VOH ISINK = 1mA ISOURCE = 0.2mA 0.8 x DVDD 0.4 V V VIH VIL CIN IIN Digital inputs = 0 or DVDD 10 1 +2.7V DVDD +3.6V +3.6V < DVDD 5.25V 0.7 x DVDD 2.4 0.8 V pF A V 1 2.900 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -5.25V Relative to AGND -0.5 0.995 70 1.000 +0.5 1.005 V V/V k -5 0.1 +5 mA VSS = -5.25V, AVCC = +5.25V (Note 1) -5 10 50 100 +5 V k pF (Note 5) Major carry transition (Note 6) Full-scale code tS SYMBOL CONDITIONS VSS = -5.50V, AVCC = +5.25V (Note 4) Full-scale change to 0.5 LSB MIN TYP 50 20 1 5 120 25 250 MAX 250 UNITS V s V/s nV-s nV-s nV-s nV/Hz
MAX5773/MAX5774/MAX5775
DYNAMIC CHARACTERISTICS (fSCLK = 20MHz)
_______________________________________________________________________________________
7
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
ELECTRICAL CHARACTERISTICS--MAX5775 (-5V to +5V Output Voltage Range) (continued)
(AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS1 = GS2 = 0, program the offset DAC to 2000h. VREF = +3.0V, RL = , CL = 50pF referenced to VSS, TA = TMIN to TMAX, SCLK = 0, all offset and gain registers = 0000h, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Tri-State Leakage Current Tri-state Output Capacitance Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current AVDD DVDD AIDD VOUT0 through VOUT31 = 0 Software shutdown DVDD = +5V, VIH = DVDD, VIL = 0, fSCLK = 20MHz, continuous writethrough Digital Supply Current DIDD DVDD = +5V, VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz, continuous writethrough Software shutdown Output-Amplifier Positive Supply Current AICC VOUT0 through VOUT31 = 0 Software shutdown VOUT0 through VOUT31 = 0 Software shutdown SYMBOL IL COUT 10 CONDITIONS MIN TYP MAX 10 UNITS A pF
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC VSS AVCC - VSS 4.75 2.7 10 10 2.5 5.0 75 4 20 -4 -20 -95 -10 10 3.5 mA 6.5 nA mA A mA A dB 4.75 -5.50 5.50 -4.75 11 5.25 AVDD 15 V V V .V V mA A
Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio
ISS
VSS = -5.25V
PSRR
TIMING CHARACTERISTICS
(Figures 1 and 2, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall to CS Fall Setup Time SYMBOL fSCLK tCH tCL tSCS CONDITIONS MIN 0 10 10 6 TYP MAX 33 UNITS MHz ns ns ns
8
_______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
TIMING CHARACTERISTICS (continued)
(Figures 1 and 2, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CS Fall to SCLK Fall Setup Time CS Rise to SCLK Fall SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Fall to DOUT Fall SCLK Fall to DOUT Rise CS Pulse-Width High CS Pulse-Width Low LDAC Pulse-Width Low RESET Pulse-Width Low SYMBOL tCSS tCS1 tCS2 tDS tDH tSCL tSDH tCSPWH tCSPWL tLDAC tCLR (Note 7) Load capacitance = 20pF Load capacitance = 20pF 50 20 20 50 At end of cycle in SPI mode only CONDITIONS MIN 5 15 0 10 2 20 20 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
MAX5773/MAX5774/MAX5775
TIMING CHARACTERISTICS
(Figures 1 and 2, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall to CS Fall Setup Time CS Fall to SCLK Fall Setup Time CS Rise to SCLK Fall SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Fall to DOUT Fall SCLK Fall to DOUT Rise CS Pulse-Width High CS Pulse-Width Low LDAC Pulse-Width Low RESET Pulse-Width Low SYMBOL fSCLK tCH tCL tSCS tCSS tCS1 tCS2 tDS tDH tSCL tSDH tCSPWH tCSPWL tLDAC tCLR (Note 7) Load capacitance = 20pF Load capacitance = 20pF 50 20 20 50 At end of cycle in SPI mode only CONDITIONS MIN 0 10 10 10 10 18 0 10 2 25 25 TYP MAX 25 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5:
AVCC should be at least 0.25V higher than the maximum output voltage required from the DAC. Linearity guaranteed for full code range. Offset error is measured at code 0. Gain error is measured at code 3FFFh. DC crosstalk is the change in the output level of one DAC at midscale in response to the full-scale output change of all other DACs. Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the device is not being written to. It is measured with a worst-case change on the digital inputs. Note 6: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. Note 7: In DSP mode, maintain the maximum CS pulse width low to 16 SCLK cycles.
_______________________________________________________________________________________
9
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5773 toc01
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5773 toc02
1.0 0.8 0.6 0.4
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2000 4000 6000 10,000 14,000 18,000 8000 12,000 16,000 INPUT CODE
2000 0 4000
6000
10,000 14,000 18,000 8000 12,000 16,000 INPUT CODE
WORST-CASE INL vs. TEMPERATURE
MAX5773 toc03
WORST-CASE DNL vs. TEMPERATURE
MAX5773 toc04
0.40 0.35 WORST-CASE INL (LSB) 0.30 0.25 0.20 0.15 0.10 0.05 0 0 17 34 51 68 AVCC = +7.75V VSS = -3.25V
0.124 0.122 WORST-CASE DNL (LSB) 0.120 0.118 0.116 0.114 0.112 0.110 AVCC = +7.75V VSS = -3.75V 0 17 34 51 68
85
85
TEMPERATURE (C)
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX5773 toc05
OFFSET ERROR vs. TEMPERATURE
1.5 OFFSET ERROR (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 DIGITAL CALIBRATION AT TA = +25C VSS = 0V, AVCC = +10.5V OFFSET CODE = 512
MAX5773 toc06
1.0 0.5 0 OFFSET ERROR (mV) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 0 17 34 51 68 WITHOUT DIGITAL CALIBRATION VSS = 0V, AVCC = +10.5V OFFSET CODE = 512
2.0
85
0
17
34
51
68
85
TEMPERATURE (C)
TEMPERATURE (C)
10
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
GAIN ERROR vs. TEMPERATURE
MAX5773 toc07
GAIN ERROR vs. TEMPERATURE
1.5 1.0 GAIN ERROR (mV) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 17 34 51 68 85 DIGITAL CALIBRATION AT TA = +25C VSS = 0V, AVCC = +10.5V
MAX5773 toc08
5.0 4.5 4.0 GAIN ERROR (mV) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 17 34 51 68 WITHOUT DIGITAL CALIBRATION VSS = 0V, AVCC = +10.5V
2.0
85
TEMPERATURE (C)
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5773 toc09
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
0.9 0.8 0.7 DVDD (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 DVDD = +2.7V SCLK = 25MHz VSS = -0.5V CONTINUOUS WRITETHROUGH USING CORRECTED WORD (FOR OFFSET AND GAIN ERRORS) TO CHANNEL PAIRS 0 AND 16 0 17 34 51 68 85
MAX5773 toc10
11.0 10.8 10.6 10.4 AVDD (mA) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 0 17 34 51 68
1.0
85
TEMPERATURE (C)
TEMPERATURE (C)
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
2.8 2.6 2.4 DVDD (mA) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0 17 34 51 68 85 DVDD = +5V SCLK = 33MHz VSS = -0.5V CONTINUOUS WRITETHROUGH USING CORRECTED WORD (FOR OFFSET AND GAIN ERRORS) TO CHANNEL PAIRS 0 AND 16
MAX5773 toc11
3.0
CHANNEL-TO-CHANNEL CROSSTALK FOR A DAC PAIR SWITCHING AND RESULTING CROSSTALK INTO ONE DAC toc12 MAX5773
OUT_ MIDSCALE (GS2) 20mV/div
0000h to 3FFFh GLITCH SUPPRESSION AND SCLK ACTIVE 2s/div
OUT 9 AND OUT 25 (GS1) 5V/div
TEMPERATURE (C)
______________________________________________________________________________________
11
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
DIGITAL FEEDTHROUGH (5V CLOCK)
MAX5773 toc13
LARGE-SIGNAL STEP RESPONSE (LOW TO HIGH)
MAX5773 toc14
LARGE-SIGNAL STEP RESPONSE (HIGH TO LOW)
MAX5773 toc15
SCLK 5V/div
CS 2V/div
CS 2V/div
OUT_ 10mV/div DVDD = +5V 400ns/div 2s/div
OUT_ 5V/div
OUT_ 5V/div
2s/div
NOISE VOLTAGE DENSITY
MAX5773 toc16
MAJOR CARRY TRANSITION 1FFFh TO 2000h WITH GLITCH SUPPRESSION
MAX5773 toc17
MAJOR CARRY TRANSITION 2000h TO 1FFFh WITH GLITCH SUPPRESSION
MAX5773 toc18
1000
CS 2V/div
CS 2V/div
NOISE (nV/Hz)
100
10
OUT_ 20mV/div
OUT_ 20mV/div
1 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
1s/div
1s/div
DVDD SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE
10,000 SUPPLY CURRENT (A) 1000 100 10 1 0.1 0.01 0.001 0.0001 0 1 2 3 4 5 LOGIC INPUT VOLTAGE (V) ALL LOGIC INPUTS CONNECTED DVDD = +5V
MAX5773 toc19
TOTAL SUPPLY SHUTDOWN CURRENT vs. TEMPERATURE
MAX5773 toc20
100,000
30 25 SHUTDOWN CURRENT (A) 20 15 10 5 0 0 17 34 51 AIDD + DIDD + AICC + ISS
AVCC = +7.75V VSS = -2.75V 68 85
TEMPERATURE (C)
12
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
Pin Description
PIN 68 TQFN 1, 16, 34, 35, 36, 51, 52, 53, 68 2, 50, 59 3 4 5 6 7 8 9 10, 46 11 12, 33, 47 13 14 15 17, 25 18, 26 19 64 TQFP 15, 33, 34, 49, 64 1, 48, 55 2 3 4 5 6 7 8 9, 44 10 11, 32, 45 12 13 14 16, 24 17, 25 18 NAME N.C. AVCC OUT9 OUT8 OUT7 I.C. OUT6 OUT5 OUT4 AGND OUT3 VSS OUT2 OUT1 OUT0 DVDD DGND GS2 FUNCTION No Connection. Not internally connected. Output-Amplifier Positive Supply Input. Bypass to AGND with a 0.1F capacitor. DAC9 Buffered Analog Output Voltage DAC8 Buffered Analog Output Voltage DAC7 Buffered Analog Output Voltage Internally Connected. Do not make any connections to I.C. DAC6 Buffered Analog Output Voltage DAC5 Buffered Analog Output Voltage DAC4 Buffered Analog Output Voltage Analog Ground DAC3 Buffered Analog Output Voltage Bypass to AGND with a 0.1F capacitor DAC2 Buffered Analog Output Voltage DAC1 Buffered Analog Output Voltage DAC0 Buffered Analog Output Voltage Digital Power-Supply Input. Bypass to DGND with a 0.1F capacitor. Digital Ground Ground-Sense Analog Input 2. Offsets the DAC amplifier outputs OUT0, OUT1, OUT2, OUT16, OUT17, and OUT18 by 0.5V to compensate for a remote system ground potential difference. Digital Serial-Interface Mode-Select Input. Drive low for DSP interface mode. Drive high for SPI interface mode. Active-Low Digital Chip-Select Input Digital Serial Data Output. Use DOUT to daisy chain or read the contents of the internal registers. DOUT data clocks out on the falling edge of SCLK, MSB first. Digital Serial Clock Input Digital Serial Data Input. Data clocks in on the falling edge of SCLK. Active-Low Digital Load DAC Input. Drive this asynchronous input low to transfer the contents of the input register to their respective DAC registers and update all DAC outputs accordingly. Active-Low Reset Input. Drive this asynchronous input low to initiate a power-on reset. See the Power-On Reset section for further information. Ground-Sense Analog Input 1. Offsets the DAC amplifier outputs OUT3-OUT15 and OUT19-OUT31 by 0.5V to compensate for a remote system ground potential difference. Reference Ground
MAX5773/MAX5774/MAX5775 MAX5773/MAX5774/MAX5775
20 21 22 23 24 27
19 20 21 22 23 26
DSP CS DOUT SCLK DIN LDAC
28
27
RESET
29 30, 60
28 29, 56
GS1 REFGND
______________________________________________________________________________________
13
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Pin Description
PIN 68 TQFN 31 32, 61 37 38 39 40 41 42 43 44 45 48 49 54 55 56 57 58 62 63 64 65 66 67 EP 64 TQFP 30 31, 57 35 36 37 38 39 40 41 42 43 46 47 50 51 52 53 54 58 59 60 61 62 63 -- NAME REF AVDD OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 EP FUNCTION Analog Reference Voltage Input. Connect a +3V reference to REF and bypass to REFGND with a 0.1F capacitor. Analog Power-Supply Input. Bypass to AGND with a 0.1F capacitor. DAC16 Buffered Analog Output Voltage DAC17 Buffered Analog Output Voltage DAC18 Buffered Analog Output Voltage DAC19 Buffered Analog Output Voltage DAC20 Buffered Analog Output Voltage DAC21 Buffered Analog Output Voltage DAC22 Buffered Analog Output Voltage DAC23 Buffered Analog Output Voltage DAC24 Buffered Analog Output Voltage DAC25 Buffered Analog Output Voltage DAC26 Buffered Analog Output Voltage DAC27 Buffered Analog Output Voltage DAC28 Buffered Analog Output Voltage DAC29 Buffered Analog Output Voltage DAC30 Buffered Analog Output Voltage DAC31 Buffered Analog Output Voltage DAC15 Buffered Analog Output Voltage DAC14 Buffered Analog Output Voltage DAC13 Buffered Analog Output Voltage DAC12 Buffered Analog Output Voltage DAC11 Buffered Analog Output Voltage DAC10 Buffered Analog Output Voltage Exposed Paddle. Connect to VSS.
Detailed Description
The MAX5773/MAX5774/MAX5775 are 32-channel, 14bit, voltage-output DACs. All devices accept a +3.0V external reference input at REF. An internal offset DAC allows all outputs to be offset up to -5V (see Table 1). A 33MHz SPI-/QSPI-/MICROWIRE- or DSP-compatible serial interface (see Figure 1) controls the MAX5773/MAX5774/MAX5775. Use DSP to select the DSP mode or the SPI/QSPI/MICROWIRE mode. Each DAC has a double-buffered input structure to minimize the digital-noise feedthrough from the digital inputs to the outputs. The two buffers are organized as
14
an input register followed by a DAC register. Input registers update the DAC registers independently or simultaneously with a single software or hardware command. Each DAC channel has its own offset and gain registers that calibrate offset and gain errors for a given channel. The MAX5773/MAX5774/MAX5775 are divided into two banks of 16 channels to provide real-time calibration of channel pairs. Channel bank pairs are ordered as (bank 0:bank 1) OUT0:OUT16, OUT1:OUT17 ... OUT14:OUT30, OUT15:OUT31. An offset DAC allows all the outputs to be offset up to -5V and dual ground-sensing inputs (GS1 and GS2) allow the output voltages to be referenced to remote
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
tCL tCH
SCLK
X
X
1 tDH
2
4
26
32
DIN tSCS
C3 tDS tCSS
C2
C0
D0 tCS2 tCS1
CS (C MODE) tCSPWH CS (DSP MODE)
tCSPWL
Figure 1. Serial-Interface Timing
Table 1. Offset DAC Codes
PART MAX5773 MAX5774 MAX5775 D13 0 0 1 D12 0 1 0 D11 0 0 0 D10 0 0 0 D9 0 0 0 D8 0 0 0 D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0 S1* 0 0 0 S0* 0 0 0
*S1 = S0 = 0 for proper operation.
grounds (see the Functional Diagram). Three output channels of each channel bank (bank 0 and bank 1) are referenced to GS2 (OUT0, OUT1, OUT2 in bank 0, and OUT16, OUT17, OUT18 in bank 1). All other output channels are referenced to GS1. The MAX5773/MAX5774/MAX5775 analog and digital sections have separate power inputs (AV DD and DVDD). Separate power inputs are also provided for the output buffers (AVCC and VSS). Proprietary deglitch circuitry prevents output glitches at power-up and eliminates the need for power sequencing. A softwareshutdown mode facilitates efficient power management. When shut down, the MAX5773/MAX5774/ MAX5775 consume 50A (typ) of supply current. The MAX5773/MAX5774/MAX5775 have a 5s (typ) wake-up time from shutdown mode to normal DAC operation. All DACs provide buffered outputs that can drive 10k in parallel with 100pF. The MAX5773 has a 0 to +10V output range; the MAX5774 has a -2.5V to +7.5V output range; and the MAX5775 has a -5V to +5V output range.
External Reference Input (REF)
The REF voltage sets the full-scale output voltage for all 32 DACs. REF accepts a +3.0V 3% input. Reference voltages outside these limits result in a degradation of device performance. REF is a buffered input. The input impedance is 1M minimum and it does not vary with code. Use a highaccuracy, low-noise voltage reference such as the MAX6126AASA30 (3ppm/C temperature drift and 0.02% initial accuracy) to improve static accuracy. REF does not accept AC signals.
Ground Sense (GS1 and GS2)
The MAX5773/MAX5774/MAX5775 include ground-sense inputs (GS1 and GS2) that allow the output voltages to be referenced to a remote ground. The ground-sense input GS1 is connected to channels OUT3-OUT15 (bank 0) and to channels OUT19-OUT31 (bank 1). The groundsense input GS2 is connected to channels OUT0, OUT1, OUT2 (bank 0), and OUT16, OUT17, OUT18 (bank 1). Channels connected to the same ground sense can be accessed in pairs. For example, OUT0 and OUT16 can
15
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
LDAC tLDAC
0.5 LSB tS
OUT_
Figure 2. LDAC Timing
be accessed as a pair (see Figure 3 for pairing of output channels). The ground-sense input voltage range (VGS1 or VGS2) is -0.5V to +0.5V with respect to AGND. VGS is added to the output voltage with unity gain. Ensure that the resulting output voltage is within the valid output voltage range set by the power supplies. Refer to the Output Amplifiers (OUT0-OUT31) section for the effect of the ground-sense inputs on the DAC outputs.
Table 2. Offset DAC Input Data Format
CONTROL BITS C3-C0 0011 ADDRESS BITS A5-A0 110000 DATA BITS D13-D0 and S1, S0* See Table 1 DON'T-CARE BITS 6 Don't-Care Bits XXXXXX
*S1 = S0 = 0 for proper 14-bit operation.
Offset DAC
The MAX5773/MAX5774/MAX5775 feature an offset DAC that determines the output voltage range. While each device provides an allowable output voltage range, the offset DAC determines the endpoint voltages of the range. Table 1 shows the offset DAC code necessary for each device's output-voltage range. The MAX5773/MAX5774/MAX5775 offset DAC can be programmed with any of the three output voltage ranges. The specifications in the Electrical Characteristics table are only guaranteed (production tested) for the offset code associated with each particular part number. The offset DAC is summed with the GS_ input voltage (see the Functional Diagram). Any change in the offset DAC affects all 32 DACs. The offset DAC is also double buffered with an input and DAC register. Software commands for the MAC-bypass for all channels and load-DAC for all channels do not affect the offset DAC. The data format for writing to the offset DAC is: control bits C3-C0 = 0011, address bits A5-A0 = 110000, 14 data bits (and S1, S0), and 6 don't-care bits as shown in Table 2.
Table 3. Software Load-DAC Input Data Format
CONTROL BITS C3-C0 0010 ADDRESS BITS A5-A0 111111 DATA BITS D13-D0 and S1, S0* XXXXXXXXXX XXXX00 DON'T-CARE BITS 6 Don't-Care Bits XXXXXX
*S1 = S0 = 0 for proper 14-bit operation.
Output Amplifiers (OUT0-OUT31)
All DAC outputs are internally buffered. The internal buffers provide gain, improved load regulation, and glitch suppression for the DAC outputs. The output buffers slew at 1V/s and can drive 10k in parallel with 100pF. The output buffers are powered by AVCC and VSS. AVCC and VSS determine the maximum output voltage range of the device. The input code, the voltage reference, the offset DAC output, the voltage on GS1 (or GS2), and the gain of the output amplifier determine the output voltage. Calculate VOUT as follows:
VOUT = GAIN x VREF x (DAC CODE - OFFSET DAC CODE) 214 + VGS _
GAIN = 10/3 for the MAX5773/MAX5774/MAX5775.
16 ______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
CHANNEL-BANK SELECTION ADDRESS BITS
A5 0 0 1 1 A4 0 1 0 1
CHANNEL BANK(S) SELECTED
CHANNEL BANK 0 CHANNEL BANK 1 BOTH CHANNEL BANKS OFFSET CHANNEL AND ALL CHANNEL OPERATION
INPUT REGISTER, DAC REGISTER, GAIN REGISTER, AND OFFSET REGISTER ACCESS* BANK 0 A5 0 A4 0 BANK 1 A5 0 A4 1 BANK 0 AND BANK 1 A5 1 A4 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ADDRESS BITS A3 A2 A1 A0
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8 CHANNEL 9 CHANNEL 10 CHANNEL 11 CHANNEL 12 CHANNEL 13 CHANNEL 14 CHANNEL 15
CHANNEL 16 CHANNEL 17 CHANNEL 18 CHANNEL 19 CHANNEL 20 CHANNEL 21 CHANNEL 22 CHANNEL 23 CHANNEL 24 CHANNEL 25 CHANNEL 26 CHANNEL 27 CHANNEL 28 CHANNEL 29 CHANNEL 30 CHANNEL 31
CHANNEL 0 AND CHANNEL 16 CHANNEL 1 AND CHANNEL 17 CHANNEL 2 AND CHANNEL 18 CHANNEL 3 AND CHANNEL 19 CHANNEL 4 AND CHANNEL 20 CHANNEL 5 AND CHANNEL 21 CHANNEL 6 AND CHANNEL 22 CHANNEL 7 AND CHANNEL 23 CHANNEL 8 AND CHANNEL 24 CHANNEL 9 AND CHANNEL 25 CHANNEL 10 AND CHANNEL 26 CHANNEL 11 AND CHANNEL 27 CHANNEL 12 AND CHANNEL 28 CHANNEL 13 AND CHANNEL 29 CHANNEL 14 AND CHANNEL 30 CHANNEL 15 AND CHANNEL 31
*CHANNEL PAIR ACCESS (BANK 0 AND BANK 1) ONLY PERMITTED FOR WRITETHROUGH, MAC-BYPASS,
AND LOAD-DAC COMMANDS.
ACCESSING OFFSET CHANNEL AND ALL CHANNELS (ADDRESS BITS A5 AND A4 = 11) A3
0 1
ADDRESS BITS A2 A1
0 0 0001 THROUGH 1110 1 1
A0
0 1
REGISTER SELECTED
OFFSET CHANNEL UNUSED ALL CHANNELS (SOFTWARE LOAD-DAC AND MAC-BYPASS COMMANDS ONLY)
ACCESSING CONFIGURATION REGISTER (CONTROL BITS C3-C0 = 1100 OR 1101, ADDRESS BITS A5 AND A4 = 00) ADDRESS BITS REGISTER SELECTED A3 A2 A1 A0
0 0 0 0001 THROUGH 1111 0 CONFIGURATION REGISTER (SEE TABLE 8) UNUSED
Figure 3. Address Space When Accessing DAC Channel Register(s), Offset Register(s), Gain Register(s), and Special Registers ______________________________________________________________________________________ 17
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Load-DAC (LDAC) Input
The MAX5773/MAX5774/MAX5775 feature an activelow LDAC input that allows the outputs (OUT_) to update asynchronously. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to simultaneously update all DAC outputs with data from their respective input registers. Figure 2 shows the LDAC timing with respect to OUT_. A software command can also perform the LDAC operation. To initiate LDAC by software, set control bits C3-C0 = 0010, address bits A5-A0 = 111111, and all data bits to don't care. See Table 3 for the data format. This operation updates all DAC outputs simultaneously. The software load-DAC command for all channels does not affect the offset DAC.
Table 4. MAC-Bypass Data Format
CONTROL BITS C3-C0 0111 ADDRESS BITS A5-A0 See Figure 3 DATA BITS D13-D0 and S1, S0* See Figure 3 DON'T-CARE BITS 6 Don't-Care Bits XXXXXX
*S1 = S0 = 0 for proper 14-bit operation.
Table 5. Reset Data Format
CONTROL BITS C3-C0 1111 ADDRESS BITS A5-A0 XXXXXX DATA BITS D13-D0 and S1, S0* XXXXXXXXXX XXXX00 DON'T-CARE BITS 6 Don't-Care Bits XXXXXX
Software MAC-Bypass
The MAX5773/MAX5774/MAX5775 feature a software MAC-bypass command that loads data into the DAC directly from DIN. Software MAC-bypass loads one DAC, a pair of DACs, or all 32 DACs with a data word (D13-D0 and S1, S0) entered at DIN and the selected DAC output(s) are simultaneously updated. Software MACbypass bypasses gain and offset calibration, sending the input data directly to the DAC register immediately updating the selected DAC outputs. After executing MAC-bypass on a channel(s), previously calibrated data can be reloaded into the DAC by executing software load-DAC or hardware LDAC (see Figure 4). Using software MAC-bypass, the DAC output(s) can be set to the ground-sense value or any arbitrary value within the DAC output voltage range. To activate software MAC-bypass, set control bits C3-C0 = 0111. The address bits (A5-A0) select the DAC(s) to be updated and the data bits (D13-D0) control the DAC output voltage value. Table 4 shows the input data format for the software-controlled MACbypass command.
*S1 = S0 = 0 for proper 14-bit operation.
Table 6. Serial Data Format
CONTROL BITS MSB C3-C0 A5-A0 D13-D0 and S1, S0* ADDRESS BITS DATA BITS 6 DON'TCARE BITS LSB XXXXXX
*S1 = S0 = 0 for proper 14-bit operation.
MAC-BYPASS
DIN
INPUT_ REGISTER
* GAIN OFFSET
+
CALIBRATED DATA REGISTER
DAC_ REGISTER
DAC_
LDAC
Figure 4. MAC-Bypass Functional Diagram
Reset (RESET)
The MAX5773/MAX5774/MAX5775 feature an activelow RESET logic input that asynchronously sets all the registers to code 0000h (power-up state). The serial interface can also issue a software-reset command. Setting the control bits C3-C0 = 1111 performs the same function as driving the logic input RESET low. Table 5 shows the reset data format for the softwarecontrolled reset command. The software reset does not work in daisy-chain mode. Reprogram the offset DAC after asserting a software or hardware reset.
Serial Interface
The MAX5773/MAX5774/MAX5775 allow channel updates either individually or in pairs. This is achieved by dividing the 32 channels into two channel banks, with 16 channels in each bank. Channel bank 0 contains output channels OUT0-OUT15 and channel bank 1 contains channels OUT16-OUT31. A channel from bank 0 is paired with a channel from bank 1 and is ordered as OUT0:OUT16, OUT1:OUT17...OUT14:OUT30, OUT15:OUT31. A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible serial interface controls the MAX5773/MAX5774/ MAX5775. The interface requires a 32-bit command
18
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
word to control the device. The command word consists of 4 control bits, 6 address bits, 14 data bits (and S1, S0 = 00), and 6 don't-care bits. Table 6 shows the general serial data format. The control bits control various write and read commands, as well as the load DAC and MACbypass commands. Table 8 shows the control-bit functions. The address bits select the register(s) to update. Figure 3 shows the address functions. The data bits control the voltage value of the DAC outputs. DIN data is clocked in at the falling edge of SCLK (Figure 1).
MAX5773/MAX5774/MAX5775
Table 7. Gain and Offset Register Input Data Format
CONTROL ADDRESS REGI ST ER BITS BITS (A5-A0) (C3-C0) Offset Register Gain Register 1001 1000 See Figure 3 See Figure 3 DATA BITS (D13-D0 AND S1, S0*) See Figure 3 6 DON'TCARE BITS XXXXXX
Gain and Offset Registers
The MAX5773/MAX5774/MAX5775 contain a gain and offset register associated with each channel to correct
See Figure 3 XXXXXX
*S1 = S0 = 0 for proper 14-bit operation.
Table 8. Control-Bit Functions
4 CONTROL BITS C3 0 C2 0 C1 0 C0 0 CONTROL-BIT DESCRIPTION No operation (NOP). No internal registers change state. The NOP command can be passed to DOUT depending on the state of the configuration register. Address bits A5-A0 and data bits D13-D0 are ignored. This instruction writes and calibrates the 14-bit input data word for gain and offset errors. Drive LDAC low or use a software load-DAC command to update the selected DAC outputs. Software load-DAC command. Updates the output of the selected DAC channel(s). Depending on the address bits, this command updates one DAC output, a pair of DAC outputs, or all the DAC outputs simultaneously. Data bits D13-D0 are ignored. This instruction writes and calibrates the 14-bit input data word for gain and offset errors and immediately updates the DAC outputs for the selected address. Read command. Depending on the address bits, one of the input register values is read back through DOUT. Data bits D13-D0 are ignored. See the Daisy-Chain Operation section. Reserved; do not use. Reserved; do not use. MAC-bypass command. Depending on the address bits, one, two, or all DAC registers are loaded with a 14-bit data word at DIN. The input data is not calibrated for gain and offset errors (see the MAC-Bypass section). Selected DAC output(s) are immediately updated. Loads D13-D0 into one or two of the gain register(s) for the selected address. The data for the selected address is calibrated for gain error. Drive LDAC low or use a software load-DAC command to update the selected DAC outputs. Loads D13-D0 into one or two of the offset register(s) for the selected address. The data for the selected address is calibrated for offset error. Drive LDAC low or use a software load-DAC command to update the selected DAC outputs. Read command. Reads one of the gain registers and presents the data at DOUT. Read command. Reads one of the offset registers and presents the data at DOUT. Write command. Loads D13-D0 into the configuration register. Read command. Reads the contents of the configuration register. Read command. Reads the DAC register for the selected address. Reset instruction.
0
0
0
1
0
0
1
0
0 0 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1
0
0
0
1 1 1 1 1 1 1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
______________________________________________________________________________________
19
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Table 9. Gain Register Code Values
CODE (HEXADECIMAL)
MAX577_ DIN(0) SCLK DOUT(0) CS 1 DSP
GAIN VALUE Unity Gain 0.00061 0.00012 : 0.499938 0.5 : 0.999877 0.999938
0000h 0001h 0002h : 1FFFh 2000h : 3FFEh 3FFFh
CONTROLLER DEVICE
MAX577_ DIN(1) SCLK DOUT(1) CS DSP
Table 10. Offset Register Code Values
MAX577_ DIN(2) SCLK DOUT(2) CS DSP
CODE (HEXADECIMAL) 2000h : 0001h 0000h 3FFFh : 2000h
OFFSET VALUE* FS/2 - 1 LSB : +1 LSB 0 -1 LSB : -FS/2
Figure 5. Daisy-Chain Configuration
*1 LSB = FS/214
real-time gain and offset errors associated with each channel. The gain and offset registers can be accessed individually or in pairs. The gain word range is limited between 0 and 1. The gain word is an unsigned 14-bit data word. A gain word of 0000h is a special mapping to provide a gain of absolute one, i.e., no gain correction. For all the other gain word codes, the amount of gain correction varies proportionally to the gain word's decimal value. For example, a gain word of 0001h is equivalent to a gain of 0.514 and a gain of 3FFFh is equivalent to 1 - 0.514 (see Table 9). To access the gain register, set control bits C3-C0 = 1000 (see Tables 7 and 8). The offset has a range from -FS/2 to + (FS/2 - 1 LSB). The offset word is a 14-bit data word represented in two's complement. For example, an offset word equivalent to 1FFFh would provide an offset of FS/2 - 1 LSB and offset word of 2000h would provide an offset of -FS/2 (see Table 10). To access the offset register, set control bits C3-C0 = 1001 (see Tables 7 and 8).
Configuration Register
The configuration register controls the advanced features of the MAX5773/MAX5774/MAX5775. Write to the configuration register by setting control bits C3-C0 = 1100 and address bits 000000. Table 11 shows the configuration register data format for the D13-D0 data bits. Table 12 shows the commands controlled by the configuration register.
DSP Mode (DSP)
The MAX5773/MAX5774/MAX5775 provide a hardwareselectable DSP-interface mode. The active-low DSP logic input selects the microcontroller (C)-interface or DSP-interface mode. Drive DSP high for C-interface mode. Drive DSP low for DSP-interface mode. DSP mode, when active, allows chip select (CS) to go high before the entire 32-bit command word is clocked in. Figure 1 illustrates serial timing for both C- and DSPinterface modes.
SING
When SING = 0, the MAX5773/MAX5774/MAX5775 are in daisy-chain mode. For daisy-chain operation, set DSP high (C mode) and SING = 0.
20
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Table 11. Configuration Register Data Format
D13 ERRF D12 SING D11 GLT D10 DT D9 SHDN D8 X D7 X 14 DATA BITS D6 D5 X X D4 X D3 X D2 X D1 X D0 X S1 X S0 X
X = Don't care.
Table 12. Configuration Register Commands
DATA BIT NAME DESCRIPTION Error flag. ERRF goes logic high when an invalid command is attempted. ERRF is cleared each time the configuration register is read back to DOUT. Reset-register commands C3-C0 = 1111 reset ERRF. Conditions that trigger ERRF include: * Attempted read of a wrong or invalid address bits A5-A0 * Access to reserved addresses The default is logic low (no error flags); ERRF is read only. Single device. SING determines daisy-chain or stand-alone mode. Logic high sets the device to operate in stand-alone mode or in parallel with other devices. Only 14 data bits (and S1, S0 = 00) are output to DOUT when SING is logic high. When SING is logic low, the entire 32-bit command word is output to DOUT. The default is logic low (daisy-chain mode). For daisy-chain operation, set SING to logic low and DSP must be set high (C mode). SING is read/write. Glitch-suppression enable. The MAX5773/MAX5774/MAX5775 feature glitch-suppression circuitry on the analog outputs that minimizes the output glitch during a major carry transition. A logic low disables the internal glitch-suppression circuitry. Logic high enables glitch suppression, suppressing up to a 120nV-s glitch impulse on the DAC outputs. Default is logic low (glitch suppression is disabled). GLT is read/write. Digital output enable. A logic low enables DOUT. Logic high disables DOUT. Disabling DOUT reduces power consumption and digital noise feedthrough to the DAC outputs from the DOUT output buffer. Default is logic-low (DOUT enabled); DT is read/write. Shutdown. A logic high shuts down all 32 DACs. The logic interface remains active, and the data is retained in the DAC and input registers. Read/write operations can be performed while the device is shut down; however, no changes can occur at the device outputs. Logic-low powers up all 32 DACs. Upon waking up (5s (typ)), the DAC outputs return to the last stored value in the DAC registers. Default is logic low (normal operation). SHDN is read/write. Don't care.
D13
ERRF
D12
SING
D11
GLT
D10
DT
D9
SHDN
D8-D0 and S1, S0
X
In daisy-chain operation, DOUT follows DIN after 32 clock cycles for a write command. For a read command, DOUT provides only the 14 data bits (and S1, S0) in the next cycle following the CS falling edge. Data is provided MSB first at DOUT on the falling edge of SCLK. When SING = 1, the device is in stand-alone mode. To reduce the time it takes to read data out, the read data is provided MSB first at DOUT on the last 16 cycles of the current command word. The device acts on an
incoming command word independent of the rising edge of CS. SING functionality is ignored in DSP mode.
Daisy-Chain Operation
Daisy chain any number of the MAX5773/MAX5774/ MAX5775 devices by connecting the DOUT of one device to DIN of another. Set DSP high and SING = 0 for all devices in the daisy chain (see Figure 5).
______________________________________________________________________________________
21
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
DIN(0) W WD2 W WD1 W WD0 R XX R XX R XX X XX X XX X XX
CS
DOUT(0)
W WD2
W WD1
W
WD0
R
XX
R
XX
R RD0
X
XX
X
XX
DOUT(1)
W WD2
W
WD1 W
WD0
R
XX
R
RD1
R
RD0
X
XX
DOUT(2)
W WD2
W WD1
W WD0
R
RD2
R
RD1
R
RD0
Figure 6. Example 1 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don't care (for X in the data or command position).
DIN(0)
W
WD2 R
XX
W WD0
R
XX
W
WD1
R
XX
X
XX
X
XX
X
XX
CS
DOUT(0)
W WD2
R
XX
W
WD0
R
XX
W
WD1
R
RD0
X
XX
X
XX
DOUT(1)
W WD2
R
RD1
W
WD0
R
XX
W
WD1
R
RD0
X
XX
DOUT(2)
W WD2
R
RD1
W WD0
R
RD2
W
WD1
R
RD0
Figure 7. Example 2 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don't care (for X in the data or command position).
22
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
The MAX5773/MAX5774/MAX5775 support daisy-chain connections of multiple devices. The default (power-up) configuration for the MAX5773/MAX5774/MAX5775 assumes that the device may be part of a daisy chain of devices (SING = 0 and DSP = 1). For a write command, DOUT follows DIN after 32 clock cycles in the default configuration. Figures 6 and 7 show examples of daisy-chain data sequences. GS2) allows the pin electronic voltages to be referenced to the ground potential at the DUT site. An integrated offset and gain feature eliminates the need for costly external circuitry. The pipelined register architecture allows all 32 DACs to be updated simultaneously. This is valuable during test setups, as all values in the tester can be set and then updated in unison with a single command. Accessing the serial interface or the LDAC input updates all 32 DACs simultaneously. The low output noise of the MAX5773/MAX5774/ MAX5775 allows direct connection to the pin electronics, eliminating the cost and PC board area of external filtering. Modern pin electronics integrated circuits (PEICs) are typically fabricated on high-speed processes with low breakdown voltages. Some devices require external protection on their reference inputs to satisfy absolute maximum ratings. The MAX5773/MAX5774/MAX5775 feature outputs that are almost rail-to-rail allowing the AVCC and VSS supplies to be set to voltages within the absolute maximum ratings of the PEIC to guarantee that the PEIC is protected in all situations.
MAX5773/MAX5774/MAX5775
Data Readback
Read the contents of the MAX5773/MAX5774/MAX5775 DAC and configuration registers at DOUT by issuing a read-data command. Control bits C3-C0 configure the device for the read-data modes (see Table 8). The address bits select the register(s) to be read. The contents of the register(s) are clocked out MSB first at DOUT on the falling edge of SCLK. The output data format depends on the status of DSP and SING. Table 13 shows the manner in which data is written to DOUT.
Shutdown Mode
The MAX5773/MAX5774/MAX5775 feature a softwarecontrolled, low-power shutdown mode. Setting bit 9 of the configuration register to a logic high, disables the analog section of the device, forcing the outputs to go high impedance. In shutdown, supply current is reduced to 50A typical. Data stored in the DAC and input registers is retained, and the device outputs return to their previous values upon exiting shutdown. Wake-up time is 5s (typ). The serial interface remains active while the device is in shutdown.
Power Supplies, Bypassing, Decoupling, and Layout
Grounding and power-supply decoupling strongly influence device performance. Digital signals can couple through the reference input, power supplies, and ground connection. Proper grounding and layout can reduce digital feedthrough and crosstalk. For noisy environments, bypass all power supplies with a 0.1F and 1F on each pin, as close to the device as possible. The MAX5773/MAX5774/MAX5775 have four separate power supplies. AVDD powers the internal analog circuitry (except for the output buffers), and DVDD powers the digital section of the device. AVCC and VSS power the output buffers.
Power-Up State
The MAX5773/MAX5774/MAX5775 monitor the four power supplies and maintain the output buffers in a known state until sufficient voltage is available to ensure that no output glitches occur. Once the minimum voltage threshold has been exceeded, the device outputs come up in the clear state (all outputs = 0).
Applications Information
Automatic Test Equipment (ATE) Applications
The MAX5773/MAX5774/MAX5775 include many features suited for ATE applications. These devices are the most highly integrated level-setting solution available for high-density pin electronics boards, and provide the output voltage ranges required by most ATE applications. The offset DAC simultaneously adjusts the voltage range of all 32 DACs, allowing optimization to the application. The remote-sense feature (GS1 and
______________________________________________________________________________________
23
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Table 13. Read-Data Modes with SING and DSP Controls
DSP 0 SING X CONFIGURATION Stand-alone DSP mode READ DATA AT DOUT DOUT provides the 14 data bits only (and S1, S0). The 14 data bits (and S1, S0) are clocked out MSB first at DOUT, on the last 16 clock edges of the current read command word. See Figures 8, 9, and 10. For write commands, DOUT follows DIN after 32 clocks. The entire 32-bit write command word (both command word and data) is clocked out MSB first at DOUT. For read commands, DOUT follows the last 32-bit read command at the falling edge of chip select in the next cycle. For read commands, the 14 data bits (and S1, S0) of the selected register are valid at DOUT starting with the first clock falling edge after the falling edge of CS. See Figures 6 and 7. DOUT provides the 14 data bits (and S1, S0) of the selected register from the current read command word. The 14 data bits (and S1, S0) are clocked out MSB first at DOUT on the last 16 clock edges of the current read command word. See Figures 8, 9 and 10.
1
0
Standard daisy-chain configuration C mode
1
1
Stand-alone C mode
CONTROLLER DEVICE 1 OR 0
MAX577_ DIN SCLK DOUT CS DSP
CONTROLLER DEVICE 1 OR 0
MAX577_ DIN SCLK DOUT CS DSP
Figure 8. Stand-Alone Configuration
MAX577_ DIN SCLK DOUT CS 1 OR 0 DSP
Chip Information
PROCESS: BiCMOS
MAX577_ DIN SCLK DOUT CS 1 OR 0 DSP
Figure 9. Example of a Parallel Configuration with Readback
24
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
DIN(0) C3 C2 C1 C0 A5 A4 A3 1 SCLK CS (C) OR CS (DSP) DOUT(0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SING = 1 (C MODE) OR X (DSP MODE)* *X = DON'T CARE. A2 A1 A0 Sp Sp Sp Sp Sp Sp D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 8 17 24 32
Figure 10. Read Data Timing When Not Daisy Chained
Pin Configurations (continued)
TOP VIEW
OUT23 OUT22 OUT21 OUT19 OUT18 OUT26 OUT25 OUT24 OUT20 OUT17 AGND AVCC OUT16 N.C. N.C. VSS N.C.
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
N.C. 52 N.C. 53 OUT27 54 OUT28 55 OUT29 56 OUT30 57 OUT31 58 AVCC 59 REFGND 60 AVDD 61 OUT15 62 OUT14 63 OUT13 64 OUT12 65 OUT11 66 OUT10 67 N.C. 68
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 N.C. 33 VSS 32 AVDD 31 REF 30 REFGND 29 GS1 28 RESET 27 LDAC
MAX5773 MAX5774 MAX5775
26 DGND 25 DVDD 24 DIN 23 SCLK 22 DOUT 21 CS
EP
20 DSP 19 GS2 18 DGND
N.C.
OUT9
OUT8
OUT7
I.C.
OUT6
OUT5
OUT4
AGND
OUT3
OUT2
OUT1
OUT0
AVCC
N.C.
VSS
TQFN
______________________________________________________________________________________
DVDD
25
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface MAX5773/MAX5774/MAX5775
Functional Diagram
AVCC * GAIN OFFSET INPUT REGISTER 1 DAC1 REGISTER DAC1 3 OF 6 CHANNELS ON GS2 AVCC OUT1 + DAC0 REGISTER DAC0 OUT0
INPUT REGISTER 0
VSS
* GAIN OFFSET
+
VSS
INPUT REGISTER 2
AVCC OUT2
* GAIN OFFSET
+
DAC2 REGISTER
DAC2
VSS ETC. AVCC
INPUT REGISTER 30
* GAIN OFFSET
+
DAC30 REGISTER
DAC30
OUT30
VSS
INPUT REGISTER 31
AVCC * GAIN OFFSET + DAC31 REGISTER DAC31 OUT31
VSS
OFFSET DAC INPUT REGISTER
* GAIN OFFSET
+
OFFSET DAC REGISTER
OFFSET DAC
REF BUFFER
AVCC VSS AGND POWER MANAGEMENT AVDD DVDD DGND REFGND
DIGITAL CONTROL LOGIC
MAX5773 MAX5774 MAX5775
CS SCLK DIN DSP LDAC RESET DOUT
REF
GS2
GS1
26
______________________________________________________________________________________
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
64L TQFP.EPS
MAX5773/MAX5774/MAX5775
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
21-0083
B
1
2
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
21-0083
B
2
2
______________________________________________________________________________________
27
32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN THIN.EPS
MAX5773/MAX5774/MAX5775 MAX5773/MAX5774/MAX5775 MAX5773/MAX5774/MAX5775
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
1
2
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX5773-MAX5775

	To Download MAX5773-MAX5775 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .