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19-3496; Rev 0; 11/04
10Gbps Clock and Data Recovery with Equalizer
General Description
The MAX3992 is a 10Gbps clock and data recovery (CDR) with equalizer IC for XFP optical transmitters. The MAX3992 and the MAX3991 (CDR with limiting amplifier) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps. The MAX3992 recovers the data for up to 12 inches of FR-4 and one connector without the need for a standalone equalizer. The phase-locked loop is optimized for jitter tolerance in SONET, Ethernet, and Fibre-Channel applications. Low jitter generation of 4mUIRMS leaves adequate margin for meeting SONET jitter requirements at the optical output. An AC-based power detector asserts the loss-of-signal (LOS) output when the input signal is removed. An external reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate, is used to aid in frequency acquisition. A loss-of-lock (LOL) indicator is provided to indicate the lock status of the receiver PLL. The MAX3992 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 356mW from a single +3.3V supply and operates over a 0C to +85C temperature range.
Features
Multirate Operation from 9.95Gbps to 11.1Gbps Span Up to 300mm (12in) FR4 with One Connector Low-Output Jitter Generation: 4mUIRMS Low-Output Deterministic Jitter: 4.6psP-P XFI-Compliant Input Interface LOS Indicator LOL Indicator Power Dissipation: 356mW
MAX3992
Ordering Information
PART MAX3992UTG MAX3992UTG+* TEMP RANGE 0C to +85C 0C to +85C PINPACKAGE 24 QFN 24 QFN PKG CODE T2444-4 T2444-4
*Future product--contact factory for availability. +Denotes lead-free package.
Applications
REFCLKFCTL1
Pin Configuration
REFCLK+
9.95Gbps to 11.1Gbps Optical XFP Modules SONET OC-192/SDH STM-64 XFP Transceivers 10.3Gbps/11.1Gbps Ethernet XFP Transceivers 10.5Gbps Fibre-Channel XFP Transceivers 10Gbps DWDM Transceivers 10Gbps XFP Copper Modules High-Speed Backplane Interconnects
TOP VIEW
VTH
LOS 20
24 VCC GND SDISDI+ GND VCC 1 2 3 4 5 6 7 SCLKO+
23
22
21
LOL 19 18 VCC 17 GND 16 SDO15 SDO+ 14 GND 13 VCC 12 CFIL
MAX3992
Typical Application Circuit appears at end of data sheet.
8 SCLKO-
9 FCTL2
10 POL
11 VCC
4mm x 4mm QFN* *THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE.
________________________________________________________________ Maxim Integrated Products
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10Gbps Clock and Data Recovery with Equalizer MAX3992
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +4.0V Input Voltage Levels (SDI+, SDI-, REFCLK+, REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V) CML Output Voltage (SDO+, SDO-, SCLKO+, SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V) Voltage at (CFIL, LOL, VTH, POL, LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 24-Pin QFN (derate 20.8mW/C above +85C) .........1355mW Junction Temperature Range .............................-40C to+150C Storage Temperature Range...........................-55C to +150C Lead Temperature (soldering, 10s) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current DATA INPUT SPECIFICATION (SDI) Single-Ended Input Resistance Differential Input Resistance Single-Ended Input Resistance Matching Differential-Input Return Loss Differential to Common-Mode Conversion Common-Mode Input Return Loss Single-Ended Input Resisitance Differential Input Resistance CML OUTPUT SPECIFICATION (SDO) SDO Differential Output Swing SDO Output Common-Mode Voltage SCLKO Differential Output Single-Ended Output Resistance Differential Output Resistance Single-Ended Output Resistance Matching Differential-Output Return Loss Rise/Fall Time Power-Down Assert Time SDD22 0.1GHz to 5.5GHz (Note 1) 5.5GHz to 12GHz (Note 1) (20% to 80%) (Note 2) (Note 3) 18 13 8 23 30 50 RO 42 84 (Note 2) RL = 50 to VCC 575 650 VCC 0.16 380 50 100 58 116 5 725 mVP-P V mVP-P % dB ps s SDD11 SCD11 SCC11 0.1GHz to 5.5GHz (Note 1) 5.5GHz to 12GHz (Note 1) 0.1GHz to 15GHz 0.1GHz to 15GHz 15 6 17 7 RSE RD 42 84 50 100 58 116 5 % dB dB dB SYMBOL ICC CONDITIONS MIN TYP 108 MAX 145 UNITS mA
REFERENCE CLOCK SPECIFICATION (REFCLK) 84 168 100 200 116 232
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10Gbps Clock and Data Recovery with Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER JITTER SPECIFICATION Jitter Peaking Jitter Transfer Bandwidth JP JBW 120kHz < f 8MHz (Notes 2, 4) f 120kHz (Notes 2, 4) (Notes 2, 4) f = 400kHz Sinusoidal Jitter Tolerance (Notes 2, 4, 6) f = 4MHz f = 80MHz Jitter Generation Serial-Data Output Deterministic Jitter DJ (Notes 2, 4, 7) PRBS 27 - 1 (Note 2) 2.2 0.4 0.4 5.6 >2.8 (Note 5) 0.55 0.45 4 4.6 6.9 13 mUIRMS psP-P UIP-P 0.05 0.25 0.03 8.0 dB MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3992
PLL ACQUISITION/LOCK SPECIFICATION Acquisition Time LOL Assert Time Maximum Frequency Pullin Time Frequency Difference at which LOL Is Asserted Frequency Difference at which LOL Is Deasserted f/fREFCLK f/fREFCLK Figures 1, 2 (Note 2) Figure 1 (Note 2) (Note 8) f = |fVCO / N - fREFCLK|, N = 16 or 64 f = |fVCO / N - fREFCLK|, N = 16 or 64 2 651 500 200 90 s s ms ppm ppm
LOSS-OF-SIGNAL (LOS) SPECIFICATION VTH Control Voltage Range LOS Gain Factor Minimum LOS Assert Voltage Maximum LOS Assert Voltage LOS Gain-Factor Accuracy LOS Hysteresis LOS Gain-Factor Stability LOS Assert Time LOS Deassert Time VTH Input Current LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage VOH VOL Sourcing 30A Sinking 1mA VIH VIL -30 VCC 0.5 0.4 2.0 0.8 +30 V V A V V VTH VTH/ VLOS_ASSERT VLOS_ASSERT VLOS_ASSERT (Notes 2, 9) (Notes 2, 10) (Note 2) Overtemperature and supply Figure 2 (Note 2) Figure 2 (Note 2) -5 -1.5 3.5 -10 3 3.7 150 10 15 50 +1.5 3.9 +10 90 90 +5 500 mV V/V mV mV dB dB % s s A
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10Gbps Clock and Data Recovery with Equalizer MAX3992
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) Note 1: Measured with 100mVP-P differential amplitude. Note 2: Guaranteed by design and characterization. Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0, to the time when the supply current drops to less than 40% of the nominal value. Note 4: Measured with PRBS = 231 - 1. Note 5: Measurement limited by test equipment. Note 6: Jitter tolerance is for BER 10-12, measured with additional 0.1VI deterministic jitter through 15 inches of FR4. (See Typical Operating Characteristics 1.) Note 7: Measured with 50kHz to 80MHz SONET filter. Note 8: Applies on power-up or after standby. Note 9: Over process, temperature and supply. Note 10: Hysteresis is defined as 20Log(VLOS-DEASSERT/VLOS-ASSERT).
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETER Supply Voltage Ambient Temperature Input Data Rate Differential Input Voltage to Transmission Line Output Load Resistance REFCLK Differential Input Voltage Swing REFCLK Duty Cycle REFCLK Frequency REFCLK Accuracy REFCLK Rise/Fall Times (20% to 80%) REFCLK Random Jitter fREFCLK Relative to Rb / 16 or Rb / 64 FREFCLK = Rb / 64 fREFCLK = Rb / 16 Noise bandwidth < 100MHz -100 SYMBOL VCC TA Rb VD RL 0 to 12 inches FR-4 RL is AC-coupled 300 30 Rb / 16 Rb / 64 +100 1200 300 10 400 50 1600 70 CONDITIONS MIN 3.0 0 (See Table 2) 1000 TYP MAX 3.6 +85 UNITS V C Gbps mVP-P mVP-P % GHz ppm ps psRMS
Table 2. Serial Data Rate and Reference Clock Frequency
APPLICATION OC-192 SONET - SDH64 OC-192 SONET over FEC ITU G.709 10Gbps Ethernet, IEEE 802.3ae 10Gbps Ethernet over ITU G.709 DATA RATE (Rb) (Gbps) 9.95328 10.664 10.709 10.3125 11.09573 /16 REFERENCE CLOCK FREQUENCY (MHz) 622.08 666.5 669.3125 644.53125 693.483125 /64 REFERENCE CLOCK FREQUENCY (MHz) 155.52 166.625 167.328125 161.1328125 173.3707813 164.355469
10Gbps Fibre Channel 10.51875 657.421875 Note: The part should be in standby mode when data rates are being switched.
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10Gbps Clock and Data Recovery with Equalizer MAX3992
f/fREFCLK 651ppm 500ppm
LOL ASSERT TIME
ACQUISITION TIME
LOL *ASSERT AND ACQUISITION TIME ARE DEFINED WITH A VALID REFERENCE CLOCK APPLIED.
Figure 1. TX LOL Assert and PLL Acquisition Time
DATA INPUT POWER
LOS ASSERT TIME
LOS DEASSERT TIME
LOS
ACQUISITION TIME
LOL
Figure 2. LOS Assert/Deassert Time
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10Gbps Clock and Data Recovery with Equalizer MAX3992
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
MAX3992 INPUT (15in FR-4)
MAX3992 toc01
RECOVERED REFERENCE SIGNAL PRBS 231-1 15in FR-4
MAX3992 toc02
JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE AMPLITUDE (BW < 100kHz)
PRBS 231-1 14 JITTER GENERATION (mUIRMS) 12 10 8 6 4 2
MAX3992 toc03
16
DIFFERENTIAL SIGNAL AMPLITUDE (mV)
50 -50
-500 0 0.35 0.65 1 NORMALIZED BIT TIME (UI) 0 1 NORMALIZED BIT TIME (UI)
DIFFERENTIAL SIGNAL AMPLITUDE (100mV/div)
500
0 0 10 20 30 40 50 NOISE AMPLITUDE (mVRMS)
POWER-SUPPLY INDUCED OUTPUT JITTER vs. RIPPLE FREQUENCY
MAX3992 toc04
SINUSOIDAL JITTER TOLERANCE 12in FR-4 231-1 PRBS DATA
TOLERANCE EXCEEDS MODULATION CAPABILITIES OF TEST EQUIPMENT
MAX3992 toc05
JITTER TRANSFER
0 JITTER TRANSFER (dB) -3 -6 -9 -12 -15 -18
MAX3992 toc06
0.07 JITTER GENERATION (psP-P/mVP-P) 0.06 0.05 0.04 0.03 0.02 0.01 0 1k 10k 100k FREQUENCY (Hz) 1M
100
3
JITTER TOLERANCE (U|P-P)
10
1 XFI TELECOM MASK 0.1
0.01 10M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
-21 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
MAX3992 SUPPLY CURRENT vs. TEMPERATURE
MAX3992 toc07
DIFFERENTIAL S11 SDD11
5 0 -5 SDD11 (dB) -10 -15 -20 -25 -30 -35 XFI MASK
MAX3992 toc08
140 130 SUPPLY CURRENT (mA) 120 110 100 90 80 -10 0
10
-40 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) 10M 100M 1G FREQUENCY (Hz) 10G 100G
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10Gbps Clock and Data Recovery with Equalizer
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
MAX3992
COMMON MODE S11 SCC11
XFI MASK
MAX3992 toc09
DIFFERENTIAL TO COMMON MODE S11 SCD11
XFI MASK
MAX3992 toc10
0 -5 -10 SCC11 (dB)
0 -10 -20 SCD11 (dB) -30 -40 -50 -60
-15 -20 -25 -30 -35 -40 10M 100M 1G FREQUENCY (Hz) 10G 100G
10M
100M
1G FREQUENCY (Hz)
10G
100G
Pin Description
PIN 1, 6, 11, 13, 18 2, 5, 14, 17 3 4 7 8 9 10 12 15 16 19 20 21 NAME VCC GND SDISDI+ SCLKO+ SCLKOFCTL2 POL CFIL SDO+ SDOLOL LOS REFCLK+ +3.3V Power Supply Supply Ground Negative Serial Input, CML Positive Serial Input, CML Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). Function Control Input 2, TTL. See Table 3 for more information. Data Polarity Control Input, TTL. Connect to VCC or leave open to maintain the same polarity as the input. Connect to GND to invert the polarity of the data. Loop-Filter Capacitor Connection. Connect a 0.047F capacitor between CFIL and VCC. Positive Serial Data Output, CML Negative Serial Data Output, CML Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock. Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal is removed. Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK have a 200 differential impedance. See the Detailed Description section for more information. See Table 2. FUNCTION
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10Gbps Clock and Data Recovery with Equalizer MAX3992
Pin Description (continued)
PIN 22 23 24 NAME REFCLKFCTL1 VTH Exposed Pad FUNCTION Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK have a 200 differential impedance. See the Detailed Description section for more information. See Table 2. Function Control Input 1, TTL. See Table 3 for more information. LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS power detector can be disabled if VTH is connected to VCC, which forces LOS low. Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical performance. The MAX3992 uses exposed-pad variation T2444-4 in the package outline drawing. See the exposed-pad package.
EP
Functional Diagram
VTH LOS
MAX3992
SDI+ SDICML EQUALIZER PLL PHASE/ FREQUENCY DETECTOR D
DFF Q CML SDO+ SDO-
VCO
CML
SCLKO+ SCLKO-
REFCLK+ REFCLK-
200
LOL DETECTOR
FUNCTIONAL CONTROL FCTL1 FCTL2 POL
LOL
CFIL
Figure 3. Functional Diagram
Detailed Description
The MAX3992 clock and data recovery with equalizer recovers data from the XFI interface. It consists of an equalizer with LOS power detector and a data retimer with LOL indicator. An optional recovered clock may also be enabled for performance testing.
most of the deterministic jitter caused by frequency dependent skin effect and dielectric losses, as well as connector loss.
PLL Retimer
The integrated PLL recovers a synchronous clock that is used to retime the input data. Connect a 0.047F capacitor between CFIL and VCC to provide PLL dampening. The external reference connected to REFCLK aids in frequency acquisition. Because the reference clock is only used for frequency acquisition, an extremely low jitter generation can be achieved from a low-quality reference clock. The reference clock should be within 100ppm of the bit rate divided by 16 or 64.
Equalizer
The SDI inputs of the MAX3992 accept serial NRZ data from XFI standard interfaces. When signals from 400mVP-P to 1000mVP-P are applied to a transmission line from 0 to 12 inches of FR-4, the equalizer restores them for recovery by the CDR. The equalizer removes
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10Gbps Clock and Data Recovery with Equalizer
Loss-of-Lock Monitor
The LOL output indicates that the frequency difference between the recovered clock and the reference clock is excessive. LOL may assert due to excessive jitter at the data input, incorrect frequency, or loss of input data. The LOL detector monitors the frequency difference between the recovered clock and the reference clock. The LOL output is asserted high when the frequency difference exceeds 650ppm.
Design Procedure
Modes of Operation
The MAX3992 has a standby mode and jitter test mode in addition to its normal operating mode. Standby is used to conserve power. In the standby mode, the power consumption of the MAX3992 falls below 40% of the normal-operation power consumption. The jitter test mode enables the SCLK outputs to clock a BERT when testing jitter generation, jitter transfer, and jitter tolerance. The FCTL1 and FCTL2 TTL inputs are used to select the mode of operation as shown in Table 3.
MAX3992
Loss-of-Signal Monitor
The LOS output indicates a loss of input data. Set VTH >500mV. When the input signal is removed (<50mV), LOS will be asserted high.
Serial Data Rate and Reference Clock Frequency
Input Configuration The SDI inputs of the MAX3992 are current-mode logic (CML) compatible. The inputs have internal 50 terminations for minimum external components. See Figure 5 for the input structure. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Reference Clock Input
The REFCLK inputs are internally terminated and selfbiased to allow AC-coupling. The input impedance is 100 single-ended (200 differential). The REFCLK inputs of the MAX3991 and MAX3992 should be connected close together in parallel. The impedance looking into the parallel combination is 100 differential. This allows both the MAX3991 and MAX3992 to easily interface with one reference clock without using additional components. See Figure 4.
Output Configuration
The MAX3992 uses CML for its high-speed digital outputs (SDO and SCLKO). The configuration of the output circuit includes internal 50 back terminations to VCC. See Figure 6 for the output structure. CML outputs may be terminated by 50 to VCC, or by 100 differential impedance. The relation of the output polarity to input can be reversed using the POL pin. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
50W REFERENCE CLOCK 50W
MAX3991
200 REFERENCE CLOCK
50W 200 50W
MAX3992
200
TRANSMITTER-ONLY TERMINATION
MAX3992
200
TRANSCEIVER TERMINATION
Figure 4. Reference Clock Termination _______________________________________________________________________________________ 9
10Gbps Clock and Data Recovery with Equalizer MAX3992
VCC
Applications Information
Exposed Pad (EP) Package
The exposed pad, 24-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3992 and must be soldered to the circuit board for proper thermal and electrical performance.
50 SDI+ SDI-
50
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3992 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals.
Figure 5. CML Input Model
VCC
(SDI+) - (SDI-)
50
50 SDO+
(SDO+) - (SDO-) POL = VCC
SDO(SDO+) - (SDO-) POL = GND
Figure 7. Polarity (POL) Function
GND
Table 3. Functional Control
FCTL1 0 1 0 1 FCTL2 0 0 1 1 DESCRIPTION Normal operation, serial clock output disabled. Standby power-down mode. Normal operation, serial clock output disabled. Serial clock output enabled for jitter testing.
Figure 6. CML Output Model
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10Gbps Clock and Data Recovery with Equalizer
Typical Application Circuit
VCC 0.047F TOSA
MAX3992
CFIL
SDO+
VCC
GND
SDI+
MAX3975
DRIVER SDO-
SDI-
MAX3992
FCTL VTH POL
2 N.C.
REFCLK+ REFCLK-
LOL LOS
30-PIN CONNECTOR
DS1862* CONTROLLER
2 N.C.
2-WIRE INTERFACE
LOL LOS
SDI+ ROSA SDI-
FCTL VTH POL
REFCLK+ REFCLK-
MAX3991
CFIL VCC GND
SDO+ SDO-
0.047F 50 TRANSMISSION LINE
XFI REFERENCE
VCC
*FUTURE PRODUCT.
Chip Information
TRANSISTOR COUNT: 10,300 PROCESS: SiGe bipolar SUBSTRATE: SOI
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maximic.com/packages.) (QFN 4mm x 4mm x 0.8mm, package code: T2444-4)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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