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Integrated Circuit Systems, Inc.
Preliminary Information
M928-02
VCSO BASED CLOCK GENERATOR
PIN ASSIGNMENT (9 x 9 mm SMT)
XTAL_1 / REF_IN GND nFOUT5 FOUT5 nFOUT4 FOUT4 nFOUT3 FOUT3 VCC XTAL_2 FOUT6 nFOUT6 FOUT7 nFOUT7 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M928-02 is a PLL (Phase Locked Loop) based clock generator that uses an internal VCSO (Voltage Controlled SAW Oscillator) to produce a very low jitter output clock. From the M928-02-622.0800, an output clock frequency of 622.08MHz is provided from eight LVPECL clock output pairs. (Other frequencies are available; consult factory.) The accuracy of the output frequency is assured by the internal PLL that phase-locks the internal VCSO to the reference input frequency (19.44MHz for the M928-02-622.0800). The input reference can either be an external crystal, utilizing the internal crystal oscillator, or a stable external clock source such as a packaged crystal oscillator.
28 29 30 31 32 33 34 35 36
M928-02
(Top View)
18 17 16 15 14 13 12 11 10
nFOUT2 FOUT2 nFOUT1 FOUT1 GND nFOUT0 FOUT0 VCC GND
FEATURES
Output clock frequency range 300MHz to 700MHz (Consult factory for frequency availability) Eight identical LVPECL output pairs Jitter 0.7ps rms (@622.08MHz, over 12kHz-20MHz), typ. Ideal for OC-48/STM-16 clock reference Output-to-output skew < 100ps External XTAL or LVCMOS reference input Integrated SAW (surface acoustic wave) delay line Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Output Frequency Configurations (M928-02-622.0800)
VCSO and Ref Clock PLL Output Frequency Multiplication Frequency (MHz) Ratio (MHz) 19.44 32 622.08 Application
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
OC-48/STM-16
Table 1: Example Output Frequency Configurations
SIMPLIFIED BLOCK DIAGRAM
M928-02-622.08 (Other Frequencies Available)
VSCO
External Crystal or Reference Clock Input (19.44MHz)
XTAL OSC
Frequency Multiplying PLL
LVPECL Output Clock Pairs (622.08MHz)
External Loop Filter
Figure 2: Simplified Block Diagram
M928-02 Datasheet Rev 0.4
M928-02 VCSO Based Clock Generator
Revised 30Jul2004
Integrated Circuit Systems, Inc.
Networking & Communications
w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M928-02
VCSO BASED CLOCK GENERATOR
Preliminary Information
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP RPOST
External Loop Filter Components
M928-02
Phase Detector
OP_IN
nOP_IN
OP_OUT
nOP_OUT
nVC
VC
XTAL_1 / REF_IN XTAL_2
RIN
SAW Delay Line
XTAL OSC
RIN Loop Filter Amplifier Phase Shifter
FOUT7 nFOUT7 FOUT6 nFOUT6
VCSO
M Divider M=8
FOUT5 nFOUT5 FOUT4 nFOUT4 FOUT3 nFOUT3 FOUT2 nFOUT2 FOUT1 nFOUT1 FOUT0 nFOUT0
Phase Locked Loop (PLL)
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12, 13 15, 16 17, 18 20, 21 22, 23 24, 25 29, 30 31, 32 27 28 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT0, nFOUT0 FOUT1, nFOUT1 FOUT2, nFOUT2 FOUT3, nFOUT3 FOUT4, nFOUT4 FOUT5, nFOUT5 FOUT6, nFOUT6 FOUT7, nFOUT7 XTAL_1 / REF_IN XTAL_2 DNC I/O Configuration Description
Ground Input Output Input Power
Power supply ground connections.
External loop filter connections. See Figure 5.
Power supply connection, connect to +3.3V.
Output
No internal terminator
Clock output pairs, differential LVPECL output (622.08 MHz for the M928-02-622.0800)
Input Input Do Not Connect.
External crystal connection. Also accepts LVCMOS/LVTTL compatible clock source. External crystal connection. Leave unconnected when driving pin 27 with external clock reference. Internal nodes. Connection to these pins can cause erratic device operation.
Table 2: Pin Descriptions
M928-02 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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Revised 30Jul2004 w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M928-02
VCSO BASED CLOCK GENERATOR
Preliminary Information
FUNCTIONAL DESCRIPTION
The M928-02 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. The M928-02 combines the flexibility of a VCSO (Voltage Controlled SAW Oscillator) with the stability of a crystal oscillator. Input Reference The 19.44MHz input reference can either be an external, discrete crystal device or a stable external clock source such as a packaged crystal oscillator:
APPLICATION INFORMATION
This section includes information on the optional external crystal and on the external loop filter. The subsections on the loop filter provide example component values and also briefly describe the SAW PLL simulator tool and additional application information available at www.icst.com. External Crystal Specifications If an external crystal is used with the on-chip crystal oscillator circuit (XTAL OSC), the external crystal should have the following general specifications: Crystal Specifications
Parameter Min Typ Max Unit AT-cut quartz Fundamental 16 40 50
* If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal should be a parallel-resonant, fundamental mode crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input pins. External crystal load capacitors are also required. * If an external LVCMOS/LVTTL clock source is used, apply it to the XTAL_1 / REF_IN input pin. In either case, the reference clock is supplied directly to the phase detector of the PLL. The PLL The PLL (Phase Locked Loop) includes the phase detector, the VCSO, and a feedback divider (labeled "M Divider"). The feedback divider is a digital circuit that divides the VCSO output frequency by a numerical value "M" in order to match the input reference frequency. By controlling the frequency and phase of the VCSO, the phase detector precisely locks the frequency and phase of the feedback divider output to that of the input reference. This creates an output frequency that is a multiple of the reference frequency (which is output from the VCSO). The relationship between the VCSO output frequency, the M Divider, and the input reference frequency is defined as follows: Fvcso = M x Fxtal For the M928-02-622.0800 (see "Ordering Information" on pg. 6): * VCSO output frequency = 622.08MHz * M = 32 * Input reference frequency = 19.44MHz Therefore, for the M928-02-622.0800:
622.08MHz = 32 x 19.44MHz
f0
ESR
Crystal Type Mode of Oscillation Frequency Range
MHz
Equivalent Series Resistance Spurious Response (non-harmonic) Load Capacitance, parallel load resonant Drive Level
16 0.1
-40 dBc pF mW
CL P0
32 1.0
Table 3: Crystal Specifications
The external crystal will be applied to the XTAL_1 / REF_IN and XTAL_2 input pins. External crystal load capacitors are also required.
Recommended External Crystal Configuration M928-02 M9xx-0x
XTAL_1 / REF_IN
C1
XTAL XTAL_2
C2
XTAL OSC
Figure 4: Recommended External Crystal Configuration
XTAL Load Capacitance Specification = 18 pF C1 = 27 pF C2 = 33 pF External load capacitors C1 and C2 present a load of 15 pf to the crystal (they are seen in series by the crystal through the common ground connection). With the additional of PCB trace capacitance and M928-02 input capacitance, the total load to the crystal is about 18 pf.
The VCSO center output frequency of 622.08MHz enables the product of M x input crystal frequency to fall within the lock range of the VCSO.
M928-02 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M928-02 requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 5).
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M928-02
VCSO BASED CLOCK GENERATOR
Preliminary Information See Table 4, Example External Loop Filter Component Values, below. Example External Loop Filter Component Values
PLL Bandwidth Damping R loop C loop R post C post (kHz) Factor (k) (F) (k) (pF) 0.395 1.2 10
1
2.0 2.9 2.4
1.5 4.7 39.0
4.70 1.00 0.01
20 20 20
3300 1000 240
Table 4: Example External Loop Filter Component Values
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
Note 1: Recommended for minimum output jitter when using a crystal or crystal oscillator reference.
nOP_IN
VC
Refer to the M928-02 product web page at www.icst.com/products/summary/M928-02.htm for additional product information.
Figure 5: External Loop Filter
The loop filter is implemented as a differential circuit to minimize system noise interference. Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here.
PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
Refer to the SAW PLL Simulator Software web page at www.icst.com/products/calculators/m2000filterSWdesc.htm for additional information.
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
oC
-45 to +100
Table 5: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 6: Recommended Conditions of Operation
M928-02 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
4 of 6 Networking & Communications
Revised 30Jul2004 w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M928-02
VCSO BASED CLOCK GENERATOR
Preliminary Information
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = 622.08MHz,1 LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 375
Max 3.465
Unit
Power Supply
VCC ICC
Positive Supply Voltage Power Supply Current Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance Output High Voltage Output Low Voltage Peak to Peak Output Voltage
FOUT, nFOUT (0-7) XTAL_1 / REF_IN XTAL_1 / REF_IN (XTAL_2 disconnected)
V mA
Reference Clock Input
VIH VIL IIH IIL
(Vcc / 2 ) +0.5
Vcc +0.3
V A A
-0.3 -5.0
(Vcc / 2 ) +0.5 V
150
Crystal or Reference Clock Input Differential Output
CIN VOH VOL VP-P
4 Vcc -1.4 Vcc -2.0 0.6 Vcc -1.0 Vcc -1.7 0.85
pF V V V
Note 1: For other VCSO center frequencies, contact ICS
Table 7: DC Characteristics
AC Characteristics
Unless implied otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = 622.08MHz,1 LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 300
Typ
Max 700
Unit
Test Conditions
FOUT FIN APR n
Output Frequency Range Nominal Input Frequency, XTAL_1 / REF_IN VCSO Pull-Range Single Side Band Phase Noise @622.08MHz Jitter (rms) Output Duty Cycle, High Time Output Rise Time Output Fall Time Output Skew
FOUT, nFOUT (0-7) FOUT, nFOUT (0-7) 1kHz Offset 10kHz Offset 100kHz Offset
MHz MHz ppm dBc/Hz dBc/Hz dBc/Hz ps % ps ps ps
Table 8: AC Characteristics
19.44
+100
+150
-100 -110 -134 0.7 1.0 55 350 350 100
J(t) tDC tR tF tS
12kHz to 20MHz
45 200 200
50 275 275
20% to 80% 20% to 80%
Between Any Pair
Note 1: For other VCSO center frequencies, contact ICS
M928-02 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
5 of 6 Networking & Communications
Revised 30Jul2004 w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
Preliminary Information
M928-02
VCSO BASED CLOCK GENERATOR
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at www.icst.com/products/appnotes/SawPllAppNotes.htm for application notes, including recommended PCB footprint, solder mask, and furnace profile.
Figure 6: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme Part Number:
Device Number Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) See Table 9 for example part numbers. Consult ICS for the availability of VCSO frequencies.
M928-02- xxx.xx
Figure 7: Part Numbering Scheme
Example Part Numbers
For Output Frequencies (MHz) Temperature 622.08 300 to 700
commercial industrial commercial industrial
Order Part Number M928-02 -622.0800 M928-02I622.0800 M928-02 -xxx.xxxx M928-02Ixxx.xxxx
Table 9: Example Part Numbers
Consult ICS for the availability of VCSO frequencies
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M928-02 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
6 of 6 Networking & Communications
Revised 30Jul2004 w w w. i c s t . c o m
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