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KS0063B
INTRODUCTION
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
The KSOO63B is a LCD driver LSl which is fabricated by low power CMOS technology. Basically this LSl consists of 40x2 bit bidrectional shift register, 40x2 bit data latch and 40x2 bit LCD driver (refer to Fig 1). This LSl can be used segment driver.
FUNCTION
* Dot matrix LCD driver with 80 channel output. * lnput/Output signal Output : 40x2channel waveform for LCD driving Input : - Serial display data and control pulse from the controller LSl. - Bias voltage (V1 - V4)
FEATURES
* Display driving bias ; static-1/5 * Power supply voltage ; 2.7V ~ 5.5V * Supply voltage for display : 0 ~ - 5V(VEE) * interface driver (cascade connection) controller KS0065B, KS0063, Other KS0063B KS0066/U * CMOS Process * l00QFP and bare chip available
BLOCK DIAGRAM
S1 V1 V2 V3 V4
S2
Part 1
S39 S40 V1 V2 V3 V4
S41 S42
Part 2
S79
S80
LCD DRIVER
LCD DRIVER
VDD Data Latch ( 40 bit ) Data Latch ( 40 bit ) VSS Bidirectional Shift Register (40 bit ) M CL1 CL2 SW CONTR LOGIC DL1 SHL1 DR1 DL2 DR2 Bidirectional Shift Register (40 bit ) VEE
SHL2
Fig. 1. KS0063 functional block diagram
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN CONFIGURATION
S70
S69
S68
S67
S66
S65
S64
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42 52
S63
80
79 78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
51
S41 50 NC 49 NC 48 M 47 DR2 46 DL2 45 DR1 44 DL1 43 CL2 42 VDD 41 NC 40 NC 39 SHL 38 SHL 37 CL1 36 GN 35 V4 34 V3 33 V2 32 V1 31 VEE 30 S1
S71 81 S72 82 S73 83 S74 84 S75 85 S76 86 S77 87 S78 88
S79 89 S80 90 S40 91 S39 92 S38 93 S37 94 S36 95 S35 96 S34 97 S33 98 S32 99 S31 100
KS0063B
1 S30
2 S29
3 S28
4 S27
5 S26
6 S25
7 S24
8 S23
9 S22
10 S21
11 12 S20 S19
13 S18
14 S17
15 S16
16 S15
17 S14
18 S13
19 S12
20 S11
21 S10
22 S9
23 S8
24 S7
25 S6
26 S5
27 S4
28 S3
29 S2
Fig. 2.100QFP Top View
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
PIN (NO.) VDD(42) Operating Voltage VSS(GND)(36) VEE(31) V1, V2 (32,33) V3, V4 (34,35) S1 - S40 SHL1(38) Input Output Input Part 1 LCD driver Data Interface Input Power Negative Supply Voltage LCD driver output voltage level Bias voltage level for LCD drive (Nonselect level) LCD driver output Selection of the shift direction of shift register LCD VDD or VSS Bias voltage level for LCD drive (Select level) Power 0V (GND) For LCD driver circuit (- 5V) Power Supply INPUT OUTPUT NAME DESCRIPTION For logical circuit (2.7V ~ 5.5V) INTERFACE
DL1, DR1 (44,45) S41 - S80 SHL2 (39)
Input Output Output Input
Data Input/output of shift register (part 1) LCD driver Data Interface LCD driver output Selection of the shift direction of shift register
Part 2
Controller or KS0063B LCD VDD or VSS
DL2, DR2 (46,47) M(48) CL1, CL2 (37,43) NC (40, 41, 49, 50)
Input Output Input Input
Data Input/output of shift register (part 2) Alternated signal for LCD driver output Data shift/latch clock The alternating signal to convert LCD drive waveform to AC CL1 : Data latch clock CL2 : Data shift clock No connection
Controller or KS0063 Controller
NC
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
MAXIMUM ABSOLUTE LIMIT (Ta=25C)
Characteristic Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V1~V4) Operating Temperature Storage Temperature Symbol VDD VLCD VlN1 VIN2 T OPR T STG Value -0.3~+7.0 VDD-13.5~VDD+0.3 -0.3~VDD+0.3 VDD+0.3~VEE-0.3 -30~+85 -55~+125 Unit V V V V
C C
* Voltage greater than above may damage to the circuit * VEE : connect a protection resistor (220<5%)
ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (VDD= 2.7V~5.5V,
Characteristic Operating Current Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending Symbol lDD lEE VIH VIL lLKG VOH VOL VD1 VD2 Leakage Current IV VIN = 0 ~ VDD IOH = -0.4mA IOL = +0.4mA ION = 0.1mA for one of S1 - S80 ION = 0.05mA for each S1 - S80 VIN = VDD ~ VEE (Output S1 ~ S80 ; floating) -10 VEE= 3~13V, VSS=0V, Ta=-30 ~ +85C) Test condition Min Max 0.7VDD 0 -5 VDD-0.4 1 10 VDD 0.3VDD 5 0.4 1.1 1.5 10 V
Unit mA
Applicable pin VDD, VEE
fCL2 = 400KHz fCL1 = 1KHz
A
V
CL1, CL2,DL1, DL2, DR1, DR2, SHL1, SHL2, M DL1, DL2, DR1, DR2 V(V1-V4)-S(S1-S80)
A
A
V1 - V4
AC CHARACTERISTICS (VDD= 2.7V~5.5V,
Characteristic Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Symbol fCL tWCKH tWCKL tSL tLS Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time tR/tF tSU tDH tD -
VEE= 3~13V, VSS=0V, Ta=-30 ~ +85C) Test condition Min Max Unit 800 800 500 500 300 300 400 200 500 ns KHz
Applicable pin CL2 CL1, CL2 CL2
from CL2 to CL1 from CL1 to CL2 CL = 15pF
CL1,CL2
DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
TIMING CHARACTERISTICS
VIH VIL
VIH
CL2
tWCKL
VIL
tR
tWCKH
tF tDH tSU
Data in ( DL1, DL2 ) ( DR1, DR2 )
VIH VIL
tD tSL
Data out ( DL1, DL2 ) ( DR1, DR2 )
VOH VOL VIH VIL
tLS
tLS
CL1
tWCKH tR tSU VIH VIL tF
FLM
Fig. 3. AV characteristics
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
LCD OUTPUT WAVEFORMS
APPLICATION CIRCUIT
COM1 ~ COM16 KS0066 ( controller ) CLK1 VDD R V1 V2 V3 V4 V5 R R R R VR CLK2 M S1 ~ S80 SHL1 SHL2 DL1 DR1 DL2 CL1 CL2 M Segment Signal S1 ~ S80 SHL1 SHL2 DL1 DR1 DL2 CL1 CL2 M D Common Signal LCD
VEE KS0063 V1 V2 (seg driver ) V3 V4
DR2
VEE KS0063 V1 V2 (seg driver ) V3 V4
DR2 OPEN
GND or Other Voltage
VDD
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM
78 79 80 81 81 82 83 84 85 86
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
65
60
59
58
57
56
55
54
53
52
55
50
49 48 4; 46 45 44
KS0063B
Y X
43 42 41 40 39 38
( 0,0 )
87 88 89 90 91 93 94 95 96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CHIP SIZE : 3160 x 4110 PAD SIZE : 100O 100 UNIT :
37 36 35 34 33 32 31
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KS0063B
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD LOCATION
I3/4A EOEAI
(R) (R) (R)(R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R)
I3/4A E3/4EA
(R) (R) (R)
AIIIAAEE3/4NA O O
(R)(R) (R) (R) (R) (R)(R) (R)(R) (R) (R) (R) (R) (R) (R) (R) (R) (R)(R) (R)(R) (R) (R) (R) (R)(R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R)
I3/4A EOEAI
(R) (R) (R)
I3/4A E3/4EA
(R) (R) (R) (R) (R) (R)
AIIIAAEE3/4NA O O
(R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R)(R) (R)(R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R)
I3/4A EOEAI
(R) (R) (R)
I3/4A E3/4EA
(R) (R) (R) (R) (R)(R) (R) (R) OAA O(R) O O O AEA AE(R) AE(R) AE OAA AE AE(R) AI(R) AE AI E (R)
AIIIAAEE3/4NA O O
(R) (R) (R) (R) (R)(R) (R)(R) (R) (R) (R) (R)(R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R)

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