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K4S561632D
CMOS SDRAM
256Mbit SDRAM
4M x 16bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.1 Aug. 2002
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
K4S561632D
Revision History Revision 0.0 (Jan., 2002)
-First generation
CMOS SDRAM
Revision 0.1(Aug.,2002)
- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.
Rev. 0.1 Aug. 2002
K4S561632D
4M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
* JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Four banks operation * MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation * DQM for masking * Auto & self refresh * 64ms refresh period (8K Cycle) Part No. K4S561632D-TC/L60 K4S561632D-TC/L7C K4S561632D-TC/L75 K4S561632D-TC/L1H K4S561632D-TC/L1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Max Freq. 166MHz(CL=3) 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 4M x 16 4M x 16 4M x 16 4M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
A ddress Register
CLK ADD
Column Decoder Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
K4S561632D
PIN CONFIGURATION (Top view)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 V SS
CMOS SDRAM
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System cock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA 0 ~ CA 8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A 12 BA 0 ~ BA1 RAS CAS WE L(U)DQM D Q0 ~
15
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
VDD /VSS VDDQ /VSSQ N.C/RFU
Rev. 0.1 Aug. 2002
K4S561632D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, V OUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD , VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 V DD+0.3 0.8 0.4 10 Unit V V V V V uA Note 4 1 2 IOH = -2mA IOL = 2mA 3
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S561632C-60 is 3.135V~3.6V.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note 1 2 2 3
RAS , CAS, WE, CS, CKE, DQM Address D Q0 ~ DQ 15
Notes : 1. -75/7C only specify a maximum value of 3.5pF 2. -75/7C only specify a maximum value of 3.8pF 3. -75/7C only specify a maximum value of 6.0pF
Rev. 0.1 Aug. 2002
K4S561632D
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE V IL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE V IH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE V IH(min), CLK VIL(max), tCC = Input signals are stable CKE V IL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE V IH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE V IH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S561632D-TC** 4. K4S561632D-TL** 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ /VSSQ ). Test Condition -60 Operating current (One bank active) Precharge standby current in power-down mode ICC1 150 -7C 110
CMOS SDRAM
Version -75 100 -1H 100 -1L 100
Unit
Note
mA
1
ICC2P ICC2PS ICC2N
2 2 20
mA
Precharge standby current in non power-down mode
mA 10 6 6 30 mA
ICC2NS ICC3P ICC3PS ICC3N
Active standby current in power-down mode
mA
Active standby current in non power-down mode (One bank active)
ICC3NS
25
mA
Operating current (Burst mode)
ICC4
180
140
140
130
130
mA
1
Refresh current Self refresh current
ICC5 ICC6
220
220
200 3 1.5
190
190
mA mA mA
2 3 4
Rev. 0.1 Aug. 2002
K4S561632D
AC OPERATING TEST CONDITIONS (V DD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
CMOS SDRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit Notes : 1. The DC/AC Test Output Load of K4S561632C-TC(L)60 is 30pF. 2. The VDD condition of K4S561632C-TC(L)60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -60 tRRD(min) tRCD(min) tR P(min) tRAS(min) tRAS(max tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) 60 60 12 18 18 42 -7C 15 15 15 45 Version -75 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 70 70 -1H 20 20 20 50 -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2, 5 5 2 2 3 4 1 1 1 1 Unit Note
CAS latency=3 CAS latency=2
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Aug. 2002
K4S561632D
AC CHARACTERISTICS
Parameter CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 2.5 2.5 2.5 1.5 1 1 5 tSAC (AC operating conditions unless otherwise noted) Symbol Min CLK cycle time CLK to valid output delay Output data hold time tCC 6 5 3 3 2.5 2.5 1.5 0.8 1 5.4 5.4 -60 Max 1000 -7C Min 7.5 7.5 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 5.4 6 Max 1000 Min 7.5 10 5.4 6 3 3 3 3 2 1 1 6 6 -75 Max 1000 -1H Min 10 10 6 6 Max 1000
CMOS SDRAM
-1L Min 10 12 6 7 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1,2 Max 1000 ns 1
Unit
Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Symbol trh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 Typ Max 4.37 Unit Volts/ns Notes 3
Output fall time
tfh
1.30
3.8
Volts/ns
3
Output rise time
trh
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
2.0
2.9
5.0
Volts/ns
1,2
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.
Rev. 0.1 Aug. 2002
K4S561632D
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 100MHz 133MHz Min I (mA) 100MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHz Min I (mA) -200 -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93.0 mA -300 -400 -500 -600 Voltage 0 0 -100 0.5 1 1.5 2
CMOS SDRAM
66MHz and 100MHz/133MHz Pull-up 2.5 3 3.5
0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0
IOH Min (100MHz) IOH Min (66MHz) IOH Max (66 and 100MHz)
66MHz and 100MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
Voltage (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz Min I (mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9
250
200
150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5
Voltage
IOL Min (100MHz) IOL Min (66MHz) IOL Max (100MHz)
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
Minimum VDD clamp current (Referenced to VDD ) 20
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31
15
mA
10
5
0 0 1 Voltage
I (mA)
2
3
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60
-3
-2
-1
0
Voltage
I (mA)
Rev. 0.1 Aug. 2002
K4S561632D
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A11,A12, A9 ~ A 0
A10/AP
Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8 ) Column address (A0 ~ A8 )
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA 1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA 1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Aug. 2002
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