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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS874005 is a high performance Differentialto-LVDS Jitter Attenuator designed for use in PCI HiPerClockSTM ExpressTM systems. In some PCI ExpressTM systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874005 has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz. The 200KHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. 400KHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. 800KHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5 Gb serdes have x20 multipliers while others have than x25 multipliers, the 874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins.
FEATURES
* (5) Differential LVDS output pairs * (1) Differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 160MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 15ps (typical) * 3.3V operating supply * 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * 0C to 70C ambient operating temperature
ICS
PLL BANDWIDTH
BW_SEL 0 = PLL Bandwidth: ~200KHz Float = PLL Bandwidth: ~400KHz (Default) 1 = PLL Bandwidth: ~800KHz
The ICS874005 uses ICS 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI ExpressTM add-in cards.
BLOCK DIAGRAM
OEA PU F_SELA PD QA0 nQA0 QA1 nQA1 QB0
PIN ASSIGNMENT
F_SELA 0 /5
(default)
BW_SEL Float 0 = ~200KHz Float = ~400KHz 1 = ~800KHz CLK PD nCLK PU
1 /4
Phase Detector
VCO
490-640MHz F_SELB 0 /5
(default)
M = /5
(fixed)
nQB0 QB1 nQB1 QB2 nQB2
nQB2 nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL VDDA F_SELA VDD OEA
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK
1 /4
ICS874005
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm package body
F_SELB
PD
MR PD OEB PU
G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 874005AG www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number 1, 24 2, 3 4, 23 5, 6 6 7 Name nQB2, QB2 nQA1, QA1 VDDO QA0, nQA0 nFB_OUT MR Type Output Output Power Output Output Input Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Inver ting differential feedback output. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ Selects PLL Band Width input. LVCMOS/LVTTL interface levels. Pulldown Analog supply pin. Frequency select pin for QAx/nQAx outputs. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx/nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
8 9 10 11 12 13 14 15, 16 17 18 19, 20 21, 22
BW_SEL VDDA F_SELA VDD OEA CLK nCLK GND OEB F_SELB nQB0, QB0 nQB1, QB1
Input Power Input Power Input Input Input Power Input Input Output Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs OEA/OEB 0 1 HiZ Enabled Outputs QAx/nQAx QBx/nQBx HiZ Enabled
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs PLL_BW 0 1 Float PLL Bandwidth ~200KHz ~800KHz ~400KHz
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874005AG
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 TBD TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH Input High Voltage MR, OEA, OEB, F_SELA, F_SELB BW_SEL VIL Input Low Voltage MR, OEA, OEB, F_SELA, F_SELB BW_SEL IIH Input High Current OEA, OEB BW_SEL, MR, F_SELA, F_SELB BW_SEL, OEA, OEB F_SELA, F_SELB, MR VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum Typical 2 VDD - 0.3 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 +0.3 5 150 Units V V V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V -150 0.15 1.3 VDD - 0.85 V V 5 15 0 A Minimum Typical Maximum 15 0 Units A
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 180 50 1.25 50 Maximum Units mV mV V mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Cycle-to-Cycle Jitter, NOTE 1 Output Rise/Fall Time 20% to 80% Test Conditions Minimum 98 15 340 50 Typical Maximum 160 Units MHz ps ps %
tjit(cc)
tR / tF
odc Output Duty Cycle NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
3.3V VDD
SCOPE
Qx
nCLK
+
POWER SUPPLY Float GND
-
LVDS
nQx
V
PP
Cross Points
V
CMR
CLK
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
nQAx, nQBx QAx, QBx
DIFFERENTIAL INPUT LEVEL
nQAx, nQBx QAx, QBx
Pulse Width t
PERIOD
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
80% Clock Outputs
20%
20% tR tF
out
VOS/ VOS
OUTPUT RISE/FALL TIME
VDD
OFFSET VOLTAGE SETUP
out
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. A JANUARY 10, 2005
tcycle n+1
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
80% VSW I N G
DC Input
out
LVDS
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874005 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V
3.3V
BY
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near
the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874005 application schematic. In this example, the device is operated at VCC=3.3V. The
decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver.
VDD = 3.3V
VDDO = 3.3V
Zo = 50 Ohm
+ U1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Zo = 50 Ohm R2 100 nQB2 nQA1 QA1 VDDO QA0 nQAO MR BW_SEL VDDA F_SELA VDD OEA QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK
R1 10
C3 10uF
C4 0.01u
MR BW_SEL F_SELA OEA
F_SELB OEB
Zo = 50 Ohm
+ 874005_tssop24 Zo = 50 Ohm nCLK Zo = 50 Ohm R3 100 -
Zo = 50 Ohm CLK
LVPECL Driv er
R4 50 (U1:23) R6 50
R5 50
(U1:11)
(U1:4)
C5 10uf
C6 .1uf
C7 .1uf
C8 .1uf
FIGURE 5. ICS874005 SCHEMATIC EXAMPLE
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
63C/W
500
60C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
TRANSISTOR COUNT
The transistor count for ICS874005 is: 1206
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
874005AG
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REV. A JANUARY 10, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS874005
PCI EXPRESSTM JITTER ATTENUATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS874005AG ICS874005AGT Marking ICS874005AG ICS874005AG Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube tape & reel Temperature 0C to 70C 0C to 70C
The aforementioned trademarks, HiPerClockSTM and PCI ExpresSTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 874005AG
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REV. A JANUARY 10, 2005

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