View ICS87016I_986899.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 16 LVCMOS/LVTTL outputs (4 banks of 4 outputs) * Selectable differential CLK1, nCLK1 or LVCMOS clock input * CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK0 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Independent bank control for /1 or /2 operation * Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation * Asynchronous clock enable/disable * Output skew: 170ps (maximum) * Bank skew: 50ps (maximum) * Part-to-part skew: 800ps (maximum) * 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator and is a member of the HiPerClockSTM HiPerClockS family of High Performance Clock Solutions. The device has 4 banks of 4 outputs and each bank can be independently selected for /1 or /2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines.
,&6
The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for /1 or /2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the /1//2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The ICS87016I is characterized to operate with the core at 3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87016I ideal for those clock applications demanding well-defined performance and repeatability.
BLOCK DIAGRAM
nMR/OE D 0 1 /1 /2 1 0 D 1 0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD 1 CLK_ENA CLK_ENB CLK_ENC CLK_END 0 1 0 D
LE LE LE
PIN ASSIGNMENT
4 QA0:QA3 VDD CLK0 DIV_SELA QB0:QB3 DIV_SELB DIV_SELC DIV_SELD CLK_ENA QC0:QC3 CLK_ENB CLK_ENC CLK_END nMR/OE QD0:QD3 GND
QA3 VDDOA QA2 GND QA1 VDDOA QA0 GND CLK_SEL nCLK1 CLK1 VDD
CLK0 CLK1 nCLK1 CLK_SEL
4
D
LE
4
4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS87016I
GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1
48-Pin LQFP 7mm x 7mm x 1.4mm body package Y Package Top View
www.icst.com/products/hiperclocks.html REV. A AUGUST 13, 2003
GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3
87016AYI
1
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Type Power Input Input Input Input Input Input Input Input Input Input Power Output Power Output Power Output Power Output Power Input Input Input Description Core supply pins. Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank A outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs Pullup LVCMOS / LVTTL interface levels.. Controls frequency division for Bank C outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pullup LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank C outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank D outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Master reset. When LOW, resets the /1//2 flip flops and sets the Pullup outputs to high impedance. LVCMOS / LVTTL interface levels. Supply ground. Bank D outputs. LVCMOS / LVTTL interface levels. Output Bank D supply pins. Bank C outputs. LVCMOS / LVTTL interface levels. Output Bank C supply pins. Bank B outputs. LVCMOS / LVTTL interface levels. Output Bank B supply pins. Bank A outputs. LVCMOS / LVTTL interface levels. Output Bank A supply pins. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 48 2 3 4 5 6 7 8 9 10 11 12, 16, 20, 24, 28, 32, 36, 40, 44 13, 15, 17, 19 14, 18 21, 23, 25, 27 22, 26 29, 31, 33, 35 30, 34 37, 39, 41, 43 38, 42 45 46 47 Name VDD CLK0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END nMR/OE GND QD3, QD2, QD1, QD0 VDDOD QC3, QC2, QC1, QC0 VDDOC QB3, QB2, QB1, QB0 VDDOB QA3, QA2, QA1, QA0 VDDOA CLK_SEL nCLK1 CLK1
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87016AYI
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 VDD, VDDOx = 3.465V; NOTE 1 VDD = 3.465, VDDOx = 2.625V; NOTE 1 VDD = 3.465, VDDOx = 1.89V; NOTE 1 5 7 18 20 30 12 Maximum Units pF K pF pF pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD.
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1 Inputs CLK_ENx X 1 1 0 DIV_SELx X 0 1 X Bank X Hi Z Active Active Low Outputs Qx Frequency N/A fIN/2 fIN N/A
87016AYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 13, 2003
3
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Core Supply Voltage VDD VDDOx IDD IDDOx Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current; NOTE 2 Test Conditions Minimum 3.135 3.135 2.375 1.71 Typical 3.3 3.3 2.5 1.8 Maximum 3.465 3.465 2.625 1.89 100 15 Units V V V V mA mA
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, and IDDOD.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH Input High Voltage DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDOx = 3.3V 5%; NOTE 2 VOH Output High Voltage; NOTE 1 VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2 IOH = -2mA VDDOx = 3.3V 5%; NOTE 2 VOL Output Low Voltage; NOTE 1 VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2 IOL = 2mA Output Tristate Current Low -5 -150 -5 2.6 1.8 VDD - 0.45 0.5 0.5 0.45 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V V V V V A A
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
IOZL
IOZH Output Tristate Current High 5 NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit. NOTE 2: VDDOx denotes VDDOA, VDDOB, VDDOC and VDDOD.
87016AYI
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions nCLK1 CLK1 nCLK1 CLK1 VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% f < 175MHz f 175MHz 200 45 40 2.8 2.75 Measured on the Rising Edge Measured on the Rising Edge 3.4 3.4 Test Conditions Minimum Typical Maximum 250 3.9 4.1 50 170 800 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
tDIS Output Disable Time; NOTE 5 10 All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87016AYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 13, 2003
5
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% f < 175MHz f 175MHz 200 45 40 2.9 3.0 Measured on the Rising Edge Measured on the Rising Edge 3.5 3.5 Test Conditions Minimum Typical Maximum 250 4.0 4.0 50 170 800 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 1.8V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% f < 175MHz f 175MHz 200 45 40 3.0 3.0 Measured on the Rising Edge Measured on the Rising Edge 3.9 3.9 Test Conditions Minimum Typical Maximum 250 4.7 4.7 50 170 800 700 55 60 10 Units MHz ns ns ps ps ps ps % % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
tDIS Output Disable Time; NOTE 5 10 All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87016AYI
www.icst.com/products/hiperclocks.html
6
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD , VDDOx
SCOPE
Qx
VDD VDDOx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V +0.9V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V DD VDDOx
SCOPE
Qx
VDD
LVCMOS
nCLK1
V
CLK1
PP
Cross Points
V
CMR
GND = -0.9V5%
GND
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
V
DDOX
V
DDOX
2
Qx
2
PART 2 Qy
V
DDOX
V
DDOX
2 tsk(pp)
Qy
2 tsk(o)
PART-TO-PART SKEW
87016AYI
OUTPUT SKEW
www.icst.com/products/hiperclocks.html REV. A AUGUST 13, 2003
7
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
QX0:QX0
VDDOX 2
80% 20% tR
80% 20% tF
QX0:QX0
tsk(b)
VDDOX 2
Clock Outputs
BANK SKEW (where X denotes outputs in the same bank)
OUTPUT RISE/FALL TIME
V
DDOX
QAx, QBx, QCx, QDx
2
CLK0
VDD 2
Pulse Width t
PERIOD
nCLK1 CLK1
odc =
t PW t PERIOD
QAx,QBx, QCx, QDx
VDDOX 2
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
87016AYI
www.icst.com/products/hiperclocks.html
8
tPD
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING
THE
DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
VCC
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
Single Ended Clock Input CLK_IN V_REF
R1 1K
R1 1K CLK
+
V_REF -
nCLK
C1 C1 0.1u
0.1uF R2 1K
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87016AYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 13, 2003
9
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
87016AYI
BY
www.icst.com/products/hiperclocks.html
10
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87016I is: 2034
87016AYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 13, 2003
11
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
FOR
PACKAGE OUTLINE - Y SUFFIX
48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87016AYI
www.icst.com/products/hiperclocks.html
12
REV. A AUGUST 13, 2003
Integrated Circuit Systems, Inc.
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87016AYI ICS87016AYIT Marking ICS87016AYI ICS87016AYI Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87016AYI www.icst.com/products/hiperclocks.html REV. A AUGUST 13, 2003
13

▲Up To Search▲

Price & Availability of ICS87016I

	To Download ICS87016I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .