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Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FEATURES
* 1 differential 2.5V/3.3V LVPECL output * LVCMOS/LVTTL CLK input * CLK accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency: 267MHz * Part-to-part skew: 275ps (maximum) * Additive phase jitter, RMS: 0.05ps (typical) * 3.3V operating supply voltage (operating range 3.135V to 3.465V) * 2.5V operating supply voltage (operating range 2.375V to 2.625V) * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85320I is a LVCMOS / LVTTL-to-Differential 2.5V / 3.3V LVPECL translator and a memHiPerClockSTM ber of the HiPerClocksTMfamily of High Performance Clocks Solutions from ICS. The ICS85320I has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
ICS
BLOCK DIAGRAM
CLK Q nQ
PIN ASSIGNMENT
nc Q nQ nc 1 2 3 4 8 7 6 5 VCC CLK nc VEE
ICS85320I
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Type Unused Output Power Input Power Pullup Description No connect. Differential output pair. LVPECL interface levels. Negative supply pin. LVCMOS / LVTTL clock input. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 4, 6 2,3 5 7 8 Name nc Q, nQ VEE CLK VCC
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF K
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 25 Units V V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK CLK CLK CLK VCC = VIN = 3.465V VCC = VIN = 3.465V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 1.3 5 Units V V A A
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK CLK CLK CLK VCC = VIN = 2.625V VCC = VIN = 2.625V -150 Test Conditions Minimum 1.6 -0.3 Typical Maximum VCC + 0.3 0.9 5 Units V V A A
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Test Conditions 267MHz Integration Range: 12KHz - 20MHz 20% to 80% Minimum 0.8 0.05 275 200 700 Typical Maximum 267 1.4 Units MHz ns ps ps ps
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time
t jit t sk(pp)
tR, tF
odc Output Duty Cycle 45 55 % NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time 267MHz Integration Range: 12KHz - 20MHz 20% to 80% 0.8 0.05 375 200 700 Test Conditions Minimum Typical Maximum 215 1.7 Units MHz ns ps ps ps
t jit t sk(pp)
tR, tF
odc Output Duty Cycle 45 55 % NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
@ 156.25MHz (12KHz to 20MHz) = 0.05ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
2V 2V
V CC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Part 1 nQx 80% Qx Part 2 nQy Qy Clock Outputs 20% tR tF 80% VSW I N G 20%
tsk(o)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
nCLK CLK nQ Q
tPD
nQ Q
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
85320AMI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ground level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCC=2.5V
2.5V
VCC=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
nations examples are shown in this schematic. For more termination approaches, please refer to the LVPECL Termination Application Note.
APPLICATION SCHEMATIC EXAMPLE
Figure 3 shows an example of ICS85320I application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. For LVPECL output termination, only two termi-
Zo = 50 Ohm
Zo = 50 Ohm
VCC = 3.3V U1 1 2 3 4 nc Q nQ nc Vcc Clk nc Vee 85320 8 7 6 5
R2 50
R1 50
Clk_in
R3 50
VCC
(U1-8)
VCC = 3.3V C2 0.1uF R4 133 Zo = 50 Ohm + R6 133
C1 10uf
Zo = 50 Ohm
-
R5 82.5
R7 82.5
Optional Termination
FIGURE 3. ICS85320I APPLICATION SCHEMATIC EXAMPLE
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85320I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85320I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 30.2mW = 116.6mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.117W * 103.3C/W = 97.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85320I is: 269
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. A AUGUST 25, 2004
Integrated Circuit Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Marking 5320AMI 5320AMI Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85320AMI ICS85320AMIT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85320AMI
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REV. A AUGUST 25, 2004

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