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ICS650-12
MPEG Clock Synthesizer
Description
The ICS650-12 is a low cost, low-jitter, high-performance clock synthesizer designed to produce fixed clock outputs of 13.5 MHz and 27.0 MHz, and four selectable clock outputs: two Processor Clocks (PCLK1) and PCLK2), an Audio Clock, and a Communications Clock (CCLK). Using analog Phase-Locked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal to produce clocks ideal for Digital Video/MPEG-based applications.
Features
* * * * * * *
Packaged in 20-pin tiny SSOP (QSOP) Input frequency of 27.0 MHz Zero ppm synthesis error in output clocks Provides fixed 13.5 MHz and 27.0 MHz. Also provides two selectable processor clocks, one audio clock, and one communications clock. Ideal for digital video MPEG-based applications 3.3 V or 5.0 V operating voltage Entire chip powers down (when CS1=CS0=0)
Block Diagram
PS2:0 AS2:0 CS1:0 Clock Synthesis and Control Circuitry
PCLK1 PCLK2 ACLK CCLK 13.5 MHz
27.0 MHz crystal or clock
Input Buffer/ Crystal Oscillator
/2
27.0 MHz
MDS 650-12 B Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com
ICS650-12 MPEG Clock Synthesizer
Pin Assignment
PS2 X2 X1 VDD CS1 GND ACLK PCLK1 CS0 AS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PS1 PS0 CCLK PCLK2 VDD AS1 GND 13.5M 27M AS0
ACLK Select Table (in MHz)
AS2
0 0 0 0 1 1 1 1
AS1
0 0 1 1 0 0 1 1
AS0
0 1 0 1 0 1 0 1
ACLK
12.288 11.2896 8.192 24.576 8.192 16.9344 18.432 11.2896
20-pin SSOP (QSOP)
CCLK Select Table (in MHz)
CS1
PCLK1 and PCLK2 Select Table (in MHz) 0 0 1 1
CS0
0 1 0 1
CCLK
All off* 20.00 66.6666 24.576
PS2
0 0 0 0 1 1 1 1
PS1
0 0 1 1 0 0 1 1
PS0
0 1 0 1 0 1 0 1
PCLK1
108.00 55.00 66.67 80.00 54.00 81.00 50.00 60.00
PCLK2
54.00 27.5 33.33 40.00 27.00 40.5 25.00 30.00
*Note: Entire chip powers-down (outputs stop low) when CS1=CS0=0.
MDS 650-12 B Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com
ICS650-12 MPEG Clock Synthesizer
Pin Descriptions
Pin Pin Pin Number Name Type
1 2 3 4, 16 5 6, 14 7 8 9 10 11 12 13 15 17 18 19 20 PS2 X2 X1 VDD CS1 GND ACLK PCLK1 CS0 AS2 AS0 27M 13.5M AS1 PCLK2 CCLK PS0 PS1 Input XO XI Power Input Power Output Output Input Input Input Output Output Input Output Output Input Input
Pin Description
Processor Clock Select pin 2. See table on page 2. Crystal connection. Connect to a 27.0 MHz crystal or leave unconnected for a clock input. Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input. Connect to +3.3 V or +5 V. Communications Clock Select Pin 1. See table on page 2. Connect to ground. Audio Clock Output. See table on page 2. Processor Clock Output 1. See table on page 2. Communications Clock Select 0. See table on page 2. Audio Clock Select Pin 2. See table on page 2. Audio Clock Select Pin 0. See table on page 2. 27 MHz buffered clock output. 13.5 MHz clock output. Audio Clock Select Pin 1. See table on page 2. Processor Clock Output 2. See table on page 2. Communications Clock Output. See table on page 2. Processor Clock Select Pin 0. See table on page 2. Processor Clock Select Pin 1. See table on page 2.
Key: Input = input with internal pull-up; XI and XO = crystal connections; Power = power supply connection; Output = output
MDS 650-12 B Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com
ICS650-12 MPEG Clock Synthesizer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-12. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature
Conditions
Referenced to GND Referenced to GND 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C
Max. of 10 seconds
260C
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature 0 to +70C Parameter Operating Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage Operating Supply Current Operating Supply Current Short Circuit Current Input Capacitance Symbol VDD VIH VIL VOH VOL VOH,VDD = 3.3 or 5 V IDD@5 V IDD@5 V VDD = 3.3 V, IOH = -8 mA VDD = 3.3 V, IOL = 8 mA IOH = -8 mA No Load No Load Except X1 VDD-0.4 39 22 50 7 2.4 0.8 Conditions Min. 3.0 2 VDD/2 VDD/2 0.8 Typ. Max. 5.5 Units V V V V V V mA mA mA pF
IOS, VDD = 3.3 V Each output
MDS 650-12 B Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com
ICS650-12 MPEG Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature 0 to +70C
Parameter
Input Crystal or Clock Frequency Output Clocks Accuracy (synthesis error) Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle One Sigma Jitter, ACLK Absolute Clock Period Jitter
Symbol
Conditions
All clocks
Min.
Typ.
27 0
Max. Units
MHz 1 1.5 1.5 ppm ns ns % ps ps ps ps
tOR tOF
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V, except CCLK = 20 MHz VDD = 5.0 V, except CCLK = 20 MHz 40 50 100 40 300 200
60
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD and GND on pins 4 and 6, 16 and 14, and a 33 terminating resistor may be used on each clock output if the trace is longer than 1 inch.
MDS 650-12 B Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com
ICS650-12 MPEG Clock Synthesizer
Package Outline and Package Dimensions (20-pin SSOP)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol Min Max
Inches Min Max
E1 INDEX AREA
E
12 D
A A1 b c D E E1 e L
1.35 1.75 0.10 0.25 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8
0.053 0.069 0.004 0.010 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 0.025 Basic 0.016 0.050 0 8
A A1 c
- Ce
b SEATING PLANE
.10 (.004)
C
L
Ordering Information
Part / Order Number
ICS650R-12 ICS650R-12T
Marking
ICS650R-12 ICS650R-12
Shipping packaging
Tubes Tape and Reel
Package
20-pin SSOP 20-pin SSOP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-12 B Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 103103 tel (408) 297-1201
www.icst.com

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