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ICS650-07C
Networking Clock Source
Description
The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-07C outputs all have 0 ppm synthesis error. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Features
* Packaged in 20-pin tiny SSOP (QSOP) * Available in Pb (lead) free package * 12.5 MHz or 25.00 MHz fundamental crystal or clock
input
* * * * * *
Six output clocks with selectable frequencies SDRAM frequencies of 67, 83, 100, and 133 MHz Buffered crystal reference output Zero ppm synthesis error in all clocks Ideal for PMC-Sierra's ATM switch chips Full CMOS output swing with 25 mA output drive capability at TTL levels
* Advanced, low power, sub-micron CMOS process * 3.0 V to 5.5 V operating voltage
Block Diagram
VDD 2 CLKA1 /2 ACS1, 0 BCS1, 0 CCS 12.5 MHz or 25.00 MHz Crystal or Clock X1/ICLK X2 Clock Buffer/ Crystal Oscillator 2 Optional crystal capacitors are shown and may be required for tuning of initial accuracy GND OE (all outputs) 2 2 Clock Synthesis and Control Circuitry CLKA2 CLKB1 /2 CLKB2 CLKC1 CLKC2 REFOUT
MDS 650-07C B
1
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
Pin Assignment
ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 BCS1 BCS0 REFOUT CLKA1 VDD OE GND CLKA2 DC CCS
20 pin (150 mil) SSOP
Pin Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name
ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 CCS DC CLKA2 GND OE VDD CLKA1 REFOUT BCS0 BCS1
Pin Type
XO XI Power Input Power Output Output Output Output -- Output Power Input Power Output Output Input
Description
Crystal connection. Connect to a crystal or leave unconnected for clock input. Crystal connection. Connect to fundamental crystal or clock input. Connect to 3.3 V or 5 V. Must be same value as other VDD. A clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-up resistor. See table below. Connect to ground. Clock C output 1. Depends on setting of CCS per table below. Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1. Clock B output 2. Depends on setting of BCS1, 0 per table below. Clock B output 1. Depends on setting of BCS1, 0 per table below. Don't Connect. Do not connect anything to this pin. Clock A output 2. Depends on setting of ACS1, 0 per table below. Connect to ground. Output enable. Tri-states all outputs when low. Internal pull-up resistor. Connect to VDD. Must be same value as other VDD. Clock A output 1. Depends on setting of ACS1, 0 per table below. Buffered reference clock output. Same frequency as crystal or clock input. B clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.
Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.
Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.
Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.
MDS 650-07C B
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Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
For a 25 MHz Fundamental Crystal or Clock Input, use the following tables: A Clocks Select Table (MHz)
ACS1 0 0 0 1 1 1 ACS0 0 M 1 0 M 1 CLKA1 100 TEST 75 33.3333 TEST 66.6667 CLKA2 OFF (low) TEST OFF (low) 16.6667 TEST 33.3333
B Clocks Select Table (MHz)
BCS1 0 0 0 1 1 1 BCS0 0 M 1 0 M 1 CLKB1 TEST 66.6667 100 83.3333 TEST 133.3333 CLKB2 TEST 33.3333 50 41.6667 TEST 66.6667
C Clocks Select Table (MHz)
CCS 0 M 1 CLKC1 125 TEST 75 CLKC2 125 TEST 75
REFOUT = 25 MHz
0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (automatically self biases to VDD/2)
MDS 650-07C B
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Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
For a 12.5 MHz Crystal or Clock Input, use the following tables: A Clocks Select Table (MHz)
ACS1 0 0 0 1 1 1 ACS0 0 M 1 0 M 1 CLKA1 50 TEST 37.5 16.6667 TEST 33.3333 CLKA2 OFF (low) TEST OFF (low) 8.3333 TEST 16.6667
B Clocks Select Table (MHz)
BCS1 0 0 0 1 1 1 BCS0 0 M 1 0 M 1 CLKB1 TEST 33.3333 50 41.66667 TEST 66.6667 CLKB2 TEST 16.6667 25 20.8333 TEST 33.3333
C Clocks Select Table (MHz)
CCS 0 M 1 CLKC1 62.5 TEST 37.5 CLKC2 62.5 TEST 37.5
REFOUT = 12.5 MHz
0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (automatically self biases to VDD/2)
MDS 650-07C B
4
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
External Components
The ICS650-07C requires a minimum number of external components for proper operation.
with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Information Decoupling Capacitor
Decoupling capacitors of 0.01F must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF capacitors should be used. If a clock input is used, drive it into X1 and leave X2 unconnected.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-07C. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature (20 seconds max) 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured with respect to GND)
Min.
0 -40 +3.0
Typ.
Max.
+70 +85
Units
C C V
+3.3
+5.5
MDS 650-07C B
5
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Internal Pull-up Resistor
Symbol
VDD IDD VIH VIL VIH VIL VIH VIL VOH VOH VOL IOS
Conditions
No load X1 pin only, Clock input X1 pin only, Clock input All tri-level inputs All tri-level inputs Other inputs, except tri-level Other inputs, except tri-level IOH = -25 mA IOH = -8 mA IOL = 25 mA Each output ACS1, BCS1, OE
Min.
3.0
Typ.
60
Max.
5.5
Units
V mA V
VDD/2+1 VDD-0.5
VDD/2 VDD/2 VDD/2-1 0.5
V V V V
2 0.8 2.4 VDD-0.4 0.4 100 200
V V V V mA k
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Input Frequency Frequency Error Output Rise Time Output Fall Time Output Clock Duty Cycle Absolute Jitter, short term
Symbol
Conditions
All clocks
Min.
10
Typ.
12.5 or 25
Max. Units
27 0 1.5 1.5 MHz ppm ns ns % ps
tOR tOF
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 Variation from mean 40 50 150
60
MDS 650-07C B
6
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
135 93 78 60
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram--ICS650R-07
20 11
Marking Diagram--ICS650R-07I
20 11
ICS650R-07 $$###### YYWW
1 10
ICS650R-07I $$###### YYWW
1 10
Marking Diagram--ICS650R-07LF
20 11
650R-07LF ###### YYWW
1
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" denotes Pb (lead) free package. 4. "I" denotes industrial grade device. 5. Bottom marking: (origin) = country of origin if not USA.
10
MDS 650-07C B
7
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS650-07C Networking Clock Source
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol
E1 INDEX AREA E
Inches* Min Max
Min
Max
12 D
A A1 A2 b c D E E1 e L
1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0 8
0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8
A 2 A 1
A
*For reference only. Controlling dimensions in mm.
c
-Ce
b SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS650R-07 ICS650R-07T ICS650R-07LF ICS650R-07LFT ICS650R-07I ICS650R-07IT
Marking
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to 85 C -40 to 85 C
see page 7
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-07C B
8
Revision 061405
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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