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MATRA MHS
HM 65764
8K x 8 High Speed CMOS SRAM
Description
The HM 65764 is a high speed CMOS static RAM organized as 8192x8 bits. It is manufactured using MHS high performance CMOS technology. Access times as fast as 15 ns are available with maximum power consumption of only 743 mW. The HM 65764 features fully static operation requiring no external clocks or timing strobes. The automatic power-down feature reduces the power consumption by 73 % when the circuit is deselected. Easy memory expansion is provided by active low chip select (CS1), an active high chip select (CS2), an active low output enable (OE) and three state drivers. All inputs and outputs of the HM 65764 are TTL compatible and operate from single 5 V supply thus simplifying system design. The HM 65764 is 100 % processed following the test methods of MIL STD 883C and/or ESA/SCC 9000 making it ideally suitable for military/space applications that demand superior levels of performance and reliability.
Features
D Fast Access Time Commercial : 15/20/25/35/45/55 ns (max) Industrial/Automotive/Military : 20/25/35/45/55 ns (max) D Low Power Consumption Active : 380 mW (typ) Standby : 110 mW (typ) D Wide Temperature Range : -55C to 125C D D D D 300 and 600 Mils Width Package TTL Compatible Inputs and Outputs Asynchronous Capable Of Withstanding Greater Than 2000 V Electrostatic Discharge D Single 5 Volt Supply
3.3 Volt version available (see L 65764 specification)
Interface
Block Diagram
Rev. B (21/06/94)
1
HM 65764
Pin Configuration
SOIC & SOJ 300 mils, 28 pins, DIL. SOIC 330 mils, 28 pins Plastic 300 & 600 mils, 28 pins, DIL.
MATRA MHS
Ceramic 300 mils, 600 mils, 28 pins, DIL LCC 32 pins
Pinout DIL/SOIC/SOJ 28 pins (top view)
Pinout LCC 32 pins (top view)
Logic Symbol
Pin Names
A0-A13: Address inputs I/O0-I/O7 VCC GND : Inputs/Outputs : Power : Ground CS1 CS2 OE W : Chip-select 1 : Chip Select 2 : Output enable : Write enable
Truth Table
CS1 CS2 OE
H L L L X H H H X L X H
W
X H L H
DATA- IN
Z Z Valid Z
DATA- OUT
Z Valid Z Z
MODE
Deselect Read Write Output disable
L = low - H = high - X = H or L - Z = High impedance.
2
Rev. B (21/06/94)
MATRA MHS
HM 65764
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA Electro static discharge voltage : . . . . . . . . > 2000 V (MIL STD 883C method 3015.2)
Electrical Characteristics
Supply voltage to GND potential : . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.0 V to 7.0 V DC output voltage in high Z state : . . . . . . . . . . . . . . -0.5 V to +7.0 V
Operating Range
OPERATING VOLTAGE
Military Automotive Industrial Commercial (- 2) (- A) (- 9) (- 5) 5 V 10 % 5 V 10 % 5 V 10 % 5 V 10 %
OPERATING TEMPERATURE
- 55C to + 125C - 40C to + 125C - 40C to + 85C 0C to + 70C
Recommended DC Operating Conditions
PARAMETER
Vcc Gnd VIL VIH
DESCRIPTION
Supply Voltage Ground Input low voltage Input high voltage
MINIMUM
4.5 0.0 - 3.0 2.2
TYPICAL
5.0 0.0 0.0 -
MAXIMUM
5.5 0.0 0.8 VCC
UNIT
V V V V
Capacitance
PARAMETER
Cin Cout Note : (1) (1)
DESCRIPTION
Input capacitance Output capacitance
MINIMUM
- -
TYPICAL
- -
MAXIMUM
5 7
UNIT
pF pF
1. TA = 25 C, f = 1 MHz, Vcc = 5.0 V, these parameters are not 100 % tested.
DC Parameters
PARAMETER
IIX IOZ IOS VOL VOH Notes : (3) (3) (4) (5) (2)
DESCRIPTION
Input leakage current Output leakage current Output short circuit current Output low voltage Output high voltage
MINIMUM
- 10.0 - 10.0 - - 2.4
TYPICAL
- - - - -
MAXIMUM
10.0 10.0 - 300.0 0.4 -
UNIT
A A mA V V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc output disabled. 3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds. Not more than 1 output should be shorted at one time. 4. Vcc min, IOL = 8.0 mA. 5. Vcc min, IOH = - 4.0 mA.
Rev. B (21/06/94)
3
HM 65764
Consumption for Commercial (-5) Specification
SYMBOL
ICCSB (6) ICCSB1 (7) ICCOP (8)
MATRA MHS
PARAMETER
Standby supply current Standby supply current Dynamic operating current
65764 E-5
40 20 135
65764 F-5
40 20 125
65764 H-5
30 20 125
65764 K-5
30 20 125
65764 M-5
30 20 125
65764 N-5
30 20 125
UNIT
mA mA mA
VALUE
max max max
Consumption for Industrial (-9), Automotive (-A) and Military (-2) Specifications
SYMBOL
ICCSB (6) ICCSB1 (7) ICCOP (8) Notes :
PARAMETER
Standby supply current Standby supply current Dynamic operating current
65764 F-9/-2
40 20 135
65764 H-9/-2
40 20 125
65764 K-9/-2
30 20 125
65764 M-9/-2
30 20 125
65764 N-9/-2
30 20 125
UNIT
mA mA mA
VALUE
max max max
6. CS1 VIH, CS2 VIL min duty cycle = 100 %, a pull-up resistor to VCC on the CS input is required to keep the device deselected during Vcc power-up otherwise IccSB will exceed above values. 7. CS1 Vcc -0.3 V, CS2< 0.3 V, lout = 0 mA. 8. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
AC Parameters
AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output loading IOL/IOH (see figure 1a and 1b) . . . . . . . . . . . . +30 pF
AC Test Loads and Waveforms
Figure 1 a
Figure 1 b
Figure 2
4
Rev. B (21/06/94)
MATRA MHS Write Cycle : Commercial (-5) Specification
SYMBOL
TAVAV TAVWL TAVWH TDVWH TEL1WH TEH2WH TWLQZ (9) TWLWH TWHAX TWHDX TWHQX (8, 9)
HM 65764
PARAMETER
Write cycle time Address set-up time Address valid to end write Data set-up time CS1 low to write end CS2 high to write end Write low to high Z Write pulse width Address hold from end of write Data hold time Write high to low Z
65764 E-5
15 0 12 10 12 12 7 12 0 0 3
65764 F-5
20 0 15 10 15 15 7 15 0 0 5
65764 H-5
20 0 20 10 20 20 7 15 0 0 5
65764 K-5
25 0 25 15 25 20 10 20 0 0 5
65764 M-5
40 0 30 15 30 25 15 20 0 0 5
65764 N-5
50 0 40 25 40 30 20 25 0 0 5
UNIT
ns ns ns ns ns ns ns ns ns ns ns
VALUE
min min min min min min max min min min min
Write Cycle : Industrial (-9), Automotive (-A) and Military (-2) Specifications
SYMBOL
TAVAV TAVWL TAVWH TDVWH TEL1WH TEH2WH TWLQZ (8) TWLWH TWHAX TWHDX TWHQX (8, 9) Note :
PARAMETER
Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 high to write end Write low to high Z Write pulse width Address hold to end from write Data hold time Write high to low Z
65764 F-9/-2 /-A
20 0 15 10 15 15 7 15 0 0 5
65764 H-9/-2 /-A
20 0 20 10 20 20 7 15 0 0 5
65764 K-9/-2 /-A
25 0 25 15 25 20 10 20 0 0 5
65764 M-9/-2 /-A
40 0 30 15 30 25 15 20 0 0 5
65764 N-9/-2 /-A
50 0 40 25 40 30 20 25 0 0 5
UNIT
ns ns ns ns ns ns ns ns ns ns ns
VALUE
min min min min min min max min min min min
8. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Rev. B (21/06/94)
5
HM 65764
Write Cycle 1 W Controlled (note 9)
MATRA MHS
Write Cycle 2 CS1 Controlled (note 9)
Note :
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Data out is HIGH impedance if OE = VIH.
6
Rev. B (21/06/94)
MATRA MHS Read Cycle : Commercial (-5) Specification
SYMBOL
TAVAV TAVQV TAVQX TEL1QV TEH2QV TEL1QX TEH2QX TEH1QZ (11) TEL2QZ (11) TEL1IC TEH1ICCL TGLQV TGLQX TGHQZ
HM 65764
PARAMETER
READ cycle time Address access time Address valid to low Z Chip-select 1 access time Chip-select 2 access time CS1 low to low Z CS2 high to high Z CS1 high to high Z CS2 low to high Z CS1 low to power up CS1 high to power down Output enable access time OE low to low Z OE high to high Z
65764 E-5
15 15 3 15 15 3 3 8 8 0 15 10 3 8
65764 F-5
20 20 3 20 20 5 3 8 8 0 20 10 3 8
65764 H-5
25 25 3 25 25 5 3 10 10 0 20 12 3 10
65764 K-5
35 35 3 35 25 5 3 15 15 0 20 15 3 12
65764 M-5
45 45 3 45 30 5 3 15 15 0 25 20 3 15
65764 N-5
55 55 3 55 40 5 3 20 20 0 25 25 3 20
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VALUE
min max min max max min min max max min max max min max
Read Cycle : Industrial (-9), Automotive (-A) and Military (-2) Specifications
SYMBOL
TAVAV TAVQV TAVQX TEL1QV TEH2QV TEL1QX TEH2QX TEH1QZ (11) TEL2QZ (11) TEL1IC TEH1ICCL TGLQV TGLQX TGHQZ
PARAMETER
READ cycle time Address access time Address valid to low Z Chip-select 1 access time Chip-select 2 access time CS1 low to low Z CS2 high to high Z CS1 high to high Z CS2 high to high Z CS1 low to power up CS1 high to power down Output enable access time OE low to low Z OE high to high Z
65764 F-9/2 /-A
20 20 3 20 20 5 3 8 8 0 20 10 3 8
65764 H-9/-2 /-A
25 25 3 25 25 5 3 10 10 0 20 12 3 10
65764 K-9/-2 /-A
35 35 3 35 25 5 3 15 15 0 20 15 3 12
65764 M-9/-2 /-A
45 45 3 45 30 5 3 15 15 0 25 20 3 15
65764 N-9/-2 /-A
55 55 3 55 40 5 3 20 20 0 25 25 3 20
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VALUE
min max min max max min min max max min max max min min
Rev. B (21/06/94)
7
HM 65764
Read Cycle nb 1 (notes 10, 11)
MATRA MHS
Read Cycle nb 2 (notes 10, 12)
Notes : 10. W is HIGH for read cycle. 11. Device is continuously selected. CS1 & OE = VIL and CS2 = VIH. 12. Address valid prior to or coincident with CS1 transition low.
8
Rev. B (21/06/94)
MATRA MHS Burn-in Schematics
HM 65764
Vcc = 5V (-0, + 0.5) R = 1K per pin FO = 50KHz 20%
Fn = 1/2 Fn -1 S0 to S3 = programmable signals for write/read cycles. NC : Not Connected.
Ordering Information
PACKAGE HM 3 DEVICE TYPE 65764 GRADE E LEVEL -5 : R
0 - Chip form 1 - Ceramic 28 pins 300 mils 1E - Ceramic 28 pins 600 mils 3 - Plastic 28 pins 300 mils 3E - Plastic 28 pins 600 mils 4 - LCC 32 pins T- SOIC 28 pins 300 mils TP- SOIC 28 pins 330 mils U - SOJ 28 pins 300 mils
8 k x 8 high speed static RAM
E = 15 ns F = 20 ns H = 25 ns K = 35 ns M = 45 ns N = 55 ns
-A : -2 : -5 : -6 : -9 : /883 DB R RD D
Automotive Military Commercial 100% 25C Probe Industrial : MIL STD 883 Class B or S : Dice Military program : Tape & Reel option : Tape & Reel/Dry pack option : Dry pack option
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. B (21/06/94)
9

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