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FSD200
Features
* * * * * * * * * * *
Fairchild Power Switch(FPS)
Description
The FSD200 is specially designed for an off-line SMPS with minimal external components. The FSD200 is a monolithic high voltage power switching regulator that combines an LDMOS SenseFET with a voltage mode PWM control block. The integrated PWM controller features: A fixed oscillator with frequency modulation for reduced EMI. Under voltage lock out. Leading edge blanking(LEB). Optimized gate turn-on/turn-off driver. Thermal shut down protection. Temperature compensated precision current sources for loop compensation and fault protection circuitry. Compared to a discrete MOSFET and controller or RCC switching converter solution, an FSD200 can reduce total component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. It is a basic platform well suited for cost effective design of flyback converters.
7-DIP
Single Chip 700V SenseFET Power Switch Precision Fixed Operating Frequency (134kHz) Internal Start-up Switch and Soft Start UVLO with Hysteresis (6V/7V) Pulse by Pulse Current Limit Over Load Protection Internal Thermal Shutdown Function (Hysteresis) Secondary Side Regulation Auto-Restart Mode Frequency Modulation for EMI No Bias Winding
Applications
* Charger & Adaptor for Mobile Phone, PDA & MP3 * Auxiliary Power for PC, C-TV & Monitor
1.2.3.GND 4.Vfb 5.Vcc 7.Drain 8.Vstr
Internal Block Diagram
Vstr 1 Vcc 7
7V
HV/REG UVLO Voltage Ref.
INTERNAL BIAS ON/OFF
7 Drain
Frequency Modulation
5uA 250uA
Vck OSC DRIVER S Q R
BURST
SFET
Vfb 4
VBURST
LEB
OLP Reset S R
TSD His 50
Iover Q Vth
Rsense
VSD UVLO Reset (Vcc<6V)
S/S 3mS
1, 2, 3
GND
Rev.1.0.0
(c)2003 Fairchild Semiconductor Corporation
FSD200
Absolute Maximum Ratings
(Ta=25C unless otherwise specified) Parameter Maximum Vstr Pin Voltage Maximum Supply Voltage Input Voltage Range Operating Ambient Temperature Storage Temperature Range Symbol Vstr,max VCC,MAX VFB TA TSTG Value 700 10 -0.3 to VSD -25 to +85 -55 to +150 Unit V V V C C
PIN Definitions
Pin Number 1, 2, 3 Pin Name GND Pin Function Description These pins are the control ground and the SenseFET Source. This pin is the inverting input of the PWM comparator. It operates normally between 0.5V and 2.5V. It has a 0.25mA current source connected internally and a capacitor and opto coupler connected externally. A feedback voltage of 3V to 4V triggers overload protection (OLP). There is a time delay due to the 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. This is the positive supply voltage input. During start up, current is supplied to this pin from Pin 8 via an internal switch. When Vcc reaches the UVLO upper threshold (7V), the internal switch start-up switch (Vstr) opens and power is supplied from auxiliary transformer winding. This pin is designed to directly drive the converter transformer and is capable of switching a maximum of 700V. This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external capacitor that connects from the Vcc pin to ground. once this reaches 7V, the internal current source is disabled.
4
Vfb
5
Vcc
7
Drain
8
Vstr
2
FSD200
Electrical Characteristics
(Ta=25C unless otherwise specified) Parameter SENSEFET SECTION Drain-Source Breakdown Voltage Off-State Current On-State Resistence Rise Time Fall Time CONTROL SECTION Output Frequency Feedback Source Current Maximum Duty Cycle Minimum Duty Cycle Supply Regulation High Voltage Supply Regulation Low Voltage Supply Shunt Regulator Internal Soft Start Time BURST MODE SECTION Burst Mode Voltage PROTECTION SECTION Drain to Source Peak Current Limit Thermal Shutdown Temperature (Tj) (1) Shutdown Feedback Voltage Feedback Shutdown Delay Current TOTAL DEVICE SECTION Operating Supply Current Start Up Current IOP Istart Vcc = 7V Vcc = 0V 0.6 0.8 1.0 mA mA Iover TSD VSD Idelay Vfb = 4.0V Hysteresis 0.26 125 3.5 3 0.30 145 50 4.0 5 0.34 4.5 7 A C C V uA VBURST Hysteresis 0.64 60 V mV Fosc Ifb Dmax Dmin Vregh Vregl VCCreg TS/S Tj = 25C Vfb = 0V Vfb = 3.5V Vfb = 0V 126 0.22 60 0 134 4 0.25 64 0 7 6 7 3 142 0.28 68 0 kHz mA % % V V V mS BVdss Idss RDS(ON) TR TF VCC = 0V, ID = 100A VDS = 560V Tj = 25C, ID = 25mA Tj = 100C, ID = 25mA VDS = 325V, ID = 50mA VDS = 325V, lD = 25mA 700 28 42 100 50 100 32 48 V A nS nS Symbol Condition Min. Typ. Max. Unit
Note: 1. These parameters, although guaranteed, are not 100% tested in production
3
FSD200
Typical Performance Characteristics
(These characteristic graphs are normalized at Ta=25C)
O u tp u t Fre q u e n c y 1.2 1 0.8 0.6 0.4 0.2 0 -25 0 25 50 Fo s c 75 100 125
0.8 0.75 0.7 0.65 0.6 0.55 0.5 -25 0
O pe r a ti ng Cur re n t
25
50
75
100
125
O pe ra t in g Cu rr e nt
Temp
Figure 1. Freqency vs. Temp
Figure 2. Operating Current vs. Temp
Over Current 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -25 0 25 50 Iover 75 100 125
Feedback Current 1.2 1 0.8 0.6 0.4 0.2 0 -25 0 25 50 75 100 125 Feedback Current
Figure 3. Peak Current Limit vs. Temp
Figure 4. Feedback Source Current vs. Temp
Shutdow n Feedback Voltage 1.2 1 0.8 0.6 0.4 0.2 0 -25 0 25 50 75 100 125
Shutdow n Feedback Voltage
Figure 5. ShutDown Feedback Voltage vs. Temp
Figure 6. Operating Current vs. Vcc Voltage
4
FSD200
Typical Performance Characteristics (Continued)
(These characteristic graphs are normalized at Ta=25C)
On_State_Resistance 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -25 0 25 50 Rds(on) 75 100 125
900 850 800 750 700 650 -25 0
Breakdow n Voltage
25
50
75
100
125
Breakdow n Voltage
Figure 7. On State Resistance vs. Temp
Figure 8. Breakdown Voltage vs. Temp
5
FSD200
Typical Circuit
+
Snubber Circuit
+
+
Load
FSD200
PWM
Feedback Circuit
+
6
FSD200
Product Information
Basic system topology of FSD200/210 is the same as the original FSDH565/0165 devices. The FSD210 devices require a bias winding, whereas the FSD200 devices do not. Other features of the two types of devices are almost the same and are listed below.
Product Parameter Breakdown voltage (min) On-state Resistance (max) Current Limit (typ.Iover) Switching Frequency Frequency Modulation Operating Current (max) Burst function Thermal Shutdown(typ.) Package Type Output Power 85~265VAC With Bias Winding FSD210 700V BCDMOS 32ohm 0.3A 134kHz 4kHz 770uA o 145(Hys 50) 7DIP/7SMD 4W FSD211 700V BCDMOS 18ohm 0.48A 134kHz 4kHz 770uA o 145(Hys 50) 7DIP/7SMD 6W Without Bias Winding FSD200 700V BCDMOS 32ohm 0.3A 134kHz 4kHz 770uA o 145(Hys 50) 7DIP/7SMD 4W FSD201 700V BCDMOS 18ohm 0.48A 134kHz 4kHz 770uA o 145(Hys 50) 7DIP/7SMD 6W
the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increase pulling down the feedback voltage and reducing the duty cycle. This will happen when the input voltage increases or the output load decreases. 3. Leading edge blanking (LEB) : When the MOSFET turns on, there will usually be a large current spike through the MOSFET. This is caused by primary side capacitance and secondary side rectifier reverse recovery. This could cause premature termination of the switching pulse if it exceeded the over-current threshold. Therefore, the FPS uses a leading edge blanking (LEB) circuit. This circuit inhibits the pvercurrent comparator for a short time after the MOSFET is turned on.
Figure 1. Line-up Table
Vcc 5uA
OSC
Vref 0.25mA Gate driver R
Functional Description
1. Startup : At startup, an internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in Figure 1. In the case of the FSD210, when Vcc reaches 8.7V the device starts switching and the internal high voltage current source is disabled. The device continues to switch provided that Vcc does not drop below 6.7V. After startup the bias is supplied from the auxiliary transformer winding. In the case of FSD200, Vcc is continuously supplied from the external high voltage source and Vcc is regulated to 7V by an internal high voltage regulator (HV Reg). The internal startup switch is not disabled and an auxiliary winding is not required. Figure 2.
Vin,dc Istr Vin,dc Istr
Vo
Vfb
FB 4
Cfb
KA431
VSD
OLP
Figure 3. PWM and feedback circuit
Vstr Vcc
Vcc<6.7V on Vcc>8.7V off
Vstr Vcc 7V HV Reg.
FSD21x
FSD20x
4. Protection Circuit : The FSD200/210 has 2 self protection functions: over-load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC with no external components, system reliability is improved without cost increase. If either of these functions are triggered, the FPS starts an auto-restart cycle. Once the fault condition occurs, switching is terminated and the MOSFET remains off. This cause Vcc to fall. When Vcc reaches the UVLO stop voltage (6.7:FSD210, 6V:FSD200), the protection is reset and the internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage (8.7V:FSD210, 7V:FSD200), the device attempts to resume normal operation. If the fault condition is no longer present start up will be successful. If it is still present the cycle is repeated. This is shown in Figure 4.
Figure 2. Internal startup circuit
2. Feedback Control : The FSD200/210 are voltage mode devices as shown in Figure 3. Usually, an optocoupler and KA431 type voltage reference are used to implement the feedbacknetwork. The feedback voltage is compared with an internally generated sawtooth waveform. This directly controls the duty cycle. When
7
FSD200
Vfb
OSC
10V
5uA
250uA
Vfb
4 R
+ 3V OLP
S R
Q
GATE DRIVER
OLP 4V 3V FPS Switching Area
Cfb
S
RESET
Q
Vth 4V
TSD His 50
R
/8
FSD2xx OLP, TSD Protection Block
Idelay (5uA) charges Cfb
Figure 4. Protection block
t t1 t2 t3
4.1 Over Load Protection (OLP) : Overload is a load current that exceeds a pre-set level due to an abnormal situation. If this occurs, the protection circuit should be triggered to protect the SMPS. It is possible that a short term load transient can occur under normal operation. If this occurs the system should not shut down. In order to avoid false shut-downs, the over load protection circuit is designed to trigger after a delay. Therefore the device can discriminate between transient overloads and true faul conditions. The device is pulse-by-pulse current limited and therefore, for a given input voltage, the maximum input power is limited. If the load tries to draw more than this, the output voltage will drop below its set value. This reduces the opto-coupler LED current which in turn will reduce the photo-transistor current. Therefore, the 250uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will increase. The input to the feedback comparator is clamped at around 3V. Therefore, once Vfb reaches 3V, the device is switching at maximum power. At this point the 250uA current source is blocked and the 5uA source continues to charge Cfb. Once Vfb reaches 4V, switching stops. Therefore the shutdown delay time is set by the time required to charge Cfb from 3V to 4V with 5uA as shown in Fig. 5.
t1<v(t1)=3V [v(t1+t2)-v(t1)]=1V, Idelay=5uA
Figure 5. Over load protection delay
4.2 Thermal Shutdown (TSD) : The SenseFET and the control IC are assembled in one package. This makes it easy for the control IC to detect the temperature of the SenseFET. When the temperature exceeds approximately 150C, thermal shutdown is activated. Thermal shutdown has a Hysteresis of 50C and so the temperature must drop to 100C before the device attempts to restart.
Temperature
TSD( )
FPS Switching Area TSD - 50
TSD Hysteresis t
5. Soft Start : FSD200/210 has an internal soft start circuit that increases the feedback voltage together with the MOSFET current slowly at start up. The soft start time is 3msec in FSD200/210.
8
FSD200
I(A)
3mS 0.25A 0.2A 0.3A
Iover
Vo
Voset
VFB
0.6V 0.5V
t
FSD200/210
Ids
6. Burst operation : In order to minimize the power dissipation in standby mode, the FSD200/210 implements burst mode.
Vds
time
OSC
S 5uA 4 250uA R
on/off
Q
GATE DRIVER
Figure 7. Burst mode operation
7. Frequency Modulation
Vfb
0.6V /0.5V
130kHz
C
FSD2xx Burst Operation Block
132kHz 133kHz 134kHz
131kHz
B
Figure 6. Circuit for burst operation
136kHz
135kHz
As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below 0.5V. At this point switching stops and the output voltages start to drop. This causes the feedback voltage to rise. Once is passes 0.6V switching starts again. The feedback voltage falls and the process repeats. Burst mode operation alternately enables and disables switching of the power MOSFET to reduce the switching loss in the standby mode.
137kHz 138kHz
A
2mS
Sawtooth waveform Vfb
138kHz
134kHz
130kHz
Vdrain
Ton
Idrain
A
B
C
9
FSD200
Typical application circuit
1. Cellular Phone Charger Example Circuit
C6 152M-Y, 250Vac
R6
R7
4.7M 1/4W 4.7M, 1/4W L1 330uH AC Fuse 1W, 10R AC D3 1N4007 D4 1N4007 D1 1N4007 D2 1N4007 C1 4.7UF 400V C2 4.7uF 400V R1 4.7k 1 R3 47k R4 47k C3 102k 1kV TX1 7 D7 SB260
0
L3 4uH C7 330uF 16V R9 56R U3 H11A817B Vo
(5.2V/0.65A)
R10 2.2k C8 330uF 16V
2
8
R8 510R
.
C9 470nF D5 UF4007 C10 4.7uF 50V U2 TL431 R12 2k
7
Drain
Vcc Vfb GND
5 4 H11A817B
D6
R5
1
Q1 KSP2222A
0
TH1 10k R19 510R R15 3R0 R16 3R0
8 U1 FSD210
1N4148 39R 3 C5 33uF 50V 4
Vstr GND 1
2
GND
3
R17 3R0
For FSD21x
0
C4 100nF
Reference D1,D2,D3,D4 D5 D6 D7 Q1 U1 U2 U3
Part # 1N4007 UF4007 1N4148 SB260 KSP2222A FSD210 (FSD200) KA431AZ H11A817A
Quantity 4 1 1 1 1 1 1 1
Description 1A/1000V Junction Rectifier 1A/1000V Ultra Fast Diode 10mA/100V Junction Diode 2A/60V Schottky Diode Ic=600mA, Vce=30V 0.5A/700V Vref=2.495V(Typ.) CTR 80~160%
Requirement/Comment DO41 Type DO41 Type D0-213 Type D0-41 Type TO-92 Type Iover=0.3A, Fairchildsemi TO-92 Type, LM431 -
1. Schematic diagram(Top view)
2mm
1 8
2mm
2
7
W4 W3
3
6
W2 W1
4
5
2. Core & Bobbin
CORE : EE1616 BOBBIN : EE1616(H)
3 . W in d in g s p e c if ic a t io n
No. W1 W2 P in ( S F ) in 1 2 W ir e 0 .1 6 1 0 .1 6 1 T u rn s 99 Ts 18 Ts W in d i n g M e t h o d in S O L E N O ID W IN D IN G C E N T E R S O L E N O ID W IN D I N G S O L E N O ID W IN D IN G S O L E N O ID W IN D IN G
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 2 T s 43
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 2 T s W3 W4 1 open 87 0 .1 6 1 0 .4 0 1 50 Ts 9 Ts I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 3 T s I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 3 T s
4 . E le c t r ic a l c h a r a c t e r is t ic tic
IT E M IN D U C T A N C E LEAKAG E L T E R M IN A L IN 1-2 1-2 S P E C I F IC A T I O N 1 .6 m H 50uH REM ARKS 1kH z, 1V 3 ,4 ,7 , 8 s h o r t 100kH z, 1V
10
FSD200
Typical application circuit
Vin,dc D2 Vcc Vfb GND 5 4 R2 100 ZD1 1N759A UF4004 7 Drain
2. Buck Convertor
Vin,dc D2 Vcc Vfb GND 5 4 R2 100 ZD1 1N759A R1 100 Q1 2N3904 R3 750 L1 12V UF4004 C4 680uF 16V GND 1mH C4 680uF 16V GND R4 5.6k UF4004 Drain GND 7 8 U1 FSD20x C3 47uF 25V C1 4.7uF/400V Vstr GND
8 U1 FSD21x C1 4.7uF/400V
Vstr GND
GND
R1 100 C2 10uF/50V Q1 2N3904
C5 4.7uF/50V
C3 47uF 25V
1
2
C2 10uF/50V R3 750 L1 12V GND 1mH D1
D1 GND UF4004
0
0
Reference D1,D2 Q1 ZD1 U1
Part # UF4007 2N3904 1N759A FSD210 (FSD200)
Quantity 2 1 1 1
Description 1A/1000V Ultra Fast Diode Ic=200mA, Vce=40V 12V 0.5W 0.5A/700V
Requirement/Comment DO41 Type TO-92 Type DO-35 Type Iover=0.3A, Fairchild
3
1
2
3
11
FSD200
Package Dimensions
7-DIP
12
FSD200
Ordering Information
Product Number FSD200 Package 7DIP Rating 700V, 0.5A Topr (C) -25C to +85C
13
FSD200
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 8/28/03 0.0m 001 Stock#DSxxxxxxxx 2003 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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