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HI1276
August 1997
8-Bit, 500 MSPS, Flash A/D Converter
Description
The HI1276 is an 8-bit, ultra-high-speed, flash Analog-toDigital converter IC capable of digitizing analog signals at a maximum rate of 500 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. The HI1276 is available in the Industrial temperature range and is supplied in a 68 lead ceramic LCC package.
Features
* Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.7 LSB * Built-In Integral Linearity Compensation Circuit * Ultra High Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . 500 MSPS * Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 20pF * Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 300MHz * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V * Low Power Consumption (Typ) . . . . . . . . . . . . . . . 2.8W * Low Error Rate * Capable of Driving 50 Loads * Direct Replacement for Sony CXA1276K
Ordering Information
PART NUMBER HI1276AIL HI1276-EV TEMP. RANGE (oC) -20 to 100 25 PACKAGE 68 Ld CLCC PKG. NO. J68.B
Evaluation Board
Applications
* Radar Systems * Communication Systems * Digital Oscilloscopes * Direct RF Down-Conversion
Pinout
HI1276 (CLCC) HEAT SINK UP, RECESSED CAVITY DOWN
DGND1 60 DGND2 59 D2 58 D2 57 DVEE 56 D3 55 D3 54 DGND2 53 DGND2 52 DGND1 51 DGND1 50 D4 49 D4 48 DVEE 47 D5 46 D5 45 NC 44 DGND2 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 D7 D7 D6 AGND VRB AVEE AVEE NC AVEE AVEE D6 DVEE MINV CLK CLK DGND1 VRBS AGND DVEE AVEE AVEE AVEE AVEE VRTS LINV VRT OR OR NC
D0
D0
D1
9 NC 10 NC 11 AVEE 12 NC 13 AGND 14 VIN1 15 VIN1 16 AGND 17 VRM 18 AGND 19 VIN2 20 VIN2 21 AGND 22 NC 23 NC 24 NC 25 NC 26
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
D1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3578.4
4-1
HI1276 Functional Block Diagram
MINV R1 VRT VRTS 6 5 R2 R 1 R 39 D7 (MSB) 2 R 38 D7 41 D6 40 D6 63 VIN1 15 16 R 64 R 65 OUTPUT 47 D5 46 D5 50 D4 49 D4 56 D3 R 126 R R3 VRM 18 R 128 R 66 D0 (LSB) 129 65 D0 R 191 R VIN2 20 21 192 R 193 127 ENCODE LOGIC 55 D3 59 D2 58 D2 64 D1 63 D1 R/2 0 68 OR 67 OR 37 COMPARATOR
R 254 R VRBS 31 VRB 30 R5 CLK 35 CLK 36 CLOCK DRIVER 1 LINV R4 R/2 255
4-2
HI1276
Absolute Maximum Ratings TA = 25oC
Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7 to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . AVEE to +0.5V |VRT - VRB |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V CLK, CLK, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DVEE to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7, IOR, ID0 to ID7, IOR) . . . . . . . . . . . . . -30mA to 0mA
Thermal Information
Thermal Resistance (Typical) JAoC/W JCoC/W CLCC Package . . . . . . . . . . . . . . . . . . 18 4 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
(Note 1) MAX -4.95V 0.05V 0.05V 100oC Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Voltage, VIN . . . . . . . . . . . . . . MIN -0.1V -2.2V VRB TYP -2 -2
-
Supply Voltage MIN TYP AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V -5.2V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . .-0.05V 0V AGND - DGND . . . . . . . . . . . . . . . . . . . . .-0.05V 0V Temperature Range (Note 5) TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20oC -
MAX 0.1V -1.8V VRT
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL DYNAMIC CHARACTERISTICS
TA = 25oC, AVEE = DVEE = -5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNITS
fC = 500 MSPS fC = 500 MSPS -
8 0.3 0.3
0.7 0.5
Bits LSB LSB
Signal to Noise and Distortion Ratio, SINAD Input = 1kHz, Full Scale fC = 500 MSPS RMS Signal = ----------------------------------------------------------------Input = 100MHz, Full Scale RMS Noise + Distor tion fC = 500 MSPS Error Rate Input = 100MHz, Full Scale Error > 16 LSB, fC = 400 MSPS Input = 125MHz, Full Scale Error > 16 LSB, fC = 500 MSPS Differential Gain Error, DG Differential Phase Error, DP Overrange Recovery Time Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUT Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN Full Scale Input Bandwidth REFERENCE INPUTS Reference Resistance, RREF VIN = -1V VIN = 2VP-P VIN = 1V + 0.07VRMS Input = 150MHz Input = 150MHz NTSC 40 IRE Mod. Ramp, fC = 500 MSPS
500 0.2
46 37 10-11 10-8 1.0 0.5 1.0 11 0.8
10-9 10-6 1.5
dB dB TPS (Note 3) TPS (Note 3) % Degree ns MSPS ps ns
30 300
20 70 -
850 -
pF k A MSPS
70
110
160
4-3
HI1276
Electrical Specifications
PARAMETER Residual Resistance R1 R2 R3 R4 R5 DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL TIMING CHARACTERISTICS Clock Duty Cycle Output Rise Time, tr Output Fall Time, tf Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. ( V RT - V RB ) 4. P D = I EEA * AV EE + I EED * DV EE + ------------------------------------ . R
REF 2
TA = 25oC, AVEE = DVEE = -5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) (Continued) TEST CONDITIONS Note 2 MIN 0.1 0.5 0.5 0.5 0.1 TYP 0.5 5.2 1.6 8.7 0.5 MAX 2.0 10 5.0 20 2.0 UNITS
-1.10 Input Connected to -0.8V Input Connected to -1.6V 0 -50 -
6
-1.55 70 60 -
V V A A pF
RL = 50 RL = 50
-1.03 -
-
-1.58
V V
45 RL = 50, 20% to 80% RL = 50, 80% to 20% 0.5 0.5 1.5
50 0.7 0.7 1.9
55 1.0 1.0 2.3
% ns ns ns
-680 Note 4 -
-520 2.8
3.6
mA W
5. TA is specified in still air and without heatsink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2).
Timing Diagram
ANALOG IN tDS N+1 tPW1 CLK CLK tPW0 N+2
DIGITAL OUT tOD
N-1
20%
80%
N
80%
N+1 20% tf
tr
FIGURE 1.
4-4
HI1276 Typical Performance Curves
20 THERMAL RESISTANCE JA (oC/W) -0.45
-0.47 SUPPLY CURRENT (A)
-0.49
10
-0.51
-0.53
0 0 1 2 AIR FLOW (m/s) 3
-0.55 -50
0
50
100
150
CASE TEMPERATURE (oC)
FIGURE 2. THERMAL RESISTANCE MOUNTED ON-BOARD
FIGURE 3. SUPPLY CURRENT vs TEMPERATURE CHARACTERISTICS
-0.80 REGISTER STRING CURRENT (mA) 0 50 100 150
-14
-0.85 HIGH LEVEL VOLTAGE (V)
-16
-09.0
-18
-0.95
-20
-1.00
-1.05 -1.10 -50
-22
-24 -50
0
50
100
150
CASE TEMPERATURE (oC)
CASE TEMPERATURE (oC)
FIGURE 4. DO PIN HIGH LEVEL VOLTAGE vs TEMPERATURE CHARACTERISTICS
FIGURE 5. REGISTER STRING CURRENT vs TEMPERATURE CHARACTERISTICS
-1.55
-1.30
CLK PIN OPEN VOLTAGE (V) 0 50 100 CASE TEMPERATURE (oC) 150
-1.60 LOW LEVEL VOLTAGE (V)
-1.32
-1.65
-1.34
-1.70
-1.36
-1.75
-1.80 -1.85 -50
-1.38
-1.40 -50 0 50 100 150 CASE TEMPERATURE (oC)
FIGURE 6. D0 PIN LEVEL VOLTAGE vs TEMPERATURE CHARACTERISTICS
FIGURE 7. CLK PIN OPEN VOLTAGE vs TEMPERATURE CHARACTERISTICS
4-5
HI1276 Typical Performance Curves
50
(Continued)
-20
45 HARMONICS (dB)
-30
40 SINAD (dB)
-40 THIRD HARMONIC -50 SECOND HARMONIC -60
35
30
25
-70
20 1 10 INPUT FREQUENCY (MHz) 100 500
-80 1 10 INPUT FREQUENCY (MHz) 100 500
FIGURE 8. SINAD vs INPUT FREQUENCY CHARACTERISTICS
FIGURE 9. HARMONIC DISTORTION vs INPUT FREQUENCY CHARACTERISTICS
10-6
10-6 INPUT FREQUENCY = CLOCK FREQUENCY/4 + 1kHz 16 LSB OR MORE ERROR 10-7 ERROR RATE (TPS)
10-7 ERROR RATE (TPS)
10-8
10-8
10-9
10-9 CLOCK FREQUENCY: 500 MSPS INPUT FREQUENCY: 125.001MHz FULL SCALE 16 LSB OR MORE ERROR
10-10 450
10-10 500 550 600 0 CLK FREQUENCY (MHz) 50 CLK DUTY CYCLE (%) 100
FIGURE 10. ERROR RATE vs CONVERSION FREQUENCY CHARACTERISTICS
FIGURE 11. ERROR RATE vs CLOCK DUTY CYCLE CHARACTERISTICS
10-3 10-4 ERROR RATE (TPS) 10-5 10-6 10-7 10-8 10-9 10-10
INPUT FREQUENCY = CLOCK FREQUENCY/ 4 + 1kHz FULL SCALE INPUT CLOCK FREQUENCY 500 MSPS 550 MSPS 450 MSPS
012345678
12 16 24 THRESHOLD LEVEL (LSB)
32
FIGURE 12. ERROR RATE vs THRESHOLD LEVEL CHARACTERISTICS
4-6
HI1276 Pin Descriptions
PIN NUMBER SYMBOL 1 LINV I/O I STANDARD VOLTAGE LEVEL ECL EQUIVALENT CIRCUIT
DGND1 43 52 51 61 R R LINV 1 OR MINV 37 R -1.3V
DESCRIPTION Polarity Selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open. Polarity Selection for MSB (refer to the A/D Output Code Table). Pulled low when left open.
37
MINV
R 42 57 48 62 DVEE
6
VRT VRTS VRM VRBS VRB
I
0V
VRT 6
Analog Reference Voltage (Top) (0V Typ).
R2 R1
5 18
O I
0V VRB/2 -2V -2V
VRTS 5
Reference Voltage Sense (Top). Reference Voltage Mid Point. Can be used for linearity compensation. Reference Voltage Sense (Bottom). Analog Reference Voltage (Bottom).
R/2
31 30
O I
R
VRM 18
R3 R
TO COMPARATORS
R VRBS 31 VRB 30 R5
R4
R/2
15, 16 20, 21
VIN1 VIN2
I
VRTS to VRBS
VIN1 15 16 20 21 VIN2
AGND
9, 14, 17, 19, 22, 27
Analog Input. All of the pins must be wired externally.
TO COMP. 0 TO 127 128 TO 255
4-7
HI1276 Pin Descriptions
PIN NUMBER SYMBOL 35 36 CLK CLK I/O I (Continued) STANDARD VOLTAGE LEVEL ECL
DGND1 43 51 52 61 CLK 35 CLK 36 42 48 57 62 DVEE R R R R R R
EQUIVALENT CIRCUIT
DESCRIPTION CLK Input. Complementary CLK Input. Pulled down to -1.3V when left open.
38, 39 40, 41 46, 47 49, 50 55, 56 58, 59 63, 64 65, 66 67, 68 2, 3, 7, 8, 12, 28, 29, 33, 34 9, 14, 17, 19, 22, 27 42, 48, 57, 62 43, 51, 52, 61 44, 53, 54, 60
D7, D7 D6, D6 D5, D5 D4, D4 D3, D3 D2, D2 D1, D1 D0, D0 OR, OR AVEE
O
ECL
44 54 DI
53 DGND2 60
MSB and Complementary Msb Data Output. D1 to D6: Data output D1 to D6: Complementary data output
DI
42 DVEE 57
48 62
LSB Data Complementary Output LSB Data Output. Overrange and Complementary Overrange Output.
60
-
-5.2V
9 14
AGND 17 19 22 27
DGND1 43 51 52 61 44
DGND2 53 54
Analog Supply. Internally connected to DVEE (resistance: 4 to 6). Analog Ground.
AGND
0V
INTERNAL ANALOG CIRCUIT INTERNAL DIGITAL CIRCUIT 4 TO 6 D1 D1
DVEE DGND1
-5.2V
Digital Supply. Internally connected to AVEE (resistance: 4 to 6). Digital Ground.
0V
2 3
8 12 28 AVEE
29 33 34
42 48
57 62
DGND2 (Note 6)
0V
7
DVEE
Digital Ground for Output Drive.
4, 10, 11, 13, 23, 24, 25, 26, 32 45 NOTE:
NC
No-Connect pins. It is recommended to wire these pins to AGND.
NC
No-Connect pin. It is recommended to wire these pins to DGND.
6. VRT = VRTS = 0V, VRM = -1V or open, VRB = VRBS = -2V
4-8
HI1276
A/D OUTPUT CODE TABLE (NOTE 1) VIN 0V 0 1 MINV 1, LINV 1 STEP OR 1 0 0 D7 D0 OR 1 0 0 0, 1 D7 D0 OR 1 0 0 1, 0 D7 D0 OR 1 0 0 0, 0 D0 D7
000 * * * * * 00 000 * * * * * 00 000 * * * * * 01 * * * 011 * * * * * 11 100 * * * * * 00 * * * 111 * * * * * 10 111 * * * * * 11 111 * * * * * 11
100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11
011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 100 * * * * * 00
111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 000 * * * * * 00
-1V
127 128
0 0
0 0
0 0
0 0
254 255 -2V
0 0 0
0 0 0
0 0 0
0 0 0
Test Circuits
FUNCTION GENERATOR 100 1 2 NTSC SIGNAL SOURCE AMP 2 VIN DUT HI1276 CLK CLK 21 -4.5V SG (CW) 50 DUTY DIVIDER SWITCH POSITION 1. MAXIMUM CONVERSION RATE 2. DG/DP VECTOR SCOPE DG/DP OSCILLOSCOPE MAXIMUM CONVERSION RATE 8 110 ECL LATCH 100 8 110 HI20201 10 BIT D/A AMP fms 0V -2V
FIGURE 13. MAXIMUM CONVERSION RATE AND DIFFERENTIAL GAIN/PHASE ERROR TEST CIRCUIT
+V
S2
+ S1
S1 : A < B : ON S2 : A > B : ON
-V AB 8
COMPARATOR A8 TO A1 A0 B8 TO B1 B0 BUFFER
DVM "0" CLK (250 MSPS)
"1" 8 000 * * * 00 TO 111 * * * 10
CONTROLLER
FIGURE 14. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
4-9
HI1276 Test Circuits
(Continued)
-5.2V A IEED
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
HI1276
-2V
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A IEEA -5.2V -1V
A IIN
FIGURE 15. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT
VIN
0V -1V -2V
100MHz AMP OSC1 : VARIABLE VIN fR CLK OSC2 100MHz ECL BUFFER HI1276 8 LOGIC ANALYZER 1024 SAMPLES CLK CLK
t VIN
t
129 128 127 126 125
(LSB)
APERTURE JITTER
Aperture jitter is defined as follows: 256 t AJ = ------ = --------- x 2f , 2 t Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 16A. FIGURE 16B. APERTURE JITTER TEST METHOD
FIGURE 16. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
4-10
HI1276
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-11

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