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HCS195MS
September 1995
Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
MR J K D0 D1 1 2 3 4 5 6 7 8 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 Q3 10 CP 9 PE
Features
* 3 Micron Radiation Hardened CMOS SOS * Total Dose 200K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s
* Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Fanout (Over Temperature Range) - Standard Outputs - 10 LSTTL Loads * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min * Input Current Levels Ii 5A at VOL, VOH
MR J
D2 D3 GND
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Q3 CP PE
Description
The Intersil HCS195MS is a Radiation Hardened 8-Bit Parallel-In/Serial-Out Shift Register with complementary serial outputs and an asynchronous parallel load input. The HCS195MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS195MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
K D0 D1 D2 D3 GND
Ordering Information
PART NUMBER HCS195DMSR HCS195KMSR HCS195D/Sample HCS195K/Sample HCS195HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
280
518760 3385.1
HCS195MS Functional Diagram
D0 D1 D2 D3
PE
CP
P J TG N CL DP PL DS Q MR P K TG N CL DP PL DS Q MR CL DP PL DS Q MR CL DP PL DS Q MR
MR
Q0
Q1
Q2
Q3
Q3
TRUTH TABLE INPUTS MR L H H H H H CP X PE X h h h h l J X h l h l X K X h l l h X Dn X X X X X dn Q0 L H L q0 q0 d0 Q1 L q0 q0 q0 q0 dl OUTPUTS Q2 L ql ql ql ql d2 Q3 L q2 q2 q2 q2 d3 Q3 H q3 q3 q3 q3 d3
Dn or Qn = referenced input (or output) one set-up time prior to clock l or h = level one set-up time prior to clock = positive clock
Spec Number 281
518760
Specifications HCS195MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (All voltage reference to VSS)
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . . .10ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . VCC to 70% of VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, IOH = -50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOH = -50A, VIL = 1.65V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 40 750 0.1 UNITS A A mA mA mA mA V
PARAMETER Quiescent Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Current (Source)
IOH
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC, +125oC, -55oC
0.5 5.0 -
A A -
Noise Immunity Functional Test
FN
VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3)
7, 8A, 8B
NOTES: 1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 282
518760
Specifications HCS195MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 9 10, 11 9 10, 11 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 2 2 2 2 2 2 2 MAX 31 37 34 42 32 39 32 39 UNITS ns ns ns ns ns ns ns ns
PARAMETER Propagation Delay (CP - Qn) Propagation Delay (CP - Qn) Propagation Delay (MR - Q0-3) Propagation Delay (MR - Q3) NOTES:
SYMBOL TPHL1
(NOTES 1, 2) CONDITIONS VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0
TPLH1
TPHL2
TPLH2
1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5V, VIL = 0.0V LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC TSU VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC Hold Time TH VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC MR to CP Removal Time Recovery Time PL to CP Maximum Clock Frequency Output Transition Time TREM VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC TREC VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC FMAX VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC TTHL TTLH VCC = 4.5V, VIH = 4.5V, VIL = 0.0V +25oC +125oC, -55oC MIN 16 24 20 20 3 3 16 24 20 30 30 20 1 1 MAX 90 120 10 10 20 20 15 22 UNITS pF pF pF pF pF pF ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
PARAMETER Capacitance Power Dissipation Input Capacitance
SYMBOL CPD
CIN
Output Capacitance
COUT
Pulse Width Time (CP or MR) Setup Time
TW
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 283
518760
Specifications HCS195MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER Supply Current Output Current (Sink) Output Current (Source) Output Voltage Low SYMBOL ICC IOL IOH (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 VCC = VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0 VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50A VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50A VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) VCC = 4.5V, VIH = 4.5V, VIL = 0V TEMPERATURE +25oC +25oC +25oC MIN 4.0 -4.0 MAX 0.75 UNITS mA mA mA
VOL
+25oC
-
0.1
V
Output Voltage High
VOH
+25oC
VCC -0.1 -
-
V
Input Leakage Current Noise Immunity Functional Test Propagation Delay (CP - Qn) Propagation Delay (CP - Qn) Propagation Delay (MR - Q0-3) Propagation Delay (MR - Q3)
IIN FN
+25oC +25oC
5 -
A -
TPHL1
+25oC
2
37
ns
TPLH1
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25oC
2
42
ns
TPHL2
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25oC
2
39
ns
TPLH2
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25oC
2
39
ns
NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
PARAMETER ICC IOL/IOH
DELTA LIMIT 12A -15% of 0 Hour
Spec Number 284
518760
Specifications HCS195MS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11, (Note 2) ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TEST METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1,9 POST RAD Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1) 11 - 15 1 - 10 16 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 15 8 1 - 7, 9 - 10, 16 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10k 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1k 5% for dynamic burn-in 8, 9 1 - 3, 16 11 - 15 10 4-7
TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 11 - 15 GROUND 8 VCC = 5V 0.5V 1 - 7, 9 - 10, 16
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 285
518760
HCS195MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 286
518760
HCS195MS AC Timing Diagram
VIH VS VIL CL TPLH TPHL VOH VS VOL TTLH 80% VOL 20% 80% 20% TTHL OUTPUT CL = 50pF RL = 500 RL INPUT
AC Load Circuit
DUT TEST POINT
VOH
OUTPUT
AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V
Pulse Width, Setup, Hold Timing Diagram Load Circuit Positive Edge Trigger DUT
TW INPUT VIH VIL TSU CP INPUT VIH VIL TH TW VS CL = 50pF RL = 500 CL RL
TEST POINT
TH = Hold Time TSU = Setup Time TW = Pulse Width AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V
Spec Number 287
518760
HCS195MS Die Characteristics
DIE DIMENSIONS: 95 x 94 mils 2.380 x 2.410mm METALLIZATION: Type: AlSi Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 x 4 mils
Metallization Mask Layout
HCS195MS
J (2) MR (1) VCC (16) Q0 (15) Q1 (14)
K (3) (13) Q2
D0 (4) (12) Q3
D1 (5) (11)Q3
(6) D2
(7) D3
(8) GND
(9) PE
(10) CP
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS195 is TA14387A.
Spec Number 288
518760

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