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HM-6518
March 1997
1024 x 1 CMOS RAM
Description
The HM-6518 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed overtemperature.
Features
* Low Power Standby . . . . . . . . . . . . . . . . . . . . 50W Max * Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min * TTL Compatible Input/Output * High Output Drive - 2 TTL Loads * High Noise Immunity * On-Chip Address Register * Two-Chip Selects for Easy Array Expansion * Three-State Output
Ordering Information
PACKAGE CERDIP TEMP. RANGE -40oC to +85oC 180ns HM16518B-9 250ns HM16518-9 PKG. NO. F18.3
Pinout
HM-6518 (CERDIP) TOP VIEW
S1 E A0 A1 A2 A3 A4 Q GND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5
PIN A E W S D Q
DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2987.1
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HM-6518 Functional Diagram
A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 G 32 GATED COLUMN DECODER AND DATA I/O D LATCH A L W A E 5 A 5 Q Q GATED ROW DECODER 32 32 x 32 MATRIX
D
A
LATCHED ADDRESS REGISTER
S1, S2
A0 A1 A2 A3 A4
NOTES: 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Data latches: L high Q = D; Q Latches on rising edge of L. 4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6518
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6518B-9, HM-6518-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9) LIMITS
PARAMETER Standby Supply Current
SYMBOL ICCSB
MIN -
MAX 10
UNITS A mA A A V A A V V V V
TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, VI = VCC or GND, VCC = 5.5V VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
Operating Supply Current (Note 1) Data Retention Supply Current HM-6518B-9 HM-6518-9 Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
ICCOP
-
4
ICCDR
-
5 10 +1.0 +1.0 0.8 VCC +0.3 0.4 -
VCCDR II IOZ VIL VIH VOL VOH
2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4
VI = VCC or GND, VCC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 3.2mA, VCC = 4.5V IO = -0.4mA, VCC = 4.5V
Capacitance
TA = +25oC SYMBOL CI CO MAX 6 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) NOTES:
1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
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HM-6518
AC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9) LIMITS HM-6518B-9 PARAMETER Chip Enable Access Time Address Access Time Chip Select Output Enable Time Write Enable Output Disable Time Chip Select Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Select Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. SYMBOL
(1) TELQV (2) TAVQV (3) TSLQX (4) TWLQZ (5) TSHQZ (6) TELEH (7) TEHEL (8) TAVEL (9) TELAX (10) TDVWH (11) TWHDX (12) TWLSH (13) TWLEH (14) TSLWH (15) TELWH (16) TWLWH (17) TELEL
HM-6518-9 MIN 5 250 100 0 50 110 0 130 130 130 130 130 350 MAX 250 250 160 160 160 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
MIN 5 180 100 0 40 80 0 100 100 100 100 100 280
MAX 180 180 120 120 120 -
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HM-6518 Timing Waveforms
(8) TAVEL A TEHEL E (7) HIGH (9) TELAX VALID TELEL TELEH (6) TEHEL (7) (8) TAVEL NEXT (17)
W D
TELQV (1) TAVQV (2) Q S1, 1 S2 TIME REFERENCE -1 0 1 2 3 4 5 PREVIOUS DATA TSHQZ HIGH Z VALID OUTPUT LATCHED (5) TSLOX (3) (5) TSHQZ HIGH Z
FIGURE 1. READ CYCLE
TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 H L L E H S1 H X L L L H W X H H H H X A X V X X X X D X X X X X X OUTPUTS Q Z Z X V V Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Output Latched Device Disabled, Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
5
X
H
V
X
Z
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
In the HM-6518 read cycle the address information is latched into the on chip registers on the falling edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required hold time the addresses may change state without affecting device operation. In order for the output to be read S1, S2 and E must
be low, W must be high. When E goes high, the output data is latched into an on chip register. Taking either or both S1 or S2 high, forces the output buffer to a high impedance state. The output data may be re-enabled at any time by taking S1 and S2 low. On the falling edge of E the data will be unlatched.
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HM-6518 Timing Wavforms (Continued)
(8) TAVEL A TEHEL (7) E TWLEH (13) TELWH (15) TWLWH (16) W TDVWH (10) D HIGH Z TSLWH (14) S1, S2 TIME REFERENCE TWLSH (12) VALID DATA TWHDX (11) (9) TELAX VALID TELEL (17) TELEH (6) TEHEL (7) (8) TAVEL NEXT
Q
-1
0
1 FIGURE 2. WRITE CYCLE TRUTH TABLE
2
3
4
5
INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L X X X E H S1 X X L W X X L L X X X A X V X X X X V D X X V V X X X
OUTPUTS Q Z Z Z Z Z Z Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Write Mode has Begun Data is Written Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The write cycle is initiated by the falling edge of E which latches the address information into the on chip registers. The write portion of the cycle is defined as E, W, S1 and S2 being low simultaneously. W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is met. The write portion of the cycle is terminated by the first rising edge of either E, W, S1 or S2. Data setup and hold times must be referenced to the terminating signal. If a series of consecutive write cycles are to be performed, the W line may remain low until all desired locations have been written. When this method is used, data setup and hold times must be referenced to the rising edge of E.
By positioning the W pulse at different times within the E low time (TELEH), various types of write cycles may be performed. If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TSLQX), a combination read write cycle is executed. Data may be modified an indefinite number of times during any write cycle (TELEH). The data input and data output pins may be tied together for use with a common I/O data bus structure. When using the RAM in this method, allow a minimum of one output disable time (TWLQZ) after W goes low before applying input data to the bus. This will ensure that the output buffers are not active.
6-6
HM-6518 Test Load Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance includes stray and jig capacitance.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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