View FN2968_984498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

82C284/883
March 1997
Clock Generator and Ready Interface for 80C286 Processors
Description
The Intersil 82C284/883 is a clock generator/driver which provides clock signals for 80C286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with hysteresis.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Generates System Clock for 80C286 Processors * Generates System Reset Output from Schmitt Trigger Input - Improved Hysteresis * Uses Crystal or External Signal for Frequency Source - Dynamically Switchable Between Two Input Frequencies * Provides Local READY and MULTIBUSTM READY Synchronization * Static CMOS Technology * Single +5V Power Supply * Available in 18 Lead CERDIP Package
Ordering Information
PART NUMBER MD82C284-12/883 TEMP. RANGE PACKAGE PKG. NO. F18.3 -55oC to +125oC CERDIP
Pinout
82C284/883 (CERDIP) TOP VIEW
ARDY SRDY SRDYEN READY EFI F/C X1 X2 GND 1 2 3 4 5 6 7 8 9 18 VCC 17 ARDYEN 16 S1 15 S0 14 NC 13 PCLK 12 RESET 11 RES 10 CLK
Functional Diagram
RESET RES SYNCHRONIZER X1 X2
RESET
XTAL OSC MUX CLK
EFI F/C ARDYEN ARDY
SYNCHRONIZER
SRDYEN SRDY
READY LOGIC
READY
S1 S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 MULTIBUSTM is a Trademark of Intel Corporation.
File Number
2968.1
1
82C284/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . GND -0.1V to VCC +1.0V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . 80 20 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Gates Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V EFI Rise Time (From 0.8V to 3.2V) . . . . . . . . . . . . . . . . . . 8ns (Max) EFI Fall Time (From 3.2V to 0.8V). . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 82C284/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. PARAMETER Input LOW Voltage Input HIGH Voltage EFI, F/C Input High Voltage RES HIGH Voltage RES Input Hysteresis RESET, PCLK Output LOW Voltage RESET, PCLK Output Voltage READY Output LOW Voltage CLK Output LOW Voltage CLK Output HIGH Voltage Input Leakage Current Active Power Supply Current NOTES: 1. ICCOP measured at 10MHz for the 82C284-10/883 and at 12.5MHz for the 82C284-12/883. VIN = GND or VCC, VCC = 5.5V, outputs unloaded. 2. Interchanging of force and sense conditions is permitted. TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet waveforms, unless otherwise specified. (NOTE 1) CONDITIONS At VCC/2, Note 8 At VCC/2, Note 8 GROUP A SUBGROUP 9, 10, 11 9, 10, 11 10MHz TEMPERATURE -55oC TA +125oC -55oC TA +125oC MIN 20 20 MAX 12MHz MIN 16 20 MAX UNITS ns ns SYMBOL VIL VIH VIHC VIHR VHYS VOL VOH VOLR VOLC VOHC II ICCOP CONDITIONS VCC = 4.5V VCC = 5.5V VCC = 5.5V VCC = 5.5V VCC = 5.5V IOL = 5mA, VCC = 4.5V, Note 2 IOH = -1mA, VCC = 4.5V, Note 2 IOH = 10mA, VCC = 4.55V, Note 2 IOL = 5mA, VCC = 4.5V, Note 2 IOH = -5mA, VCC = 4.5V, Note 2 VIN = GND or VCC, VCC = 5.5V 82C284-10/883, Note 1 82C284-12/883, Note 1 GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.2 3.2 VCC -0.8 0.5 VCC -0.4 VCC -0.4 -10 MAX 0.8 0.4 0.4 0.4 10 48 60 UNITS V V V V V V V V V V A mA mA
PARAMETER EFI LOW Time EFI HIGH Time
SYMBOL t1 t2
2
82C284/883
TABLE 2. 82C284/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested. A.C. timings are referenced to 0.8V and 2.0V points of the signals as illustrated in datasheet waveforms, unless otherwise specified. (Continued) (NOTE 1) CONDITIONS GROUP A SUBGROUP 9, 10, 11 10MHz TEMPERATURE -55oC TA +125oC MIN 20 MAX 12MHz MIN 18 MAX UNITS ns
PARAMETER Status Setup Time for Status Going Active Status Setup Time for Going Inactive Status Hold Time F/C Setup Time F/C Hold Time SRDY or SRDYEN Setup Time SRDY or SRDYEN Hold Time ARDY or ARDYEN Setup Time ARDY or ARDYEN Hold Time RES Setup Time RES Hold Time CLK Period CLK LOW Period CLK HIGH Time READY Inactive Delay READY Active Delay PCLK Delay RESET Delay PCLK LOW Time PCLK HIGH Time NOTES:
SYMBOL t5A
t5B t6 t7 t8 t9 t10 t11 t12 t13 t14 t16 t17 t18 t21 t22 t23 t24 t25 t26 Notes 2, 6 Notes 2, 6 At 0.8V, Note 4, Test Condition 2 At 0.8V, Note 4 CL = 75pF, Test Condition 1 CL = 75pF, Test Condition 3 CL = 75pF, Note 5 CL = 75pF, Note 5 Note 3 Note 3 Notes 3, 7 Notes 3, 7
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA -55oC TA -55oC TA -55oC TA -55oC TA +125oC +125oC +125oC +125oC +125oC
20 1 15 15 15 2 5 30 20 10 50 12 16 5 t1610 t1610
24 20 27 -
16 1 15 15 15 2 5 25 18 8 40 11 13 5 t1610 t1610
18 16 26 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
1. VCC = 4.5V and 5.5V unless otherwise specified. CLK loading: CL = 100pF. 2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2. The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to GND, and 15pF from pin X2 to GND; for CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND, and 15pF from X2 to GND. These recommended values are 5pF and include all stray capacitance. Decouple VCC and GND as close to the 80C284/883 as possible. 3. This is an asychronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge. 4. The pull-up resistor value for the READY pin is 620 with the rated 150pF load. 5. t16 refers to any allowable CLK period. 6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 requirements. 7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES active, and to 4.2V on the RES waveform for RES inactive. 8. Input test waveform characteristics: VIL= 0.0V, VIH = 4.5V.
3
82C284/883
TABLE 3. 82C284/883 ELECTRICAL PERFORMANCE SPECIFICATIONS 10MHz PARAMETER Input Capacitance SYMBOL CIN CONDITIONS FREQ = 1MHz, All measurements are referenced to device GND NOTES 1 TEMPERATURE TA = +25oC MIN MAX 10 12MHz MIN MAX 10 UNITS pF
EFI HIGH to CLK LOW Delay EFI LOW to CLK HIGH Delay CLK Rise Time
t15A
1, 2
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
-
30
-
25
ns
t15B
1, 3
-
35
-
30
ns
t19
1.0V to 3.6V, CL = 100pF 3.6V to 1.0V, CL = 100pF
1
-
8
-
8
ns
CLK Fall Time
t20
1
-
8
-
8
ns
X1 HIGH to CLK NOTES:
t27
1, 4
-
35
-
30
ns
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 2. Measured from 3.2V on the EFI waveform to 1.0V on the CLK. 3. Measured from 0.8V on the EFI waveform to 3.6V on the CLK. 4. Measured from 3.6V on the X1 input to 3.6V on the CLK. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
A.C. Test Conditions
TEST CONDITION
VCC
RL 750 620
CL 75pF 150pF 75pF
1 2
RL
DEVICE OUTPUT CL
3
4
82C284/883 A.C. Specifications
3.2V EFI INPUT 0.8V tDELAY (MAX) VCC - 0.4V CLK OUTPUT tSETUP tHOLD 3.2V 3.2V F/C INPUT 0.8V 0.8V 0.4V 3.8V 3.6V 1.0V 3.6V 1.0V 0.4V 3.8V 0.4V
VCC - 0.8V RES INPUT 0.8V 0.8V
VCC - 0.4V 0.4V
2.6V OTHER DEVICE INPUT 2.0V 0.8V tDELAY (MAX) tDELAY (MIN) DEVICE OUTPUT 2.0V 0.8V 2.0V 0.8V
0.4V
FIGURE 1. A.C. DRIVE, SETUP, HOLD AND DELAY TIME MEASUREMENT POINTS
Timing Waveforms
t1 EFI t19 CLK t17 t20 t15B t18 t2 t16
t15A
FIGURE 2. CLK AS A FUNCTION OF EFI NOTE: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown.
t16 CLK t13 RES t24 RESET DEPENDS ON
STATE OF PREVIOUS RES
t14
(SEE NOTE) t13
t14
t24
t22 READY
t21
NOTE:
This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
FIGURE 3. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN AND SRDY + SRDYEN HIGH
5
82C284/883 Timing Waveforms
(Continued)
1 CLK t6 S1 * S0 t5A PCLK
TS
2
1
TC
2
t5B t6 t23
IF THIS IS CYCLE
t23 t26 t25 t9 t10
UNDEFINED FIRST BUS
SRDY + SRDYEN t11 ARDY + ARDYEN t21 READY NOTE 2
NOTE 1 t12 t11 t12
t21
t22
NOTES: 1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown. 2. If SRDY + SRDYEN or ARDY + ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted until the falling edge of 2 of TS. FIGURE 4. READY AND PCLK TIMING WITH RES HIGH
1 CLK
2
1
2
1
2
PCLK t7 F/C t8 t27 X1
CLK 1 PCLK t7 t8 EFI t15B 2 1 2 1 2
F/C
FIGURE 5. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAMIC FREQUENCY SWITCHING NOTE: This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
6
82C284/883 Burn-In Circuit
18 LEAD CERDIP
R1 F7 F5 F6 VCC/2 F1 F12 R1 F0 R1 VCC/2 GND C1 VCC 8 9 11 R1 10 VCC/2 7 12 R1 F11 R1 R1 R1 R1 R1 1 2 3 4 5 6 18 17 R1 16 R1 15 R1 14 R1 13 R1 VCC/2 VCC/2 NC F10 F9 R1 VCC F8
NOTES: 1. Supply Voltage: VCC = 5.5V, 0.5V, GND = 0V. Driver Voltage: VIH = 4.5V 10%, VIL = 0V 2. Input Voltage Limits: VIL (Max) = 0.4V, VIH (Min) = 2.6V 3. Component Values: R1 = 47k, C1 = 0.1F (Min) 4. Oven type and frequency requirements microtest, F0 through F12. 5. Approximate current per unit. ICC = 0.3mA. 6. Special requirements: (a) Electrostatic Discharge Sensitive. Proper precautions must be used when handling units. (b) All power supplies must be at zero volts when the boards are inserted into the ovens. After insertion, apply VCC first, then activate the driver power supplies. 7. Oscilloscope measurements: To be on loaded boards before insertion into the oven.
7
82C284/883 Die Characteristics
DIE DIMENSIONS: 63 mils x 69 mils x 19 mils 1 mil METALLIZATION: Type: Silicon - Aluminum Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 2 x 105 A/cm2
Metallization Mask Layout
82C284/883
SRDY
ARDY
VCC
ARDYEN
S1 SRDYEN S0
READY NC EFI
F/C
PCLK
X1
RESET
X2
GND
CLK
RES
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
8

▲Up To Search▲

Price & Availability of FN2968

	To Download FN2968 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .