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| 06/20/00 Errata: CS43L42 Rev. D CS43L42 Low Voltage, Stereo DAC with Headphone Amp All references to the CS43L42 mentioned below shall be taken to refer to revision D of the CS43L42 product. The hardware revision code can be found in the 10-character field printed below the part number on each chip. The letter which appears as the fifth character from the right is the revision code (e.g. ZNACSD9926 is a Revision D part). * The PopGuard(c) Transient Control does not function properly and will produce audible artifacts on the headphone and line outputs during power-up. A hardware fix is available for this issue. Please see Figures 1 and 2 for the headphone output fix. For the line outputs, please use the optional mute circuit shown in the CDB43L42 schematic to mask this problem. The PopGuard(c) Transient Control power-down ramp requires 5 seconds to prevent audible artifacts on the headphone outputs at the next power-up. A hardware fix is available for this issue, see Figures 1 and 2 for details. This fix will reduce the ramp down time to approximately 300 milliseconds. The headphone outputs clip when the value of VA_HP is below VA. It is recommended that these two supplies be tied together. The Peak Signal Limiter is not functional. When the Analog Headphone Attenuation Control registers (02h and 03h) are set for attenuation levels greater than -10 dB, the actual attenuation deviates from the register setting by more than 1 dB. * * * * Cirrus Logic P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com JUN `00 ER481A2 1 The Motorola MOSFETs shown have been tested to work properly, however, an equivalent device may be used. MGSF1NH02ELT 2 2 0uF 4 7 uH F r o m C S 4 3 L 4 2 P i n 10 (HP_A) Headphones 120 to 150 Ramp_Down_A 16 MGSF1NH02ELT 2 2 0uF 4 7 uH F r o m C S 4 3 L 4 2 P i n 14 (HP_B) 120 to 150 Ramp_Down_B 16 Mute Control from uC or DSP 100K Ramp_Down_A 47k / R S T _ f r o m _ C S43L42 1 2 39k 1.0uF 180 180 3 1 Ramp_Down_B 2 2 S C 2 8 7 8 or 2SC3326 2 3 1 2 S C 2 8 7 8 or 2SC3326 See attached timing diagram for /RST and the Mute control. Customer will need to generate the mute control from their DSP or micro-controller. 2SC2878 is in TO-92 package 2SC3326 is in SOT-23 package The Toshiba transistors or equivalent will work best here. The device used must have a very low Ron (3 ohms or less). Figure 1. Pop Guard Fix 2 ER481A2 Headphone output at pin of part ~300 msec. /RST ~900 msec. Mute Control from DSP or uC Figure 2. Timing for Pop Guard Fix If there are any questions concerning this information, please contact Applications Engineering at 512-445-7222. ER481A2 3 |
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