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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11416-1E
MEMORY Mobile FCRAMTM
CMOS
16 Mbit (1 M word x 16 bit) MB82D01171B-60L/-60LL/-70L/-70LL
CMOS 1,048,576-WORD x 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface
Mobile Phone Application Specific Memory
s DESCRIPTION
The Fujitsu MB82D01171B is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This MB82D01171B is suited for mobile applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan.
s PRODUCT LINEUP
Parameter Access Time (tAA Max, tCE Max) Active Current (IDDA1 Max) Standby Current (IDDS1 Max) Power Down Current (IDDP Max) 100 A 70 A 10 A MB82D01171B 60L 60 ns 20 mA 100 A 70 A 60LL 70L 70 ns 70LL
s PACKAGES
48-ball plastic FBGA
(BGA-48P-M18)
MB82D01171B-60L/-60LL/-70L/-70LL
s FEATURES
* * * * * Asynchronous SRAM Interface 1 M word x 16 bit Organization Fast Random Access Time : tAA = tCE = 60 ns, 70 ns Low Power Consumption : IDDS1 = 100 A (L version) , 70 A (LL version) Wide Operating Conditions : VDD = +2.3 V to +2.7 V +2.7 V to +3.1 V +3.1 V to +3.5 V TA = -30 C to +85 C * Byte Write Control * 8 words Address Access Capability * Power Down Control by CE2
2
MB82D01171B-60L/-60LL/-70L/-70LL
s PIN ASSIGNMENTS
(TOP VIEW)
1 2 3 4 5 6
A B C D E F G H
LB DQ9
OE UB
A0 A3 A5 A17 NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE1 DQ2 DQ4 DQ5 DQ6 WE A11
CE2 DQ1 DQ3 VDD VSS DQ7 DQ8 NC
DQ10 DQ11 VSS VDD DQ12 DQ13
DQ15 DQ14 DQ16 A18 A19 A8
(BGA-48P-M18)
s PIN DESCRIPTION
Pin Name A19 to A0 CE1 CE2 WE OE LB UB DQ8 to DQ1 DQ16 to DQ9 VDD VSS NC Address Input Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Write Control (Low Active) Upper Byte Write Control (Low Active) Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Ground No Connection Description
3
MB82D01171B-60L/-60LL/-70L/-70LL
s BLOCK DIAGRAM
VDD VSS
A19 to A0
Address Latch & Buffer
Row Decoder
Memory Cell Array 16,777,216 bit
DQ8 to DQ1
I/O Buffer
DQ16 to DQ9
Input Data Latch & Control
Sense / Switch
Output Data Control
Column / Decoder
Address Latch & Buffer
CE2
Power Control Timing Control
CE1 WE LB UB OE
4
MB82D01171B-60L/-60LL/-70L/-70LL
s FUNCTION TRUTH TABLE
Mode Standby (Deselect) Output Disable*1 No Read Read*2 H Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down *3 L X X X L L H H L CE2 CE1 H WE X H OE X H LB X X H L *4 H L L X UB X X H L *4 L H L X A19 to A0 DQ8 to DQ1 DQ16 to DQ9 X *5 Valid Valid Valid Valid Valid X High-Z High-Z High-Z Output Valid Invalid Input Valid Input Valid High-Z High-Z High-Z High-Z Output Valid Input Valid Invalid Input Valid High-Z IDDP No IDDA Yes IDD IDDS Data Retention
Note : L = Logic Low, H = Logic High, X = either "L" or "H", High-Z = High Impedance *1 : Output Disable mode should not be kept longer than 1 s. *2 : Byte control at Read mode is not supported. *3 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. *4 : Either or both LB and UB must be Low for Read operation. *5 : Can be either VIL or VIH but must be valid before Read or Write.
5
MB82D01171B-60L/-60LL/-70L/-70LL
s ABSOLUTE MAXIMUM RATINGS
Parameter Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature Symbol VDD VIN VOUT IOUT TSTG Rating Min -0.5 -0.5 -0.5 -50 -55 Max +3.6 +3.6 +3.6 +50 +125 Unit V V V mA C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VDD (31) Supply Voltage *1 VDD (27) VDD (23) VSS VIH (31) High Level Input Voltage *1, *2 VIH (27) VIH (23) VIL (31) Low Level Input Voltage *1, *3 Ambient Temperature *1 : All voltages are referenced to VSS. *2 : Maximum DC voltage on input and I/O pins are VDD + 0.3 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for periods of up to 5 ns. *3 : Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. VIL (27) VIL (23) TA 2.2 2.0 -0.3 -0.3 -0.3 -30 Value Min 3.1 2.7 2.3 0 2.6 Max 3.5 3.1 2.7 0 VDD + 0.3 and 3.6 VDD + 0.3 VDD + 0.3 0.6 0.5 0.4 85 Unit V V V V V V V V V V C
6
MB82D01171B-60L/-60LL/-70L/-70LL
s PIN CAPACITANCE
(f = 1.0 MHz, TA = +25 C) Value Unit Typ Max 5 5 8 pF pF pF
Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance
Symbol CIN1 CIN2 CIO
Conditions VIN = 0 V VIN = 0 V VIO = 0 V
Min
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level VDD Power Down Current L Version LL Version L Version VDD Standby Current LL Version L Version LL Version L Version LL Version IDDS1 IDDS Symbol ILI ILO VOH(31) VOH(27) VOH(23) VOL IDDP Conditions VSS VIN VDD 0 V VOUT VDD, Output Disable VDD = VDD(31), IOH = -0.5 mA VDD = VDD(27), IOH = -0.5 mA VDD = VDD(23), IOH = -0.5 mA IOL = 1 mA VDD = VDD Max, VIN = VIH or VIL, CE2 0.2 V VDD = VDD(31) Max, VIN = VDD - 0.5 V or VIL, CE1 = CE2 = VIH VDD = VDD(27, 23) Max, VIN = VDD - 0.5 V or VIL, CE1 = CE2 = VIH VDD = VDD(31) Max, VIN 0.2 V or VIN VDD - 0.2 V, CE1 = CE2 VDD - 0.2 V VDD = VDD(27, 23) Max, VIN 0.2 V or VIN VDD - 0.2 V, CE1 = CE2 VDD - 0.2 V VDD = VDD Max, VIN = VDD - 0.5 V or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA VDD = VDD Max, VIN = VDD - 0.5 V or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min Value Min -1.0 -1.0 2.5 2.2 1.8 Max +1.0 +1.0 0.4 10 2.0 1.5 1.0 0.5 150 100 100 70 mA mA Unit A A V V V V A
A
A
IDDA1 VDD Active Current IDDA2
20
mA
tRC / tWC = 1 s
3.0
mA
Notes: * All voltages are referenced to Vss. * DC Characteristics are measured after following POWER-UP timing. * IOUT depends on the output load conditions. 7
MB82D01171B-60L/-60LL/-70L/-70LL
s AC CHARACTERISTICS
(1) Read Operation Parameter Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low LB/UB Setup Time to CE1 Low LB/UB Setup Time to OE Low Address Invalid Time Address Hold Time from CE1Low Address Hold Time from OE Low Address Hold Time from CE1 High Address Hold Time from OE High LB/UB Hold Time from CE1 High LB/UB Hold Time from OE High CE1 Low to OE Low Delay Time OE Low to CE1 High Delay Time CE1 High Pulse Width OE High Pulse Width *1 : The output load is 50 pF + 1TTL. *2 : The output load is 5 pF. *3 : The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4 : Applicable only to A2, A1 and A0 when both CE1 and OE are kept at Low for the address access. *5 : Applicable if OE is brought to Low before CE1 goes Low. *6 : The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1 stays Low) , the tOE become tOE (Max) + tASO (Min) - tASO (actual) . *7 : The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8 : The tAX is applicable when all or two addresses among A2 to A0 are switched from previous state. *9 : If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . *10 : Maximum value is applicable if CE1 is kept at Low. 8 Symbol tRC tCE tOE tAA tOH tCLZ tOLZ tCHZ tOHZ tASC tASO tASO[ABS] tBSC tBSO tAX tCLAH tOLAH tCHAH tOHAH tCHBH tOHBH tCLOL tOLCH tCP tOP tOP[ABS] -60L/-60LL Min Max 80 60 35 60 5 5 0 20 20 -5 25 5 -5 0 5 80 45 -5 -5 -5 -5 25 1000 45 10 25 1000 10 -70L/-70LL Min Max 90 70 40 70 5 5 0 25 25 -5 30 5 -5 0 5 90 50 -5 -5 -5 -5 30 1000 50 12 30 1000 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes
*1, *3 *1 *1, *4 *1 *2 *2 *2 *2 *5 *3, *6 *7 *5 *4, *8 *4 *4, *9
*3, *6, *9, *10 *9 *6, *9, *10 *7
MB82D01171B-60L/-60LL/-70L/-70LL
(2) Write Operation -60L/-60LL Parameter Write Cycle Time Address Setup Time Address Hold Time CE1 Write Setup Time CE1 Write Hold Time WE Setup Time WE Hold Time LB and UB Setup Time LB and UB Hold Time OE Setup Time OE Hold Time OE High to CE1 Low Setup Time Address Hold Time from OE High CE1 Write Pulse Width WE Write Pulse Width CE1 Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1 High Pulse Width Symbol Min tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP 80 0 35 0 0 0 0 -5 -5 0 25 12 -5 -5 45 45 20 20 15 0 10 Max 1000 1000 1000 1000 1000 Min 90 0 40 0 0 0 0 -5 -5 0 35 15 -5 -5 50 50 20 20 20 0 12 Max 1000 1000 1000 1000 1000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *10 *3 *3, *4 *5 *6 *7 *1, *8 *1, *8, *9 *1, *10 *1, *3, *10 *1 *2, *9 *2 *9 -70L/-70LL Unit Notes
*1 : Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2 : New write address is valid from either CE1 or WE is brought to High. *3 : Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High. *4 : The tOEH is specified from end of tWC (Min). The tOEH (Min) is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *5 : The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6 : tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7 : Applicable if CE1 stays Low after read operation. *8 : tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively. , *9 : If write operation is terminated by WE followed by CE1 = High, the sum of actual tCS and tWP and the sum of actual tAS and tWP must be equal or greater than 60 ns. For example, if actual tWP is 45 ns, tCS and tAS must be equal or greater than 15 ns. *10 : tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively. In case CE1 is brought to High before satisfaction of tWR (Min) , the tWRC (Min) is also applied. 9
MB82D01171B-60L/-60LL/-70L/-70LL
(3) Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit CE1 High Setup Time following CE2 High after Power Down Exit (4) Other Timing Parameters Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE2 High Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up CE1 and CE2 High Hold Time during Power-up Input Transition Time Symbol tCHOX tCHWX tC2LH tC2HL tCHH tCHHP tT -60L/-60LL Min 10 10 50 50 350 400 1 Max 25 -70L/-70LL Min 10 10 50 50 350 400 1 Max 25 Unit ns ns s s s s ns *4 *1 *2 *3 *2 Note Symbol tCSP tC2LP tCHH tCHS -60L/-60LL Min 10 80 350 10 Max -70L/-70LL Min 10 90 350 10 Max Unit ns ns s ns Note
*1: It may write some data into any address location if tCHWX (Min) is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, each AC specification must be relaxed accordingly. (5) AC Test Conditions Parameter Input High Level Input Low level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Conditions Between VIL and VIH Measured Value VDD - 0.4 0.4 1.3 5 Unit V V V ns Note
10
MB82D01171B-60L/-60LL/-70L/-70LL
s TIMING DIAGRAM
1. READ Timing #1 (OE Control Access)
tRC tRC Address Valid tASO tOHAH tOHAH
Address
Address Valid tCE
CE1
tOLCH tCLOL tOE tOP tOE
OE
tASO tBSO tOHBH tBSO tOHBH
LB, UB
tOHZ tOLZ tOH tOLZ tOHZ tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2 and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low.
11
MB82D01171B-60L/-60LL/-70L/-70LL
2. READ Timing #2 (CE1 Control Access)
tRC tRC Address Valid tCHAH tASC tCE tCHAH
Address
tASC
Address Valid tCE
CE1
tCP
OE
tCHBH tBSC tBSC tCHBH
LB, UB
tCHZ tCLZ tOH tCLZ
tCHZ tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2 and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low.
12
MB82D01171B-60L/-60LL/-70L/-70LL
3. READ Timing #3 (Address Access after OE Control Access)
tRC tRC Address Valid (No change)
Address (A19-A3)
Address Valid
Address (A2-A0)
tASO
Address Valid tOLAH tAX
Address Valid tAA tOHAH
CE1
tOE tOHZ
OE
tBSO tOHBH
LB, UB
tOLZ
tOH
tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2 and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low.
13
MB82D01171B-60L/-60LL/-70L/-70LL
4. READ Timing #4 (Address Access after CE1 Control Access)
tRC tRC Address Valid (No change)
Address (A19-A3)
Address Valid
Address (A2-A0)
tASC
Address Valid tCLAH tAX
Address Valid tAA tCHAH
CE1
tCE tCHZ
OE
tBSO tCHBH
LB, UB
tCLZ tOH tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2 and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low.
14
MB82D01171B-60L/-60LL/-70L/-70LL
5. WRITE Timing #1 (CE1 Control)
tWC
Address
tAS
Address Valid tAH tAS
CE1
tCW tWS tWH tWRC tWS
WE
tBS
tBH
tBS
UB, LB
tOHCL
OE
tDS tDH
DQ (Input)
Valid Data Input
Note : CE2 must be High for write cycle.
15
MB82D01171B-60L/-60LL/-70L/-70LL
6. WRITE Timing #2-1 (WE Control, Single Write Operation)
tWC
Address
tOHAH tAS
Address Valid tAH tCH tAS
CE1
tWRC, tCP tOHCL tCS tWP tWR
WE
tBH tBS
tBH
UB, LB
tOES
OE
tOHZ tDS tDH
DQ (Input)
Valid Data Input
Note : CE2 must be High for write cycle.
16
MB82D01171B-60L/-60LL/-70L/-70LL
7. WRITE Timing #2-2 (WE Control, Continuous Write Operation)
tWC Address Valid tOHAH tAS tAH tAS
Address
CE1
tOHCL tCS tWP tWR
WE
tOHBH tBS tBH tBS
UB, LB
tOES
OE
tOHZ tDS tDH
DQ (Input)
Valid Data Input
Note : CE2 must be High for write cycle.
17
MB82D01171B-60L/-60LL/-70L/-70LL
8. READ/WRITE Timing #1-1 (CE1 Control)
tWC
Address
tCHAH tAS
Write Address tAH tASC
Read Address
CE1
tCP tWH tWS tCW tWH tWRC tWS tCLOL
WE
tCHBH tBS tBH tBSO
UB, LB
tOHCL
OE
tCHZ tOH tDS tDH tOLZ
DQ
Read Data Output Write Data Input
Note : Write address is valid from either CE1 or WE of last falling edge.
18
MB82D01171B-60L/-60LL/-70L/-70LL
9. READ/WRITE Timing #1-2 (CE1 Control)
tRC
Address
tASC tWRC
Read Address tCHAH tAS
Write Address
CE1
tWRC (Min) tWH tWS tCE tWH tCP tWS
WE
tBH tBSC tCHBH tBS
UB, LB
tOEH tOHCL
OE
tCHZ tDH tCLZ tOH
DQ
Write Data Input Read Data Output
Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) .
19
MB82D01171B-60L/-60LL/-70L/-70LL
10. READ (OE Control) /WRITE (WE Control) Timing #2-1
tWC Write Address tOHAH tAS tAH tASO Read Address
Address
CE1
Low tWP tWR tOEH
WE
tOHBH tBS tBH tBSO
UB, LB
tOES
OE
tOHZ tOH tDS tDH tOLZ
DQ
Read Data Output Write Data Input
Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE.
20
MB82D01171B-60L/-60LL/-70L/-70LL
11. READ (OE Control) /WRITE (WE Control) Timing #2-2
tRC
Address
tASO
Read Address Valid tOHAH tAS
Write Address
CE1
Low tWR tOEH
WE
tBH tBSO tOHBH tBS
UB, LB
tOE tOES
OE
tOHZ tDH tOLZ tOH
DQ
Write Data Input Read Data Output
Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE.
21
MB82D01171B-60L/-60LL/-70L/-70LL
12. Standby Entry Timing after Read or Write
CE1
tCHOX tCHWX
OE
WE
Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A2, A1, and A0, or CE1 Low to High transition.
13. POWER DOWN Entry and Exit Timing
CE1
tCHS
CE2
tCSP tC2LP High-Z tCHH
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used for Power-up #2 below.
14. POWER-UP Timing 1
CE1
tCHS tC2LH tCHH
CE2
VDD
0V
VDD Min
Note : The tC2LH specifies after VDD reaches specified minimum level.
22
MB82D01171B-60L/-60LL/-70L/-70LL
15. POWER-UP Timing 2
CE1
tCHS tC2HL tCSP tC2LP tCHH
CE2
tC2HL
VDD
0V
VDD Min
Note : The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition.
16. POWER-UP Timing 3
CE1 tCHHP CE2
VDD
0V
VDD Min
Note : Both CE1 and CE2 must be High together with VDD. Otherwise either POWER-UP Timing #1 or #2 must be used for proper operation.
23
MB82D01171B-60L/-60LL/-70L/-70LL
s DATA RETENTION
1. Low VDD Characteristics
Parameter VDD Data Retention Supply Voltage VDD Data Retention Supply Current L Version LL Version IDR1 Symbol VDR Test Conditions CE1 = CE2 VDD - 0.2 V or CE1 = CE2 = VIH VDD = VDD (23) , VIN 0.2 V or VIN VDD - 0.2 V, CE1 = CE2 VDD - 0.2 V, IOUT = 0 mA VDD = VDD at data retention entry VDD = VDD after data retention Value Min 2.3 0 100 0.2 Max 3.5 100 70 Unit V A
Data Retention Setup Time Data Retention Recovery Time VDD Voltage Transition Time
tDRS tDRR V/t
ns ns V/s
2. Data Retention Timing
tDRS tDRR
3.5 V
VDD V/t V/t
2.7 V
CE2
2.3 V
CE1 VIH VDD - 0.2 V
0.4 V VSS
Data Retention Mode Data bus must be in High-Z at data retention entry.
24
MB82D01171B-60L/-60LL/-70L/-70LL
s ORDERING INFORMATION
Part Number MB82D01171B-60LPBN MB82D01171B-60LLPBN MB82D01171B-70LPBN MB82D01171B-70LLPBN Package 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) Remarks tCE = 60 ns Max, IDDS1 = 100 A Max tCE = 60 ns Max, IDDS1 = 70 A Max tCE = 70 ns Max, IDDS1 = 100 A Max tCE = 70 ns Max, IDDS1 = 70 A Max
25
MB82D01171B-60L/-60LL/-70L/-70LL
s PACKAGE DIMENSION
48-ball plastic FBGA (BGA-48P-M18)
1.05 -0.10 9.000.10(.354.004) .041 -.004
+0.15 +.006
(Mounting height) (5.25(.207)) 0.75(.030) TYP
0.250.10 (.010.004) (Stand off)
6 5 6.000.10 (.236.004) (3.75(.148)) 4 3 2 1 0.75(.030) TYP INDEX AREA
H
GFE
DC
BA
INDEX MARK 0.08(.003)
M
48-o0.350.10 (48-o.014.004) 0.20(.008) S S
0.10(.004) S
C
2001 FUJITSU LIMITED B48018S-c-1-1
Dimensions in mm (inches)
26
MB82D01171B-60L/-60LL/-70L/-70LL
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0303 (c) FUJITSU LIMITED Printed in Japan

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