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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CW11 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0, INTRTC), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CW11 Low Voltage/Low Power CMOS 16-Bit Microcontrollers TMP91CW11F 1. Outline and Features TMP91CW11 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91CW11 is housed in a 100-pin flat package (P-LQFP100-1414-0.50C). Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear ADdress space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (640 ns/ 2 bytes at 25 MHz) (800 ns/ 2 bytes at 20 MHz) (1.28 ns/ 2 bytes at 12.5 MHz) (2) Minimum instruction execution time: 160 ns (at 25 MHz, VCC 200 ns (at 20 MHz, VCC 320 ns (at 12.5 MHz, VCC (3) Internal RAM: 4 Kbytes ROM: 128 Kbytes (4) External memory expansion Expandable up to 16 Mbytes (for both programs and data) Can simulatneously support 8-/16-bit width external data bus ... Dynamic data bus sizing 5 V without external bus) 5 V) 3 V) 000707EBP1 For ADiscussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be mADe at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trADe laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 91CW11-1 2003-03-31 TMP91CW11 (5) 8-bit timer: 2 channels (6) 8-bit PWM timer: 2 channels (7) 16-bit timer: 2 channels (8) General-purpose serial interface: 6 channels for UART/8-bit SIO: 2channels for UART: 1 channel for 8-bit SIO: 2 channels for I2C bus (multi-master)/8-bit SIO: 1 channel (9) 10-bit AD converter: 8 channels (10) Watchdog timer (11) Chip select/wait controller: 3 blocks (12) Interrupts: 39 interrupts 9 CPU interrupts: Sofware interrupt instruction and illegal instruction 24 internal interrupts: 6 external interrupts: (13) Input/output ports 79 pins Large current output: 6 pors, LED direct drive (14) Standby mode 4 HALT modes: RUN, IDLE2, IDLE1, STOP (15) Clock gear function High-frequency clock can be changed from fc to fc/16. Dual clock Operation (16) Real Time Counter (17) Operating voltage VCC 2.7 to 5.5 V 7-level priority can be set. (18) Package: P-LQFP100-1414-0.50C 91CW11-2 2003-03-31 TMP91CW11 ADTRG (P53) AN0 to AN7 (P50 to P57) AVCC AVSS VREFL VREFH CPU (TLCS-900L1) 10-Bit 8CH AD Converter XWA XBC XDE XHL XIX XIY XIZ XSP W B D H IX IY IZ SP 32 bits Serial I/ O (CH.1) SR PC Serial I/O (CH. 2) Port 3 Serial I/O (CH. 3) 4-KB RAM F A C E L VCC [3] VSS [3] OSC1 Clock Gear OSC2 XT1 (P96) XT2 (P97) CLK ALE EA AM8/16 RESET X1 X2 SO0 (P93) SI0 (P94) SCK0 (P95) SO1 (P42) SI1 (P41) SCK1 (P40) TXD2 (P60) RXD2 (P61) SCK2 (P62) TXD3 (P63) RXD3 (P64) SCK3 (P65) Serial I/ O (CH.0) RD (P30) WR (P31) HWR (P32) WAIT (P33) BUSRQ (P34) BUSAK (P35) R / W (P36) P37 TXD4 (P66) RXD4 (P67) Serial I/O (CH. 4) Port 0 Port 1 Port 2 AD0 to AD7 (P00 to P07) AD8/A8 to AD15/A15 (P10 to P17) A0/A16 to A7/A23 (P20 to P27) SDA/SO5 (P90) SCL/SI5 (91) SCK5 (P92) TI0 (P70) Serial Bus Interface Controller 8-Bit Timer (Timer 0) 8-Bit Timer (Timer 1) Port A PA0 to PA6 SCOUT (PA7) TO1 (P71) TO2(P72) 8-Bit Timer (Timer 2) 8-Bit Timer (Timer 3) 128-KB ROM Watchdog Timer TO3 (P73)) WDTOUT INT4/TI4 (P80) INT5/TI5 (P81) TO4 (P82) TO5 (P83) INT6/TI6 (P84) INT7/TI7 (P85) TO6 (P86) 16-Bit Timer (Timer 4) Real Time Counter Interrupt Controller NMI INT0 (P87) 16-Bit Timer (Timer 5) CS/WAIT Controller (3 blocks) CS0 (P40) CS1(P41) CS2 (P42) Figure 1.1 TMP91CW11 block diagram 91CW11-3 2003-03-31 TMP91CW11 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91CW11F, their names and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of TMP91CW11F. Programmable Pull Up Pull Down Pin No. Programmable TMP91CW11 TMP91CW11 P66/TXD4 P67/RXD4 VSS P50/AN0 P51/AN1 P52/AN2 Pin No. Pull Down Pull Up 88 P65/CTS3/SLCK3 87 P64/RXD3 86 P63/TXD3 85 P62/CTS2/SLCK2 84 P61/RXD2 83 P60/TXD2 82 P42/CS2/SO1 81 P41/CS1//SI1 80 P40/CS0/SCK1 79 P37 78 P36/R/W 77 P35/BUSAK 76 P34/BUSRQ 75 P33/WAIT 74 P32/HWR 73 P31/WR 72 P30/RD 71 P27/A7/A23 70 P26/A6/A22 69 P25/A5/A21 68 P24/A4/A20 67 P23/A3/A19 66 P22/A2/A18 65 P21/A1/A17 89 90 91 92 93 94 SIO P53/AN3/ADTRG 95 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC NMI P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 96 97 98 99 100 ADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Timer P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/SDA/SO5 P91/SCL/SI5 P92/SCK5 P93/SO0 P94/SI0 P95/SCK0 AM8/16 CLK VCC VSS X1 Top View LQFP100 64 P20/A0/A16 63 VCC 62 VSS 61 WDTOUT 60 P17/AD15/A15 59 P16/AD14/A14 58 P15/AD13/A13 57 P14/AD12/A12 56 P13/AD11/A11 55 P12/AD10/A10 54 P11/AD9/A9 53 P10/AD8/A8 52 P07/AD7 51 P06/AD6 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3 SIO Clock mode X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2 Figure 2.1.1 Pin assignment 91CW11-4 2003-03-31 Memory Interface TMP91CW11 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/4) Pin name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of pins 8 8 I/O I/O Tri-state I/O Tri-state Output I/O Output Output Function Port 0: I/O port that allows selection of I/O on a bit basis Address/data (lower): Bits 0 to 7 of address/data bus Port 1: I/O port that allows selection of I/O on a bit basis Address data (upper): Bits 8 to 15 of address/data bus Address: 8 to 15 of address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to 7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to 15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port34: I/O port(with pull-up resistor) Bus request: Signal used to request high impedance for AD0 to 15, A0 to 23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins. (For external DMAC) Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 to 15, A0 to 23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle; 0, write cycle. Port 37: I/O port (with pull-up resistor) Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Serial clock I/O 1 8 1 1 1 1 1 Output Output Output Output I/O Output I/O Input I/O Input P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK 1 I/O Output P36 R/W 1 1 1 I/O Output I/O I/O Output I/O P37 P40 CS0 SCK1 Note: This device's built-in memory or built-in I/O cannot be accessed with the external DMA controller, using the BUSRQ and BUSAK signals. 91CW11-5 2003-03-31 TMP91CW11 Table 2.2.2 Pin names and functions (2/4) Pin name P41 CS1 Number of pins 1 I/O I/O Output Input I/O Output Output Input Input Input Input Input Input Input Input Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output Function Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Serial receive data 1 Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Serial send data 1 Port5: Input port Analog input: Analog signal input for AD converter Port 53: Input Port Analog input = Analog signal input for AD converter AD external trigger Port 5: Input Port Analog input: Analog signal input for AD converter Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Port 60: I/O port (Programmable open drain) Serial send data 2 Port 61: I/O port Serial receive data 2 Port 62: I/O port serial data send enable 2 (Clear To Send) Serial Clock I/O 2 Port 63: I/O port Serial send data 3 Port 64: I/O port Serial receive data 3 Port 65: I/O port Serial data send enable 3 (Clear To Send) Serial Clock I/O 3 Port 66: I/O port Serial send data 4 Port 67: I/O port Serial receive data 4 Port 70: I/O port Timer input 0: timer 0 input Port 71: I/O port Timer output 1: Timer 0 or 1 output Port 72: I/O port PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port PWM output 3: 8-bit PWM timer 3 output SI1 P42 CS2 1 SO1 P50 to P52 AN0 to AN2 P53 AN3 ADTRG 3 1 P54 to P57 AN4 to AN7 VREFH VREFL P60 TXD2 P61 RXD2 P62 CTS2 4 1 1 1 1 1 SCLK2 P63 TXD3 P64 RXD3 P65 CTS3 1 1 1 SCLK3 P66 TXD4 P67 RXD4 P70 TI0 P71 TO1 P72 TO2 P73 TO3 1 1 1 1 1 1 91CW11-6 2003-03-31 TMP91CW11 Table 2.2.3 Pin names and functions (3/4) Pin name P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 SDA SO5 P91 SCL SI5 P92 SCK5 P93 SO0 P94 SI0 P95 SCK0 PA0 to PA5 PA6 Number of pins 1 I/O I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Input I/O I/O Output I/O I/O Input I/O I/O I/O Output I/O Input I/O I/O I/O I/O Function Port 80: I/O port Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port Timer output4: Timer 4 output pin Port 83: I/O port Timer output 5: Timer 4 output pin Port 84: I/O port Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port Timer output 6: Timer 5 output pin Port 87: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (Programmable open-drain) SBI I2C bus mode channel data Serial send data 5 Port 91: I/O port (Programmable open-drain) SBI I2C bus mode clock Serial receive data 5 Port 92: I/O port Serial Clock I/O 5 Port 93: I/O port (Programmable open-drain) Serial send data 0 Port 94: I/O port Serial receive data 0 Port 95: I/O port Serial clock I/O 0 Port A0 to A5: I/O ports (large current output) Port A6: I/O port 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 91CW11-7 2003-03-31 TMP91CW11 Table 2.2.4 Pin names and functions (4/4) Pin name PA7 SCOUT WDTOUT Number of pins 1 I/O I/O Output Output Input Output Port A7: I/O port System Clock Output: Watchdog timer output pin Function Outputs system clock or 2 times oscillation clock for synchronizing to external circuit. 1 1 1 NMI Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs [System Clock 2] Clock. Pulled-up during reset. can be disabled for reducing noise. CLK EA 1 1 1 1 2 1 1 2 3 3 1 1 Input Input Output Input I/O Input I/O Output I/O Output /Input Fixed to 1. Fixed to 1. Address Latch Enable (Can be disabled for reducing noise.) Reset: Initializes LSI. (With pull-up resistor) High Frequency Oscillator connecting pin Low Frequency Oscillator connecting pin Port 96: I/O port (Open-Drain Output) Low Frequency Oscillator connecting pin Port 97: I/O port (Open-Drain Output) TEST1 Should be connected with TEST2 pin. Power supply pin (All VCC pins are connected to the power supply source.) GND pin (All Vss pins are connected to the GND (0 V).) Power supply pin for AD converter GND pin for AD converter (0 V) AM8/ 16 ALE RESET X1/X2 XT1 P96 XT2 P97 TEST1/TEST2 VCC VSS AVCC AVSS Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by software. 91CW11-8 2003-03-31 TMP91CW11 3. Operation The following describes block by block the functions and basic operation of TMP91CW11. Notes and restrictions for each block are outlined in 7, "Use Precautions and Restrictions" at the end of this manual. 3.1 CPU TMP91CW11 incorporates a high-performance 16-bit CPU (900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describes the unique functions of the CPU used in TMP91CW11; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91CW11 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level for at least 10 system clocks (ten states: 16 s at 20 MHz), resetting initializes the clock gear to fc/16. When the reset is accepted, the CPU sets as follows: Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC (7 to 0) PC (15 to 8) PC (23 to 16) data located at FFFF00H data located at FFFF01H data located at FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits 91CW11-9 2003-03-31 Omitted 45 times of X1 Omitted 220 times of X1 X1 CLK Sampling RESET Sampling A16 to 23 (P20 to 27 input mode) (P40 to 41 input mode) CS0 to 1 CS2 (P42 input mode) (P36 input mode) R/W ALE AD0 to 15 Address Address read RD (Starts read cycle of 0WAIT after reset releasee) Address Data output Address write Figure 3.1.1 TMP91CW11 Reset timing chart AD0 to 15 91CW11-10 WR HWR (P32 input mode) (input mode) P42 P20 to 27, P32 to 37, 40, 41 P50 to 57, A0 to A7 P60 to 67, 70 to 73 P80 to 87, 90 to 95 P96 to 97 Internal pull-up or pull-down High impedance (input mode) (input mode) (Output mode: pen drain output) Note: TMP91CW11 2003-03-31 TMP91CW11 3.2 Memory Map The TMP91CW11 uses an address space of 128 bytes as an internal I/O area, which is allocated to addresses 000000H to 00007FH. The CPU can access this internal I/O area with short instruction code using the direct addressing mode. Figure 3.2.1 shows the memory map and the access ranges corresponding to the CPU addressing modes. 000000H 000080H 000100H 001080H Internal I/O (128 bytes) 256-byte direct area (n) Internal RAM (4 Kbytes) 64-Kbyte area (nn) External memory 010000H FE0000H Internal ROM (128 Kbytes) 16-Mbyte area (r32) ( r32) (r32 ) (r32 r8/16) (r32 d8/16) (nnn) FFFF00H Vector Table (256 bytes) FFFFFFH ( Internal area) Note: After reset, the stack pointer XSP is set to 100H. Figure 3.2.1 Memory map 91CW11-11 2003-03-31 TMP91CW11 4. Electrical Characteristics X used in an expression shows a frequency of clock fFPH selected by SYSCR1 Power Supply voltage Input Voltage Output Voltage Output Current (per pin) 4.1 Absolute Maximum Ratings Symbol VCC VIN VOUT IOUT1 IOUT2 IOUT3 Pin Rating 0.5 to 6.5 0.5 to VCC 0.5 0.5 Unit V V V mA mA mA mA mA mA mW C C C P96, P97, PA0 to A5, P60, P91 to 93 (for open-drain) Only PA0 to A5 Except PA0 to A5 Total PA0 to A5 Total 0.5 to VCC 20 2 2 120 80 80 600 260 65 to 150 40 to 85 Output Current (total) IOUT1 IOUT2 IOUT3 Power Dissipation (Ta Soldering Temperature Storage Temperature Operating Temperature 85C) PD Tsolder TSTG Topr Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 91CW11-248 2003-03-31 TMP91CW11 4.2 DC Characteristics (1/2) (Vss Parameter Power Supply Voltage Avcc Vcc Avss Vss AD0 to 15 0 V, Ta Condition 40 to 85C) Min 4.5 5.5 2.7 0.8 0.6 V Symbol Typ. (note) Max Unit fc 4 to 25 MHz VCC fc Vcc 4 to 12.5 MHz 4.5 V fs 30 to 34 kHz VIL Vcc < 4.5 V Input Low Voltage P20 to 27, P32 to 37, P42, P50 to 57, P60 to 67, P70 to 73, VIL1 P80 to 86, P93, P96, P97 to 37, PA0 to A7 RESET , NMI , P40 to 41, P87, P90 to 92, P94, P95 VIL2 VIL3 VIL4 VIH 0.3 VCC 0.3 Vcc 2.7 to 5.5 V 0.25 VCC 0.3 0.2 VCC Vcc 4.5 V 2.2 2.0 V Vcc < 4.5 V EA , AM8/ 16 X1 AD0 to 15 Input High Voltage P20 to 27, P32 to 37, P42, P50 to 57, P60 to 67, P70 to 73, VIH1 P80 to 86, P93, P96, P97 to 37, PA0 to A7 RESET , NMI , P40 to 41, P87, P90 to 92, P94, P95 Vcc VIH2 VIH3 VIH4 2.7 to 5.5 V 0.7 VCC Vcc 0.3 0.75 VCC VCC 0.3 0.8 VCC EA , AM8/ 16 X1 Note: Typical values are for Ta 25 C and Vcc 5 V unless other wise noted. 91CW11-249 2003-03-31 TMP91CW11 4.2 DC Characteristic (2/2) (Vss Parameter Output Low Voltage (except PA0 to PA5) 0 V, Ta 40 to 85C) Min Typ. (Note 1) Max 0.45 Symbol VOL Condition I OL 1.6 mA (Vcc 2.7 to 5.5 V) VOL 1.0 V (Vcc 3 V VOL 1.0 V (Vcc 5 V 10%) 10%) Unit V 7 mA 16 2.4 V 4.2 Output Low Current (PA0 to 5) IOLA VOH1 Output High Voltage VOH2 I OH 400 A (Vcc 3 V 10%) I OH 400 A (Vcc 5 V 10%) V EXT 1.5 V R EXT 1.1 k (Vcc 5 V 10% only) 0.0 0.2 VIN VIN VCC VCC 0.2 Darlington Drive Current (8 Output Pins max.) Input Leakage Current Output Leakage Current Power Down Voltage (at STOP, RAM Back up) RESET Pull Up Resistor IDAR (Note 2) ILI ILO VSTOP 1.0 0.02 0.05 2.0 50 80 3.5 5 10 6.0 150 200 10 mA A V k pF V VIL2 0.2 Vcc, VIH 2 0.8 Vcc Vcc Vcc fc 5V 3V 1 MHz 10% 10% RRST CIO VTH RKL RKH Icc Pin Capacitance Schmitt Width RESET , NMI , P40, P41, P87, P90 0.4 Vcc Vcc Vcc Vcc 5V 3V 5V 3V 10% 10% 10% 10% 10 30 50 100 1.0 80 150 150 300 45 25 15 3 55 40 30 10 20 11 7.5 1.8 200 52 52 40 10 0.2 20 50 to 92, P94, P95 Programmable Pull Down Resistor Programmable Pull Up Resistor NORMAL RUN IDLE2 IDLE1 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 Ta STOP Ta Ta 50C 70C 85C Vcc = 2.7 to 5.5 V Vcc 3 V 10% fs 32.768 kHz (Typ: Vcc 3.0 V) Vcc 3 V 10% fc 12.5 MHz (Typ: Vcc 3.0 V) k Vcc 5 V 10% fc 25 MHz mA 13 7 4 0.8 110 22 14 6 mA A A Note 1: Typical values are for Ta = 25C and Vcc 5 V unlesss otherwise noted. Note 2: I-DAR is guranteed for total of up to 8 ports. 91CW11-250 2003-03-31 TMP91CW11 4.3 AC Characteristics (1) Vcc 5V 10% (fc (fs 4 to 20 MHz) 30 to 34 kHz) Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD n mode) tAWH tAWL tCW tAPH tAPH2 tCP 2.5x 50 2.0x 0 x 2.0x 2.0x 0.5x 2.0x 0 15 40 55 15 40 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x Min 50 40 20 70 15 20 40 25 20 25 50 25 External-bus access isn't supported in over 20 MHz. Variable Max 33.3 s 16 MHz Min 62.5 85 11 24 16 11 23 6 11 38 44 6 3.0x 3.5x 2.0x 55 65 60 85 0 48 85 70 16 3.5x 3.0x 90 80 125 2.5x 120 206 200 200 36 175 200 129 108 100 5 133 154 65 60 0 35 60 45 10 85 70 Max 20 MHz Min 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 Max No. 1 Osc. Period ( 2 CLK width x) Parameter Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 A0 to 23 Valid CLK Hold 4 CLK Valid A0 to 23 Hold 5 A0 to 15 Valid ALE fall 6 ALE fall A0 to 15 Hold 7 ALE High pulse width 8 ALE fall RD/ WR fall 9 RD/ WR rise ALE rise 10 A0 to 15 Valid RD/ WR fall 11 A0 to 23 Valid RD/ WR fall 12 RD/ WR rise A0 to 23 Hold 13 A0 to 15 Valid D0 to 15 input 14 A0 to 23 Valid D0 to 15 input 15 RD fall D0 to 15 input 16 RD Low pulse width 17 RD rise D0 to 15 Hold 18 RD rise A0 to 15 output 19 WR Low pulse width 20 D0 to 15 Valid WR rise 21 WR rise D0 to 15 Hold 22 A0 to 23 Valid 23 A0 to 15 Valid WAIT input (1WAIT WAIT input (1WAIT n mode) 24 RD/ WR fall WAIT Hold (1WAIT n mode) 25 A0 to 23 Valid PORT input 26 A0 to 23 Valid PORT Hold 27 WR rise PORT Valid AC Measuring Conditions * Output Level: High 2.2 V /Low 0.8 V, CL = 50 pF (However CL 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/ W , CLK) * Input Level: High 2.4 V / Low 0.45 V (AD0 to AD15) High 0.8 Vcc / Low 0.2 Vcc (Except for AD0 to AD15) 91CW11-251 2003-03-31 TMP91CW11 (2) Vcc 3V 10% (fc (fs 4 to 12.5 MHz) 30 to 34 kHz) No. 1 Osc. Period ( 2 CLK width x) Parameter Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD n mode) tAWH n mode) tAWL n mode) tCW tAPH tAPH2 tCP x Variable Min 80 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 30 80 35 35 60 35 40 50 50 40 3.0x 3.5x 2.0x 2.0x 0 25 40 120 40 3.5x 3.0x 2.0x 0 2.5x 2.5x 50 200 120 130 100 40 110 125 115 Max 33.3 s 12.5 MHz Min 80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 80 250 200 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 A0 to 23 Valid CLK Hold 4 CLK Valid A0 to 23 Hold 5 A0 to 15 Valid ALE fall 6 ALE fall A0 to 15 Hold 7 ALE High width 8 ALE fall RD/ WR fall 9 RD/ WR rise ALE rise 10 A0 to 15 Valid 11 A0 to 23 Valid RD/ WR fall RD/ WR fall 12 RD/ WR rise A0 to 23 Hold 13 A0 to 15 Valid D0 to 15 input 14 A0 to 23 Valid D0 to 15 input 15 RD fall D0 to 15 input 16 RD Low pulse width 17 RD rise D0 to 15 Hold 18 RD rise A0 to 15 output 19 WR Low pulse width WR rise 2.0x 2.0x 0.5x 20 D0 to 15 Valid 21 WR rise D0 to 15 Hold WAIT input (1WAIT WAIT input (1WAIT WAIT Hold (1WAIT 22 A0 to 23 Valid 23 A0 to 15 Valid 24 RD/ WR fall 25 A0 to 23 Valid PORT input 26 A0 to 23 Valid PORT Hold 27 WR rise PORT Valid AC Measuring Conditions * Output Level: High 0.7 Vcc / Low 0.3 Vcc, CL = 50 pF * Input Level: High 0.9 Vcc / Low 0.1 Vcc 91CW11-252 2003-03-31 TMP91CW11 (1) Read Cycle tOSC X1/XT1 tCLK CLK tAK A0 to 23 tKA CS0 to 2 R/W tAWH tAWL tCW WAIT tAPH tAPH2 Port Input tADH RD tACH tACL tLC A0 to 15 tAL ALE tLL tLA tRR tRSH RD RAS ttADL tCA tRAE tHR D0 to 15 tCL AD0 to 15 91CW11-253 2003-03-31 TMP91CW11 (2) Write Cycle X1/XT1 CLK A0 to 23 CS0 to 2 R/W WAIT Port Output tCP WR, HWR tWW tDW AD0 to 15 A0 to 15 D0 to 15 tWD ALE 91CW11-254 2003-03-31 TMP91CW11 4.4 AD Conversion Characteristics (Vss 0 V, AVcc Vcc, AVss Vss, Ta 40 to 85C) Parameter AD analog reference supply voltage ( ) AD analog reference supply voltage ( ) Analog reference voltage Analog reference voltage Analog input voltage Analog input impedance Analog reference Symbol VREFH VREFL AVCC AVSS VAIN RAIN IREF Test Conditions Vcc 5V 10%, (fc 4 to 25 MHz) Vcc 3V 10%, (fc 4 to 12.5 MHz) Min Typ. Max Unit Vcc 0.2 Vss Vcc 0.2 Vss VREFL Vcc Vss 0.2 Vcc Vss 0.2 VREFH 5 3.7 2.2 5.0 3 3 V k mA A LSB ET 10 Vcc Vcc Vcc Vcc Vcc 5 V 10% 3 V 10% 2.7 to 5.5 V 5 V 10% 3 V 10% 0.02 Note 1: 1LSB (VREFH -VREFL)/2 [V] Note 2: Power supply current ICC from the VCC pin includes the power supply current from the AVCC pin. 4.5 Serial Channel Timing (Serial channel 2, 3 and 4) (1) SCLK Input Mode Parameter SCLK cycle Output Data Rising edge of SCLK SCLK edge* Output Data hold SCLK edge* Input Data hold SCLK edge* effective data input Symbol tSCY tOSS tOHS tHSR tSRD Min 16X tSCY/2 5X 5X 0 tSCY 5X 100 100 Variable Max 50 32.768 MHz (Note) Min Max 488 s 91.5 s 152 s 0 336 s 12.5 MHz Min 1.28 s 190 ns 300 ns 0 780 ns Max 20 MHz Min 0.8 s 100 ns 150 ns 0 450 ns Max * It is rising edge in using rising edge mode and falling edge in using falling edge mode. (2) SCLK Output Mode Parameter SCLK cycle (Programmable) Output Data SCLK rising edge SCLK rising edge Output Data hold SCLK rising edge Input Data hold SCLK rising edge effective data input Symbol tSCY tOSS tOHS tHSR tSRD tSCY 2X 0 tSCY 2X 150 Min 16X 2X 80 150 Variable Max 8192X 32.768 MHz 12.5 MHz (Note) Min Max Min Max 488 s 250 ms 1.28 s 655.36 s 427 s 60 s 0 428 s 970 ns 80 ns 0 970 ns 20 MHz Min 0.8 s 550 ns 20 ns 0 550 ns Max 409.6 s (3) SCLK Input Mode (UART mode) Symbol tSCY tSCYL tSCYH Parameter SCLK cycle Low level SCLK Pulse width High level SCLK Pulse width Variable Min 4X 20 2X 5 2X 5 Max 32.768 MHz (Note) Min 122 s 6s 6s Max 12.5 MHz Min 340 ns 165 ns 165 ns Max 20 MHz Min 220 ns 105 ns 105 ns Max Note: fs is used as system clock or input clock to prescaler. 91CW11-255 2003-03-31 TMP91CW11 Timing Chart for I/O Interface Mode tSCY SCLK tOSS Output Data TxD 0 tOHS 1 2 3 tSRD Input Data RxD Valid Valid tHSR Valid Valid Note: SCLK is reversed in SCLK input falling mode. 91CW11-256 2003-03-31 TMP91CW11 4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7) Parameter Clock Cycle Low level pulse width High level pulse width Symbol tVCK tVCKL tVCKH Variable Min Max 8X 100 4X 40 4X 40 12.5 MHz Min Max 740 360 360 20 MHz Max Unit ns ns ns Min 500 240 240 4.7 Interrupt and Capture (1) NMI , INT0 interrupts Parameter NMI , INT0 Low level pulse width NMI , INT0 High level pulse width Symbol tINTAL tINTAH Min 4X 4X Variable Max 12.5 MHz Min Max 320 320 Min 200 200 20 MHz Max Unit ns ns (2) INT4 to 7 Parameter INT4 to INT7 Low level pulse width INT4 to INT7 High level pulse width Symbol tINTBL tINTBH Variable Min Max 4X 100 4X 100 12.5 MHz Min Max 420 420 Min 300 300 20 MHz Max Unit ns ns 4.8 Serial Bus Interface Timing (1) I2C bus Mode Parameter START command SDA fall Hold time START condition SCL Low level pulse width SCL High level pulse width Data hold time (input) Data set-up time (input) Data hold time (output) Data output SCL Rising edge STOP command SDA falling edge SDA Falling edge SCL Rising edge Set-up time STOP condition Symbol tGSTA tHD: STA tLOW tHIGH tHD: IDAT tSU: IDAT tHD: ODAT tODAT tFSDA tFDRC tSU: STO Min 3X 2nX 2nX n 2 X 8X 0 250 7X 3X 2nX 2nX 16X Variable Typ Unit Max s s s s ns ns s s s s s 11X 2nX tHD: ODAT Note: n value is set by SBICR1 START Command STOP Command SDA tGSTA tLOW tHD:ODAT tODAT tFSDA tFDRC SCL tHIGH tHD:STA tHD:IDAT tSU:IDAT tSU:ST 91CW11-257 2003-03-31 TMP91CW11 (2) Clocked-synchronous 8-bit SIO Mode a. SCK Input Mode Parameter SCK cycle SCK falling edge Output data Input data SCK rising edge Output data hold Input data hold SCK rising edge SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 6X tSCY2/2 6X 0 6X Unit Max s s s ns ns b. SCK Output Mode Parameter SCK cycle SCK falling edge Output data Input data SCK rising edge Output data hold Input data hold SCK rising edge SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 2X tSCY2/2 2X 0 2X Unit Max 211X s s s s ns tSCY2 SCK (Input/Output mode) tOHS2 tOSS2 tISS2 SO (Output data) tHSR2 SI (Input data) 91CW11-258 2003-03-31 TMP91CW11 4.9 Timing Chart for Sirial Channel 0,1 a. SCK input mode Parameter SCK cycle SCK falling edge SCK rising edge SCK rising edge Output data hold Effective data input Input data hold Symbol tSCY tSKDO tSRD tHSR Variable Min 16X 6X tSCY 6X 2X Unit Max ns ns ns ns b. SCK output mode Parameter SCK cycle SCK falling edge SCK rising edge SCK rising edge Output data hold Effective data input Input data hold Symbol tSCY tSKDO tSRD tHSR Variable Min 16X 2X tSCY 2X 2X Unit Max ns ns ns ns tSCY tSCL tSCH SCK tSKDO SO (Output data) tSRD tHSR SI (Input data) Valid Valid Valid Valid 91CW11-259 2003-03-31 TMP91CW11 4.10 SCOUT pin AC characteristics Parameter High-level pulse width VCC 5 V VCC 3 V Low-level pulse width VCC 5 V VCC 3 V 10% 10% tSCL 10% 10% 0.5X 0.5X 10 20 30 20 15 Symbol tSCH Variable Min Max 0.5X 0.5X 10 20 12.5 MHz Min Max 30 20 20 MHz Min Max 15 Unit ns ns ns ns Measurement condition Output level: High 2.2 V / Low 0.8 V, CL tSCH tSCL SCOUT 10 pF 91CW11-260 2003-03-31 TMP91CW11 4.11 Timing Chart for Bus Request (BUSRQ )/Bus Acknowledge ( BUSAK ) (Note 1) CLK tBRC BUSRQ tCBAL tBRC tCBAH BUSAK tBAA AD0 to AD15, A0 to A23, CS0 to CS2, R/W tABA (Note 2) (Note 2) RD, WR, HWR ALE Parameter BUSRQ set-up time to CLK Symbol Min tBRC tCBAL tCBAH tABA tBAA 0 0 120 Variable Max 12.5 MHz Min 120 Max 20 MHz Min 120 Max Unit ns 195 65 ns ns ns ns CLK CLK BUSAK falling edge BUSAK rising edge 1.5X 0.5X 80 80 120 40 0 0 240 80 80 80 0 0 Output Buffer is off to BUSAK BUSAK 80 80 to Output Buffer is on. Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to 0 during Wait cycle. Note 2: This line shows the output buffer is off-state. It doen't indicate the signal level is fixed. Just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level - fix will be delayed. The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal. 91CW11-261 2003-03-31 |
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